200 IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 22, NO. 4, APRIL 2012

A 5 GHz 0.95 dB NF Highly Linear CascodeFloating-Body LNA in 180 nm

SOI CMOS TechnologyAnuj Madan, Member, IEEE, Michael J. McPartlin, Member, IEEE, Christophe Masse, William Vaillancourt, and

John D. Cressler, Fellow, IEEE

Abstract—A 5 GHz CMOS LNA featuring a record 0.95 dBnoise-figure is reported. Using an inductively-degenerated cascodetopology combined with floating-body transistors and high-Qpassives on an SOI substrate, record noise figure and superior lin-earity performance at 5 GHz are obtained. The low-noise amplifier(LNA) achieves up to 11 dB of gain while consuming 12 mW dcpower, and is capable of supporting 802.11a WLAN applications.The impact of SOI body-contact on the LNA RF performance isdescribed and linked to improved intermodulation performance.

Index Terms—Intermodulation distortion, linearity, low-noiseamplifier (LNA), radio-frequency integrated circuits (RFICs),system-on-chip (SoC) CMOS, WLAN.

I. INTRODUCTION

H IGH data rate wireless local area networks (LAN) havefueled the rapid growth of portable electronics. To keep

the overall solution cost of portable devices low, the wirelesstransceiver should be highly integrated with the baseband asa system-on-chip (SoC) solution, preferably using a low-com-plexity CMOS process [1]. Due to the scaling-induced reductionin supply voltage, it has become increasingly difficult to inte-grate the RF front-end on the same chip with the digital base-band circuits, while also obtaining the required RF performance.As a result, “front-end modules” are typically used, which incor-porate performance-critical blocks such as the RF switch and thelow-noise amplifier (LNA) on the receive side, and the poweramplifier (PA) on the transmit side [2]. In a typical radio re-ceiver front-end, the LNA is one of the key components since itdominates the radio sensitivity. The LNA design involves trade-offs between noise-figure (NF), gain, power dissipation, inputmatching, and harmonic content in the output signal. Addingin progressively lower power dissipation constraints inherent tobattery-powered portable applications, a primary challenge inLNA design is achieving simultaneous noise and input matching

Manuscript received May 09, 2011; revised September 27, 2011; acceptedFebruary 02, 2012. Date of publication March 19, 2012; date of current versionApril 11, 2012.

A. Madan and C. Masse are with Skyworks Solutions, Inc., Woburn, MA01801 USA (e-mail: anuj.madan@skyworksinc.com).

M. J. McPartlin and W. Vaillancourt are with Skyworks Solutions, Inc., An-dover, MA 01810 USA.

J. D. Cressler is with the School of Electrical and Computer Engineering,Georgia Institute of Technology, Atlanta, GA 30332-0250 USA.

Color versions of one or more of the figures in this letter are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/LMWC.2012.2187882

at any given amount of power dissipation. Moreover, the ampli-fier’s compression point requirement also imposes a limitationon the LNA transistor size, making the simultaneous noise andinput match even more difficult to achieve in practice.

An integrated 5 GHz LNA implemented in floating bodySOI CMOS technology is described in this letter. The activesilicon layer is isolated from the substrate by buried-oxide andis surrounded by shallow-trench isolation on all sides. Theburied oxide layer combined with the high-substrate resistivitydecrease substrate noise injection by providing isolation fromthe substrate. Due to the low-loss dielectric substrate, SOIinductors have higher self-resonant frequency and qualityfactor than those fabricated on bulk silicon. In this work, the0.18 SOI CMOS technology, originally intended for RFswitch applications [3], allows one to achieve sub-1.0 dB NFfor the 5 GHz LNA. This work reports state-of-the-art noiseperformance, linearity and improved LNA figures-of-merit forsilicon-based 5 GHz LNAs targeting WLAN applications.

II. DESIGN OF THE CMOS LNA

The schematic diagram of the proposed LNA is shown inFig. 1. The LNA employs a cascode topology to realize the re-quired gain and provide isolation between the receive port andthe antenna. The inductive matching elements are a combinationof bondwires and on-chip inductors, and the capacitive elementsare implemented as on-chip MIM capacitors. The isolated SOIsubstrate enables high-Q inductors to minimize the loss throughmatching network. The inductively-degenerated LNA can si-multaneously achieve minimum NF, input impedance matching,and maximum transconductance gain. The input impedance ofthe inductively degenerated LNA can be expressed as

(1)

where is the device transconductance and is the intrinsicgate-to-source capacitance of transistor M1. To match the inputimpedance to 50 , the imaginary part of the impedance canbe eliminated by resonating and at an operatingfrequency of 5 GHz. The real part of the input impedance isshown as

(2)

1531-1309/$31.00 © 2012 IEEE

MADAN et al.: 5 GHZ 0.95 DB NF HIGHLY LINEAR CASCODE FLOATING-BODY LNA 201

Fig. 1. Circuit schematic of the inductively-degenerated cascode LNA.

Fig. 2. Die photograph of the fabricated LNA.

The inductors used are 0.4 nH for Ls, 3.7 nH for Lg, and 2.2 nHfor load inductor; the simulated quality factors, based on electro-magnetic simulations at 5 GHz are 7.8, 22.7, and 20.2, respec-tively. The value of resistance is chosen to ensure uncondi-tionally stable operation of the LNA up to 15 GHz. TransistorsM1 and M2 are sized 128 wide with a minimum gate lengthof 0.18 .

III. EXPERIMENTAL RESULTS

To validate the design and probe the impact of various tech-nology options, the LNA has been fabricated in a 0.18 SOICMOS process, with both floating-body and body-contactedFETs. The die photograph of the proposed LNA is shownin Fig. 2. The active die area of the fully integrated LNAis (excluding the pads). On-chip MIMcapacitors serve to decouple supply. All measurements wereperformed on a FR-4 board after mounting the die directly onthe board.

The measured S-parameters of the floating-body LNAare plotted in Fig. 3. Due to the combination of the on-chipmatching network and the bond-wire inductance, the inputreturn loss is 33 dB at 5 GHz, while the output return loss is13 dB at 5 GHz. A small-signal gain of 11 dB at 5 GHz isobtained with a supply voltage of 1.5 V and total current of8 mA. Due to additional input capacitance associatedwith the body-contacted FET, a slightly different inductor value

at the input gives an input return loss of 22 dB, as shownin Fig. 3.

Fig. 3. S-parameters of floating-body and body-contacted LNA with integratedinput and output matched to 50 �.

Fig. 4. De-embedded NF of the LNA.

The gain of the body-contacted LNA biased at the same cur-rent is reduced to 9.3 dB, primarily because of lower transcon-ductance of the body-contacted device as compared to thefloating body device.

A 0.95 dB NF with an error of is measured acrossfive samples at room-temperature for the floating-body LNAat 5 GHz, as shown in Fig. 4. When the body terminal of theFETs is tied to its source terminal in the body-contacted LNA,the increased gate resistance due to the polysilicon abutting thebody-contact degrades the NF to 1.9 dB at 5 GHz.

Power handling capability of the LNA is critical for WLANapplications in order to avoid LNA compression and preservethe modulated signal received at the front-end. The input 1 dBcompression point for the LNAs was measured to be

, as shown in Fig. 5(a). A two-tone test with equalpower levels at 5.000 GHz and 5.001 GHz was performed tomeasure the input third-order intercept point (IIP3), as shown inFig. 5(b). The floating-body LNA has an IIP3 of 5 dBm whilethe body-contacted LNA has an IIP3 of 6.5 dBm.

Minimum-achievable noise-figure for a body-con-tacted device is 1 dB higher than the floating-body device, as

202 IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 22, NO. 4, APRIL 2012

Fig. 5. (a) Measured input � compression point, and (b) comparison ofmeasured harmonics and IIP3 of the LNAs.

Fig. 6. Simulated �� and extracted � comparison of the LNA input de-vice.

TABLE IPERFORMANCE COMPARISON BETWEEN RECENTLY PUBLISHED LNAS

illustrated in Fig. 6. This is primarily attributed to the highergate-electrode resistance for body-contacted device, which is in-dependent of frequency [8].

To evaluate the performance of the LNAs, different figure-of-merit (FOM) are often used. is the ratio of the gain (in

dB) to the dc power consumption (in mW), which is more com-monly used for comparing low-power LNAs. Furthermore, itcan be expanded to include the NF, IIP3, and operating fre-quency (fc) as follows [9]. A larger FOM is better in all cases

A comparison between the present LNAs and other recentlypublished LNAs is presented in Table I [4]–[9]. It should benoted that all of the LNAs shown are fully integrated withoutoff-chip components. By achieving a 0.95 dB NF while con-suming 12 mW, this LNA exhibits the lowest NF and highest

. Furthermore, the proposed LNA also meets the stringentwireless LAN standards demanding high linearity and power-handling capability for the 802.11a/n standard.

IV. CONCLUSION

We have presented a fully-integrated 5 GHz LNA for802.11a/n WLAN applications. This state-of-the-art LNAfeatures a NF below 1.0 dB and has 11 dB power gain, whileconsuming 12 mW of power and maintaining an input returnloss of 33 dB. The measured input 1 dB compression point at5 GHz is , while IIP3 is 5 dBm. The body-contactedFET LNA performance is compared with the floating-bodyLNA. Due to the additional polysilicon gate resistance, thebody-contacted FET based LNA is seen to have higher NF.

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