9/11/2015 1 vlsi physical design automation prof. david pan [email protected] office: aces 5.434...
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VLSI Physical Design Automation
Prof. David Pan
Office: ACES 5.434
Misc. Topics and Conclusion
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Other Design Styles: FPGA• Field Programmable Gate Array• First introduced by Xilinx in 1984.• Pre-fabricated devices and interconnect, which are
programmable by user.• Advantages:
– short turnaround time.– low manufacturing cost.– fully testable.– re-programmable.
• Particularly suitable for prototyping, low or medium-volume production, device controllers, etc.
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Comparison of Design Styles
Full-CustomStandard
CellGate Array FPGA
Cell size variable fixed height fixed fixed
Cell type variable variable fixedprogramma
ble
Cell placement variable in row fixed fixed
Interconnections variable variable variableprogramma
ble
Fabrication layers
all layersall
layersrouting
layers only no layers
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Comparison of Design Styles
Full-Custom Standard Cell Gate Array FPGA
Area compactcompact to moderate
moderate large
Performance highhigh
to moderatemoderate low
Design cost high medium medium low
Time-to-market long medium medium short
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Programming Technologies
• SRAM to control pass transistor / multiplexer• EPROM – UV light Erasable PROM• EEPROM – Electrically Erasable PROM• Antifuses – One time programmable
• They are different in ease of manufacturing, manufacturing reliability, area, ON and OFF resistance, parasitic capacitance, power consumption, re-programmability.
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Typical FPGA Architecture• Consists of: Logic modules, Routing resources, and
I/O modules.
Logic ModuleLogic Module
IO ModuleIO Module
Routing TracksRouting Tracks& Switch boxes& Switch boxes
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FPGA Architecture Examples
LogicLogicModuleModule
Array-based ModelArray-based Model Row-based ModelRow-based Model
Sea-of-Gates ModelSea-of-Gates Model Hierarchical ModelHierarchical Model
RoutingRoutingresourcesresourcesoverlayedoverlayedon logicon logicmodulesmodules
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Two Types of Logic Modules
Look-Up Table (LUT) based:• A block of RAM to store the truth table.• A k-input 1-output functions needs 2k bits.• k is usually 5 or 6.
Multiplexer based: e.g., f=ABC+ABCe.g., f=ABC+ABC
CCBBAA
AABB
ff
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Two Types of Switchboxes• First Type:First Type:
• Second Type:Second Type:
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Several Segmentation Models• Non-Segmentation Model:
• Uniform Segmentation Model:
11 44 00 00 22 00 00 33 00 55 00 00 00 00
00 00 00 11 00 00 44 00 22 00 33 00 00 55
ConnectingConnecting
Not connectingNot connecting
11 44 00 00 22 00 00 33 00 55 00 00 00 00
00 00 00 11 00 00 44 00 22 00 33 00 00 55
Fuse orFuse orProgrammableProgrammable
switchswitch
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Several Segmentation Models
• Uniform Staggered Segmentation Model:
• Non-uniform Staggered Segmentation Model:
11 44 00 00 22 00 00 33 00 55 00 00 00 00
00 00 00 11 00 00 44 00 22 00 33 00 00 55
11 44 00 00 22 00 00 33 00 55 00 00 00 00
00 00 00 11 00 00 44 00 22 00 33 00 00 55
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Comparison of Segmentation Models
• The segmented model provides better utilization of routing resources.
• However, segmented model uses more fuses or programmable switches.
• The delay of a net is directly proportional to the # of fuses or programmable switches in the route– Manhattan-distance based delay model does NOT work
anymore– The segmented model is slower in general
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Physical Design of FPGAs
• Very different from other design styles• Architecture dependent:
– LUT or Multiplexer in logic modules– Type of switchboxes used– Type of segmentation model used– ......
• Physical Design:– Partitioning– Floorplanning/Placement– Routing
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Partitioning
• Want to partition the circuit such that each partition (cluster) can be implemented by a logic module.
• Also called Clustering.• # of I/O pins, not cluster sizes, is important. (For multiplexer based logic modules, functionality of
clusters is also important.)
Example:Example:Using 4-LUTsUsing 4-LUTs
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Placement
• Assign clusters formed during partitioning to logic modules of FPGA.
• The problem is the same as gate-array placement.
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Routing
• Global routing:– Similar to global routing in other design styles.– Minimize wire length and balance densities.
• Detailed routing:– Very different from other design styles.– Different algorithms for different segmentation models.– Channels and switchboxes have fixed capacities.
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Structured ASIC
• New buzz word, but essentially gate array– Mask reconfigurable – Not field reconfigurable
• Between FPGA and standard cells– Balance delay/performance and mask cost
• Only programmable once– by vias (e.g., Via-Programmable Gate Array – VPGA)
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Physcial Design Automationof MCMs and SiPs
Physcial Design Automationof MCMs and SiPs
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MCM and SiP
• Multi-Chip Module• System in package (SiP)
– Different package styles– Thermal consideration for 3D
• Alternative packaging approach for high performance systems.
• Similar to PCB and IC layout problems, but– PCB layout tools cannot handle the dense and complex wiring
structure of MCM.– IC layout tools cannot handle the complex electrical, thermal
and geometrical constraints.
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Example: Pentium
Substrate size:Substrate size:32mmx32mm32mmx32mm
Package size:Package size:43mmx43mm43mmx43mm(4 times smaller)(4 times smaller)
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Partitioning
• Partitioning a circuit so that each sub-circuit can be implemented into a chip.
• MCM may contain as many as 100 chips.• Need to consider timing constraints and thermal
constraints• In addition, also need to consider traditional I/O
constraints and area constraints.
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Placement
• # of components is much less as compared to IC placement.
• However, need to consider timing constraints and thermal constraints (as bare chips are placed close to each other).
• Routing is done in routing layers, not between chips.• So no routing region needs to be allocated.
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Routing
• Main objective is to satisfy timing constraints.• Another objective is to minimize # of routing layers, not to
minimize routing area.– Cost is directly proportional to # of layers
• Crosstalk, skin effect and parasitic effect are important considerations.
• Wires are of smaller pitch and more dense than PCB layout.
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EE382 V -- Conclusions
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What Have Been Taught?
• Introduced different problems in Physical Design.• Numerous algorithms which are different in terms of
– design styles– objectives– constraints– techniques– optimality– efficiency– robustness– .....
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What Is Important?• Understand the problems
– How to formulate the problems, represent the constraints, solutions, etc.
– Reasonable assumptions/abstractions
• Know fundamental algorithms to solve the problems.• However, the world keeps on changing:
– technology– objectives– constraints– requirement on solution quality– computational power
• It is more important to learn how to think – formulate the problem– solve it smartly
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Problem Solving Techniques
• Greedy Algorithm• Simulated Annealing/Genetic Algorithm• Mathematical Programming
– Linear, Quadratic, Integer Linear, geometric, posynomial, …
• Dynamic Programming• Reduction to graph problems
– min-cut, max-cut, shortest path, longest path, bipartite matching, minimum spanning tree, etc.
• Divide-and-Conquer• Many different heuristics• ....
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System SpecificationSystem Specification
Micro-ArchitecturalMicro-ArchitecturalSpecificationSpecification
Timing & RelationshipTiming & RelationshipBetween UnitsBetween Units
RTL (in HDL)RTL (in HDL)
NetlistNetlist
Architectural Design
Functional Design
Logic Design
Circuit Design
VLSI Design CycleVLSI Design Cycle
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NetlistNetlist
LayoutLayout
MaskMask
Packaged ChipsPackaged Chips
Physical Design
Fabrication
PackagingAnd Testing
VLSI Design CycleVLSI Design Cycle
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Conventional Physical Design Cycle
PartitioningPartitioning
Floorplanning & PlacementFloorplanning & Placement
RoutingRouting
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Technology Trend and Challenges
Source:ITRS’03
Interconnect determines the overall performanceInterconnect determines the overall performance In addition: noise, power => In addition: noise, power => Design closureDesign closure Furthermore: manufacturability => Furthermore: manufacturability => Manufacturing closureManufacturing closure
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New Trends in Physical Design
• For nanometer IC designs, interconnect dominates• New physical effects
– Noise: coupling, P/G noise– Power: leakage, power/voltage islands– Manufacturability: yield, printability– Reliability, …
• More and more vertical integration– Logic synthesis coupled with physical design– Interconnect optimizations & design planning– Physical design as a bridge between lower level modeling
and higher level optimization/planning
• Existing CAD algorithms are far away from optimal
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Check points
Problem solving skills on underlying physical design algorithms
Know what’s behind the scene of CAD tools Know the trend and critique ability if given a new
research paper Project study of a topic of your choice and
implementation (through class project) Presentation skill Paper writing and job preparation