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Scaling at the End of Moore’s Law

David Z. PanDept. of Electrical and Computer Engineering

The University of Texas at Austin

dpan@ece.utexas.edu

http://www.cerc.utexas.edu/utda

PROFIT Workshop – Dec. 22, 2009

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Moore’s Law & CMOS Scaling

1980 1990 2000 2010 2020

10

1

0.1

um

[Courtesy Intel]

X

[Moore 1965] Lithography Gap!

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Scaling is Certainly Not Easy

Litho CMP

Random defects Etch

-nce

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You Probably Have Seen This!

[Courtesy Synopsys]

DFM toRescue

Scaling, though challenged, still pushing ahead! Quite Amazing… Yes, we can!

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Scaling at the End Vertically – 3D ICNew devices/materials

› E.g., Optical interconnect, high-K, strain siliconMulti-core, many core, networks-on-chip…….But still life in continuing pushing the envelope,

22nm, 16nm, 11nm, 8nm (ITRS)› Computational Scaling› Double Patterning › Emerging Nanolithography› …

E.g., Intel sees no problem for another decade

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Computational Scaling

Scaling by massive computational power› Fast computers to help design faster computers

Computational lithography for nanolithography systems

› Computationally reverse-engineeringElectronic design automation (EDA) eco-system

to close the gaps› Current tools are still very sub-optimal› Synergistic Process-Layout-Circuit Co-Optimization› Parallel, multi-core, GPU, domain-specific, FPGA…

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Computational Lithography

[Singh+, SPIE’08)

Intel’s Pixelated Mask

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Synergistic CAD to the RescueCAD tools still very suboptimalNeed good levers at different levels of

abstraction for process/layout/circuit co-opt.

“Give me a lever, and I can optimize your billion transistor design.” - EDA’s Lever (model/rule)

“Give me a place to stand on, and I can move the earth.” - Archimedes’ Lever LeverEDA

Design

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Process Modeling

How complicated?

or simple can it be?

Key Issues:› Accuracy vs. Fidelity (Elmore-like)› Design-oriented vs. process-oriented

' ' ' '1 1 0 0 0 0 0 0 0 0 0

' ' ' '1 0 1 0 1 0 1 0 0 0 0 0

( ) ( ) ( ) ( )

( ) ( )

II x y J x x y y F x y F x y

K x x y y K x x y y dx dy dx dy

Litho model: Hopkins eqn

)_

1(*_2

densityMetal

ThicknessCu CMP model:

[Cho+, ICCAD’06]

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Prediction & Prescription

Layout!Hotspot!

Prediction: e.g., data mining, machine learning [Ding+, ICICDT’09] (Best Student Paper)

Prescription: only work with patterns that are printable Robustness Design: tolerant to variations/aging, e.g. ,

[Chakraborty+, DATE 2009] (Best IP Award)

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“Next” Generation Lithography

EUV

mindp

193i w/ DPL

Nanoimprint

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Double Patterning Lithography

For 22nm and 16nm, the industry most likely will adopt double patterning lithography (DPL)

A key problem is overlay control› Double exposures, masks, …

Intelligent CAD solution to compensate the unwanted overlay effects or even take advantage of them!

E.g., [Yang et al, ASPDAC’2010] (Best Paper Award Nomination)

› A new layout decomposition framework

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A Faster & Versatile Framework

[Yang et al., ASPDAC 2010] proposed a new graph-theoretic, multi-objective layout decomposition framework

Consider new objectives› Density balancing › Overlay compensation

In addition to conventional metrics› Decomposability› Stitch minimization

Very efficient for full chip mindp

Stitch

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Overlay Compensation

1st patterning

C1 -∆C1 C2 -∆C2

2nd patterning 2nd patterning

1st patterning

Decomposition Without Overlay Compensation

1st patterning

2nd patterning

C1 -∆C1 C2 +∆C2

2nd patterning

1st patterning

Decomposition With Overlay Compensation (for Timing Variation Reduction)

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The number of stitches in layout decomposition is equal to the cut size of the bi-partitioning problem in graph theory.

Theorem 1 : Min-Cut Based Stitch Minimization

Color Assignment – Heuristic Solution

Example of Graph Based Stitch Minimization

Minimize : A X + X Z + Y Z + E Y + 2(Ā X) + 2(Ē Y)⊕ ⊕ ⊕ ⊕ ⊕ ⊕

Ā(20)A(17)

X(9)

E(15)

Y(9)

Ē(17)

1 2

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Z(5)

1

1

Constraint: (A, Ā) and (E, Ē) are repulsive pairs.

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Balancing Density is Easy

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Color0 Area=32 (35%) Color1 Area=60 (65%)

Ā(20)A(17)

X(9)

E(15)

Y(9)

Ē(17)

1 2

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Z(5)

1

1

Color0 Area=46 (50%)

Color1 Area=46 (50%)

Ā(20)A(17)

X(9)

E(15)Y(9)

Ē(17)

12

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Z(5)1

1

Min-Stitch Coloring Balanced Coloring

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Compensate Overlay Effect

Cc1

Rd

Cc2

Cc3

R1 R2 R3 R4

R5

R7

R6

Cc1

Rd

Cc2

Cc4

Cc3

R1 R2 R3 R4

R5

# of Stitch=2

R7

R6TDD

TDD constraints insertion

y2’

x1

x2

y1

y2

x1’

x2’

y1’

i1

i2

i3

1

1

1

1

1

1

w

w

Cc4

x1

x1’ x2’

x2

y1 y1’

y2

i1 i2

i3

y2’Relative coloring

y2’

x1

x2

y1

y2

x1’

x2’

y1’

i1

i2

i3

1

1

1

1

1

1

color0 color1

without TDD constraints

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Experimental Results

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[Yang et al., ASPDAC 2010] very fast (cf. ILP) It handles density balancing nicely

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Reduction of Timing Variations

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How about post-16nm?

Triple patterningQuadruple patterning

› Intel 7nm

Extreme Ultra-Violet Lithography (13.5nm)Massively e-beam direct writeNanoimprint

[Intel, July 2009]

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50 Years Ago, …

There's Plenty of Room at the Bottom

- An Invitation to Enter a New Field of Physics

Richard P. Feynman, 1959

Still

The Moore, The Better!