9 interrupts

Upload: shanty85

Post on 06-Apr-2018

230 views

Category:

Documents


0 download

TRANSCRIPT

  • 8/3/2019 9 Interrupts

    1/25

    ECE473/573Microprocessor System Design, Dr. Shiue

    1

    Interrupt

  • 8/3/2019 9 Interrupts

    2/25

    ECE473/573Microprocessor System Design, Dr. Shiue

    2

    Interrupt Programming

    An interrupt is an external or internal event that interrupts

    the microcontroller to inform it that a device needs its

    service.

    A single 8051 can serve several devices. There are 2 ways

    to do that

    Interrupt: interrupt service routine (ISR) or interrupt handler

    polling

    8051 Several devices

  • 8/3/2019 9 Interrupts

    3/25

    ECE473/573Microprocessor System Design, Dr. Shiue

    3

    Interrupt

    Whenever any device needs its service, the device notifies

    the microcontroller by sending it an interrupt signal.

    Upon receiving an interrupt signal, the microcontrollerinterrupts whatever it is doing and serves the devices.

  • 8/3/2019 9 Interrupts

    4/25

    ECE473/573Microprocessor System Design, Dr. Shiue

    4

    Polling

    The microcontroller continuously monitors the status of a

    given device; when the condition is met, it performs the

    service.

    After that, it moves on the monitor the next device until

    everyone is serviced.

    8051

    Monitoring

    Device 1

    Device 2

    :

    This is NOT efficient!!

  • 8/3/2019 9 Interrupts

    5/25

    ECE473/573Microprocessor System Design, Dr. Shiue

    5

    Interrupt vs. Polling

    The interrupt method is preferable because the polling

    method wastes much of the microcontrollers time by

    polling devices that do not need service.

    For interrupt method, during the waiting, you could do

    other tasks and when the TF is raised, it will interrupt the

    microcontroller in what it is doing.

    Monitoring by polling method

    Target: JNB TF, Target

    Doing waiting, you could not do anything!!

  • 8/3/2019 9 Interrupts

    6/25

    ECE473/573Microprocessor System Design, Dr. Shiue

    6

    Interrupt Service Routine (ISR)

    For every interrupt, there is a fixed location in memory that

    holds the address of its ISR.

    The group of memory location set aside to hold theaddresses of ISRs is called Interrupt Vector Table

    Interrupt Vector Table

    0023 ~ 002A(8B)Serial COM interruptRI and TI

    001B ~ 0022(8B)Timer 1 InterruptTF1

    13 (P3.3)0013 ~ 001A (8B)External H/W Interrupt 1INT1

    000B ~ 00012(8B)Timer 0 InterruptTF0

    12 (P3.2)0003 ~ 000A (8B)External H/W Interrupt 0INT0

    90000 ~ 0002 (3B)Reset interruptReset

    PinROM locationsDescriptionInterrupt

  • 8/3/2019 9 Interrupts

    7/25

    ECE473/573Microprocessor System Design, Dr. Shiue

    7

    Reset Interrupt

    There are 3 bytes of ROM spaces assigned to the reset pin.

    0000

    00010002

    For this reason, in our program, we put LJMP as the firstinstruction and redirect the processor away from the

    interrupt vector table.ORG 0

    LJMPMain 3-byte instruction located to0000, 0001, and 0002

    ORG 30H

    Main:

    Reset

    0000

    0001

    0002

    0030

    0031

    0032

  • 8/3/2019 9 Interrupts

    8/25

    ECE473/573Microprocessor System Design, Dr. Shiue

    8

    Interrupt Enable (IE) Register

    Enabling and disabling an interrupt

    EA:

    EA=0 No interrupt

    EA=1 Interrupt

    ET2 is for Timer 2 (in 8052)

    ES: enable/disable the serial port interrupt

    ET1 (Timer 1 interrupt) and ET0 (Timer 0 interrupt)

    EX1 (External interrupt: INT1) and EX0 (Externalinterrupt INT0)

    EX0ET0EX1ET1ESET2-EAIE

  • 8/3/2019 9 Interrupts

    9/25

    ECE473/573Microprocessor System Design, Dr. Shiue

    9

    Example

    Q1: Show the instructions to (a) enable the serial interrupt,

    timer 0 interrupt, and external H/W interrupt 1, and (b)

    disable the timer 0 interrupt, and (c) show how to disable

    all the interrupt with a single instruction.

  • 8/3/2019 9 Interrupts

    10/25

    ECE473/573Microprocessor System Design, Dr. Shiue

    10

    Timer Interrupts

    TF0 interrupt (for example of Timer 0)

    Steps

    1. IE register is enable for ET0.

    2. When the timer rolls over, TF0 is raised.

    3. Microcontroller is interrupted and jump to the interrupt vector table to

    serve the ISR. In this way, the microcontroller can do other things until

    it is notified that the timer 0 has rolled over.

    1 000BH

    Jump toTF0

    EX0ET0

    =1

    EX1ET1ESET2-EA

    =1

    IE

  • 8/3/2019 9 Interrupts

    11/25

    ECE473/573Microprocessor System Design, Dr. Shiue

    11

    Timer Interrupts

    Step 1:

    ORG 0

    LJMP Main

    ORG 30H

    Main:

    Step 2:

    Timer 0 000BH

    Step 3: (EA=1, and ET0 =1 for Timer 0)

    MOV IE, #10000010B

  • 8/3/2019 9 Interrupts

    12/25

    ECE473/573Microprocessor System Design, Dr. Shiue

    12

    Example

    Q2: Write a program that continuously gets 8-bit data from

    P0 and sends it to P1 while simultaneously creating a

    square-wave of 200us period on Pin P2.1 (Use timer 0 to

    create the square wave. Assume XTAL=11.0592MHz) Q3: Rewrite Q2 to create a square wave as below

    Q4: Write a program for Timer 0 to generate a square wave

    of 50Hz frequency on P1.2 (a) using polling method, and(b) using interrupt method.

    1085us

    15us

  • 8/3/2019 9 Interrupts

    13/25

    ECE473/573Microprocessor System Design, Dr. Shiue

    13

    External H/W Interrupt

    !INT0 (0003 ~000AH) and !INT1 (0013 ~ 001AH)

    Level-Triggered Interrupt

    Normally high (!INT0 and !INT1) when if a low signal applied

    to them, it trigger the interrupt. The low signal must be removed before RETI

    !INT0 12 P3.2

    !INT1 13 P3.3

  • 8/3/2019 9 Interrupts

    14/25

    ECE473/573Microprocessor System Design, Dr. Shiue

    14

    Example

    Q5: Assume that the INT1 pin is connected to a switch that

    is normally high whenever it goes low, it should turn on an

    LED. The LED is connected to P1.3 and is normally off

    when it is turned on it should stay on for a fraction of asecond. As long as the switch is pressed low, the LED

    should stay ON.

  • 8/3/2019 9 Interrupts

    15/25

    ECE473/573Microprocessor System Design, Dr. Shiue

    15

    Sampling of the low level-triggered interrupt

    The INTx pin must be held in a low state until the start of

    the execution of ISR This duration is around 4 machine

    cycle but no more.

    The INTx must be brought back to high before theexecution of RETI

    IT0 (TCON.0) and IT1 (TCON.2) are both 0, making

    external interrupts level-triggered.

  • 8/3/2019 9 Interrupts

    16/25

    ECE473/573Microprocessor System Design, Dr. Shiue

    16

    Edge-Triggered Interrupt

    SETB TCON.0 (IT0)

    SETB TCON.2 (IT1)

    INT1

    Pulse generator

    (edge-triggered)

    P1.3 LED

  • 8/3/2019 9 Interrupts

    17/25

    ECE473/573Microprocessor System Design, Dr. Shiue

    17

    Example

    Q6: Assume that P3.3 (INT1) is connected to a pulse

    generator, write a program in which the falling edge of the

    pulse will send a high to P1.3, which connected to a LED

    (or buzzer). In other words, the LED is turned ON andOFF at the same rate as the pulses are applied to the INT1

    pin (edge-triggered).

  • 8/3/2019 9 Interrupts

    18/25

    ECE473/573Microprocessor System Design, Dr. Shiue

    18

    Sampling of the edge-triggered interrupt

    The falling edge is located by 8051 and is held by the

    TCON register.

    Interrupt-in-service flags

    TCON.1 (IE0) hold the latch falling edge for INT0

    TCON.3 (IE1) hold the latch falling edge for INT1

    IE0=1 or IE1=1 in Interrupt service. They are only

    cleared by RETI, soCLR TCON.1

    CLR TCON.3

    are NOT necessary!!!

  • 8/3/2019 9 Interrupts

    19/25

    ECE473/573Microprocessor System Design, Dr. Shiue

    19

    Serial Communication Interrupt

    Remind the SCON register

    TI=1 SBUF is ready to transfer the next byte.

    RI=1 The received byte needs to be picked up before it

    is lost.

    Enable Serial comm. Interupt SETB IE.4

    RITIRB8TB8RENSM2SM1SM0SCON

    EX0ET0EX1ET1ES=1

    ET2-EA

    =1IE

  • 8/3/2019 9 Interrupts

    20/25

    ECE473/573Microprocessor System Design, Dr. Shiue

    20

    Serial Communication Interrupt

    The serial interrupt is used mainly for receiving data and is

    never used for sending data serially.

    Phone

    Call

    Receiving

  • 8/3/2019 9 Interrupts

    21/25

    ECE473/573Microprocessor System Design, Dr. Shiue

    21

    Example

    Q7: Write a program in which the 8051 reads data from P1and writes it to P2 continuously while giving a copy of it tothe serial com port to be transferred serially.

    (XTAL=11.0592MHz, and baud rate = 9600) Q8: Write a program in which the 8051 gets data from P1and send it to P2 continuously while incoming data fromthe serial port is sent to P0. (XTAL=11.0592MHz, and

    baud rate = 9600) Q9: Write a program using interrupts to do the following

    (a) receive data serially and sent it to P0, (b) have P1 portread and transmitted serially, and a copy given to P2, and

    (c) make timer 0 generate a square wave of 5KHzfrequency on P0.1 (XTAL=11.0592MHz, and baud rate =4800)

  • 8/3/2019 9 Interrupts

    22/25

    ECE473/573Microprocessor System Design, Dr. Shiue

    22

    Interrupt Flags

    For Serial Communication Interrupt

    RI (SCON.0)

    TI (SCON.1)

    For Timer 0 and Timer 1 interrupt TF0 (TCON.5 for Timer 0)

    TF1 (TCON.7 for Timer 1)

    For external HW interrupt IE0 (TCON.1 for INT0)

    IE1 (TCON.3 for INT1)

  • 8/3/2019 9 Interrupts

    23/25

    ECE473/573Microprocessor System Design, Dr. Shiue

    23

    Interrupt Priority

    High to Low Priority

    INT0

    TF0

    INT1

    TF1

    RI + TI

  • 8/3/2019 9 Interrupts

    24/25

    ECE473/573Microprocessor System Design, Dr. Shiue

    24

    Interrupt Priority (IP) Register

    IP register

    PT2 (timer 2 in 8052)

    PS (for serial Port)

    PT1 (for timer 1)

    PX1 (for external interrupt 1)

    PT0 (for timer 0)

    PX0 (for external interrupt 0)

    PX0PT0PX1PT1PSPT2--IP

  • 8/3/2019 9 Interrupts

    25/25

    ECE473/573Microprocessor System Design, Dr. Shiue

    25

    Example

    Q10: (a) program the IP register to assign the highest

    priority to INT1 then (b) discuss what happen if INT0 and

    TF0 are activated at the same time. Assume the interrupts

    are both edge-triggered. Q11: Assume that after reset, the interrupt priority is set by

    the instruction MOV IP, #00001100B. Discuss the

    sequence in which the interrupts are serviced.