7-5 microoperation an elementary operations performed on data stored in registers or in memory....
TRANSCRIPT
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7-5 MicrooperationAn elementary operations performed on
data stored in registers or in memory.Transfer ArithmeticLogic: perform bit manipulation on data in
registerBitwise AND, Bitwise OR ….
Shift
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Arithmetic Microoperations
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Arithmetic Microoperations
The control variable X selects the operation, and the control variable K1 loads the result in to R1.
211:1 RRRKX
1211:1 RRRKX
Fig. 7.6 Implementation
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Logic Microoperationsmanipulate the bits stored in a registerconsider each bit in register separately
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Logic MicrooperationsMask: allow us to deal with some specific bits
R1: 10101101 10101011 (data)R2: 00000000 11111111 (mask) 00000000 10101011 <=R1
←R1^R2
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Logic Microoperations
R1: 10101101 10101011 (data)R2: 11111111 00000000 (mask) 11111111 10101011 <=R1
←R1ˇR2
R1: 10101101 10101011 (data)R2: 11111111 00000000 (mask) 01010010 10101011 <=R1
←R1 R2
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Shift Microoperationsshift left/shift rightincoming bit/outgoing bit
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7-6 Microoperation on A single RegisterMultiplexer-based transferif (K1=1) then (R0 ← R1) else if (K2=1) then
(R0 ← R2)
K1: R0 ← R1, R0 ← R2:21KK
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Multiplexer-based transfer
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Multiplexer-based transfer •Generalization of Multiplexer selection for n sources
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Shift RegistersSerial input (SI)Serial output (SO)
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Shift Register with parallel load
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Shift Register with Parallel Load
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Bidirectional Shift Register
DQSS
QQSS
QQSS
:
sr:
sl:
01
01
01
One stage diagram
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Bidirectional Shift Register
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Ripple counterStructure similar to ripple adder
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Synchronous Binary Counter -Serial gating
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Synchronous Binary Counter -Parallel gating
Only one AND gate delay
Four AND gates delay
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Up-Down Binary Counter
))((
))((
))((
21021033
101022
0011
00
ENSQQQSQQQQD
ENSQQSQQQD
ENSQSQQD
ENQD
A
A
A
A
Homework #1
Prove it and draw the logic diagram
S=0 up counter
S=1 down counter
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Binary counter with parallel load
Fig. 7-14
It is a case of the up-down counter in the previous slide.
(why? what case?)
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BCD counterA divide-by-N counter (modulo-N counter)
is a counter goes through a repeated sequence of N states
Fig. 7-15
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Another BCD counter
81
4218188
2144
8122
11
)(
QQCOY
QQQQQQD
QQQD
QQQD
QD
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Modulo 6 counter
CBD
CD
BAD
C
B
A
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Modulo 6 counter
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Homework #2Problem 7-15 with modified sequence
0,3,2,1,5,4,7Run the simulation for the designed circuit
by using Quartus IIDeal with the unused state as don’t care Test the circuit when the unused state
occurs (on paper)