singlecycle-22017/02/14 · single-cycle datapath for arithmetic and logical instructions executing...
TRANSCRIPT
2/14/17
1
SamiraKhanUniversityofVirginia
Feb14,2017
IntrotoMicroarchitecture:Single-Cycle
CS3330
AGENDA• Reviewfromlastlecture
• Single-cyclemicroarchitecture
• Evaluationofsingle-cyclemicroarchitecture
2
RecapofLastWeek• ISAbasicsandtradeoffs
• Instructionlength• Uniformvs.non-uniformdecode• Numberofregisters• Addressingmodes• RISCvs.CISCproperties
3
ANoteonRISCvs.CISC• Usually,…
• RISC• Simpleinstructions• Fixedlength• Uniformdecode• Fewaddressingmodes
• CISC• Complexinstructions• Variablelength• Non-uniformdecode• Manyaddressingmodes
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Y86-64InstructionSet#1Byte
pushq rA A 0 rA F
jXX Dest 7 fn Dest
popq rA B 0 rA F
call Dest 8 0 Dest
cmovXX rA, rB 2 fn rA rB
irmovq V, rB 3 0 F rB V
rmmovq rA, D(rB) 4 0 rA rB D
mrmovq D(rB), rA 5 0 rA rB D
OPq rA, rB 6 fn rA rB
ret 9 0
nop 1 0
halt 0 0
0 1 2 3 4 5 6 7 8 9
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AVeryBasicInstructionProcessingEngine• Single-cyclemachine
• Whatistheclockcycletimedeterminedby?• Whatisthecriticalpath ofthecombinationallogicdeterminedby?
AS’ AS(State)CombinationalLogic
6
InstructionProcessing“Stage”• Instructionsareprocessedunderthedirectionofa“controlunit” stepbystep.
• Instructionstage:Sequenceofstepstoprocessaninstruction• Fundamentally,therearefivephases:
• Fetch• Decode• Execute• Memory• StoreResult
• Notallinstructionsrequireallstages
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Single-cyclevs.Multi-cycle:Control&Data• Single-cyclemachine:
• Controlsignalsaregeneratedinthesameclockcycleastheoneduringwhichdatasignalsareoperatedon
• Everythingrelatedtoaninstructionhappensinoneclockcycle(serializedprocessing)
• Multi-cyclemachine:• Controlsignalsneededinthenextcyclecanbegeneratedinthecurrentcycle
• Latencyofcontrolprocessingcanbeoverlappedwithlatencyofdatapath operation(moreparallelism)
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ASingle-CycleMicroarchitectureACloserLook
Let’sStartwiththeStateElements• Dataandcontrolinputs
Registerfile
A
B
W dstW
srcA
valA
srcB
valB
valW
ALU
Operation
A
B
MUX0
1
PC
InstructionMem
InstrAddr
InstructionDataMem
AddressReadData
WriteData
RegWrite
MemWrite
MemRead
MUXSelect
10
InstructionProcessing• 6(5)genericsteps
• Instructionfetch(IF)• Instructiondecodeandregisteroperandfetch(ID/RF)• Execute/Evaluatememoryaddress(EX/AG)• Memoryoperandfetch(MEM)• Store/writeback result(WB)• PCUpdate
Registerfile
ValA
rB
DestE
valBALU
PC
InstructionMem
InstrAddr Instruction
DataMem
Address ReadData
WriteData
rA
ValE
IF ID/RF EX/AG WBMEM
newPC
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InstructionProcessing• 6(5)genericsteps
• Instructionfetch(IF)• Instructiondecodeandregisteroperandfetch(ID/RF)• Execute/Evaluatememoryaddress(EX/AG)• Memoryoperandfetch(MEM)• Store/writeback result(WB)• PCUpdate
Registerfile
ValA
rB
DestE
valBALU
PC
InstructionMem
InstrAddr Instruction
DataMem
Address ReadData
WriteData
rA
ValE
IF ID/RF EX/AG WBMEM
newPC
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InstructionProcessing• 6(5)genericsteps
• Instructionfetch(IF)• Instructiondecodeandregisteroperandfetch(ID/RF)• Execute/Evaluatememoryaddress(EX/AG)• Memoryoperandfetch(MEM)• Store/writeback result(WB)• PCUpdate
Registerfile
ValA
rB
DestE
valBALU
PC
InstructionMem
InstrAddr Instruction
DataMem
Address ReadData
WriteData
rA
ValE
IF ID/RF EX/AG WBMEM
newPC
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InstructionProcessing• 6(5)genericsteps
• Instructionfetch(IF)• Instructiondecodeandregisteroperandfetch(ID/RF)• Execute/Evaluatememoryaddress(EX/AG)• Memoryoperandfetch(MEM)• Store/writeback result(WB)• PCUpdate
Registerfile
ValA
rB
DestE
valBALU
PC
InstructionMem
InstrAddr Instruction
DataMem
Address ReadData
WriteData
rA
ValE
IF ID/RF EX/AG WBMEM
newPC
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Single-CycleDatapathforArithmeticandLogical
Instructions
ExecutingArith./LogicalOperation
•Fetch• Read2bytes
•Decode• Readoperandregisters
•Execute• Performoperation• Setconditioncodes
•Memory• Donothing
•Writeback• Updateregister
•PCUpdate• IncrementPCby2
OPq rA, rB 6 fn rA rB
ifMEM[PC]==OPq rA, rBR[rB]¬R[rB] opR[rA]PC¬ PC+2
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StageComputation:Arith/Log.Ops
• Formulateinstructionexecutionassequenceofsimplesteps
• Usesamegeneralformforallinstructions
OPq rA,rBicode:ifun¬M1[PC]rA:rB¬M1[PC+1]
valP¬ PC+2
FetchReadinstructionbyteReadregisterbyte
ComputenextPCvalA¬ R[rA]valB¬ R[rB]
Decode ReadoperandAReadoperandB
valE¬ valBOPvalASetCC
Execute PerformALUoperationSetconditioncoderegisterMemory
R[rB]¬ valEWrite
backWritebackresult
PC¬ valPPCupdate UpdatePC
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ALUDatapath
**Basedonoriginalfigurefrom[P&HCO&D,COPYRIGHT2004Elsevier.ALLRIGHTSRESERVED.]
ifMEM[PC]==OPq rA, rBR[rB]¬R[rB] opR[rA]PC¬ PC+2
Combinationalstateupdatelogic
IF ID EX MEM WB
Registerfile
ValB
rA
DestE
valAALU
PC
InstructionMem
InstrAddr Instruction
DataMem
Address ReadData
WriteData
rB
ValE
ADD
RegWrite ALU
OP
PC
2
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ALUDatapath
**Basedonoriginalfigurefrom[P&HCO&D,COPYRIGHT2004Elsevier.ALLRIGHTSRESERVED.]
ifMEM[PC]==OPq rA, rBR[rB]¬R[rB] opR[rA]PC¬ PC+2
Combinationalstateupdatelogic
IF ID EX MEM WB
Registerfile
ValB
rA
DestE
valAALU
PC
InstructionMem
InstrAddr Instruction
DataMem
Address ReadData
WriteData
rB
ValE
ADD
RegWrite ALU
OP
PC
2
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Single-CycleDatapathforDataMovementInstructions
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Executingmrmovq (LoadfromMemtoReg)
•Fetch• Read10bytes
•Decode• Readoperandregisters
•Execute• Computeeffectiveaddress
•Memory• Readfrommemory
•Writeback• WritetoRegister
•PCUpdate• IncrementPCby10
6 fn rA rB
mrmovq D(rB),rA
D
ifMEM[PC]==mrmovq Disp (rB), rAEA=Disp +R[rB]R[rA]¬MEM[EA]PC¬ PC+10 21
StageComputation:mrmovq
• UseALUforaddresscomputation
mrmovq D(rB),rAicode:ifun¬M1[PC]rA:rB¬M1[PC+1]valC¬M8[PC+2]valP¬ PC+10
Fetch
ReadinstructionbyteReadregisterbyteReaddisplacementDComputenextPC
valB¬ R[rB]Decode
ReadoperandBvalE¬ valB +valC
ExecuteComputeeffectiveaddress
valM¬ M8[valE]Memory WritevaluetomemoryR[rA]¬ valMWrite
backPC¬ valPPCupdate UpdatePC
ifMEM[PC]==mrmovq Disp (rB), rAEA=Disp +R[rB]R[rA]¬MEM[EA]PC¬ PC+10 22
Ld Datapath
ifMEM[PC]==mrmovq Disp (rB), rAEA=Disp +R[rB]R[rA]¬MEM[EA]PC¬ PC+10
Combinationalstateupdatelogic
IF ID EX MEM WB
Registerfile
ValA
rB
DestE
valBALU
PC
InstructionMem
InstrAddr Instruction
DataMem
Address ReadData
WriteData
rA
ValE
ADD
RegWrite ALU
OP
MUX
MUXSelect
MUX
rB
rA
MUX
D
FromALU
FromMem10
PC
23
Ld Datapath:CalculatetheEffectiveAddress
ifMEM[PC]==mrmovq Disp (rB), rAEA=Disp +R[rB]R[rA]¬MEM[EA]PC¬ PC+10
Combinationalstateupdatelogic
IF ID EX MEM WB
Registerfile
ValA
rB
DestE
valBALU
PC
InstructionMem
InstrAddr Instruction
DataMem
Address ReadData
WriteData
rA
ValE
ADD
RegWrite ALU
OP
MUX
MUXSelect
MUX
rB
rA
MUX
D
FromALU
FromMem10
PC
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ifMEM[PC]==mrmovq Disp (rB), rAEA=Disp +R[rB]R[rA]¬MEM[EA]PC¬ PC+10
Combinationalstateupdatelogic
IF ID EX MEM WB
Registerfile
ValA
rB
DestE
valBALU
PC
InstructionMem
InstrAddr Instruction
DataMem
Address ReadData
WriteData
rA
ValE
ADD
RegWrite ALU
OP
MUX
MUXSelect
MUX
rB
rA
MUX
D
FromALU
FromMem10
PC
Ld Datapath:LoadedmemoryneedstobewrittentotheRegisterFile
25
ifMEM[PC]==mrmovq Disp (rB), rAEA=Disp +R[rB]R[rA]¬MEM[EA]PC¬ PC+10
Combinationalstateupdatelogic
IF ID EX MEM WB
Registerfile
ValA
rB
DestE
valBALU
PC
InstructionMem
InstrAddr Instruction
DataMem
Address ReadData
WriteData
rA
ValE
ADD
RegWrite ALU
OP
MUX
MUXSelect
MUX
rB
rA
MUX
D
FromALU
FromMem10
PC
Ld Datapath:NeedtheDestinationRegister
26
ifMEM[PC]==mrmovq Disp (rB), rAEA=Disp +R[rB]R[rA]¬MEM[EA]PC¬ PC+10
Combinationalstateupdatelogic
IF ID EX MEM WB
Registerfile
ValA
rB
DestE
valBALU
PC
InstructionMem
InstrAddr Instruction
DataMem
Address ReadData
WriteData
rA
ValE
ADD
RegWrite ALU
OP
MUX
MUXSelect
MUX
rB
rA
MUX
D
FromALU
FromMem10
PC
Ld Datapath:UpdatePC
27
Executingrmmovq (Stfromreg toMemory)
•Fetch• Read10bytes
•Decode• Readoperandregisters
•Execute• Computeeffectiveaddress
•Memory• Writetomemory
•Writeback• Donothing
•PCUpdate• IncrementPCby10
rmmovq rA,D(rB)
4 0 rA rB D
ifMEM[PC]==rmmovq rA, Disp (rB)EA=Disp +R[rB]MEM[EA]¬R[rA]PC¬ PC+10 28
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StageComputation:rmmovq
• UseALUforaddresscomputation
rmmovq rA,D(rB)icode:ifun¬M1[PC]rA:rB¬M1[PC+1]valC¬M8[PC+2]valP¬ PC+10
Fetch
ReadinstructionbyteReadregisterbyteReaddisplacementDComputenextPC
valA¬ R[rA]valB¬ R[rB]
DecodeReadoperandAReadoperandB
valE¬ valB+valCExecute
Computeeffectiveaddress
M8[valE]¬ valAMemory WritevaluetomemoryWrite
backPC¬ valPPCupdate UpdatePC
ifMEM[PC]==rmmovq rA, Disp (rB)EA=Disp +R[rB]MEM[EA]¬R[rA]PC¬ PC+10 29
StDatapath
ifMEM[PC]==rmmovq rA, Disp (rB)EA=Disp +R[rB]MEM[EA]¬R[rA]PC¬ PC+10
Combinationalstateupdatelogic
IF ID EX MEM WB
Registerfile
ValA
rB
DestE
valBALU
PC
InstructionMem
InstrAddr Instruction
DataMem
Address ReadData
WriteData
rA
ValE
ADD
RegWrite ALU
OP
MUX
MUXSelect
MUX
rB
rA
MUX
D
FromALU
FromMem
PC
10
MemWrite
30
StDatapath:Calculatetheeffectiveaddress
ifMEM[PC]==rnmovq rA, Disp (rB)EA=Disp +R[rB]MEM[EA]¬R[rA]PC¬ PC+10
Combinationalstateupdatelogic
IF ID EX MEM WB
Registerfile
ValA
rB
DestE
valBALU
PC
InstructionMem
InstrAddr Instruction
DataMem
Address ReadData
WriteData
rA
ValE
ADD
RegWrite ALU
OP
MUX
MUXSelect
MUX
rB
rA
MUX
D
FromALU
FromMem
PC
10
MemWrite
31
ifMEM[PC]==rnmovq rA, Disp (rB)EA=Disp +R[rB]MEM[EA]¬R[rA]PC¬ PC+10
Combinationalstateupdatelogic
IF ID EX MEM WB
Registerfile
ValA
rB
DestE
valBALU
PC
InstructionMem
InstrAddr Instruction
DataMem
Address ReadData
WriteData
rA
ValE
ADD
RegWrite ALU
OP
MUX
MUXSelect
MUX
rB
rA
MUX
D
FromALU
FromMem
PC
10
MemWrite
StDatapath:Storedataneedstoreachmemory
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ifMEM[PC]==rnmovq rA, Disp (rB)EA=Disp +R[rB]MEM[EA]¬R[rA]PC¬ PC+10
Combinationalstateupdatelogic
IF ID EX MEM WB
Registerfile
ValA
rB
DestE
valBALU
PC
InstructionMem
InstrAddr Instruction
DataMem
Address ReadData
WriteData
rA
ValE
ADD
RegWrite ALU
OP
MUX
MUXSelect
MUX
rB
rA
MUX
D
FromALU
FromMem
PC
10
MemWrite
StDatapath:UpdatePC
33
Executingirmovq (Moveimm toReg)
•Fetch• Read10bytes
•Decode• Readoperandregisters
•Execute• Add0toV
•Memory• Donothing
•Writeback• WriteVtorB
•PCUpdate• IncrementPCby10
irmovq V, rB
3 0 F rB V
ifMEM[PC]==irmovq V, rBR[rB]¬ V + 0PC¬ PC+10
34
StageComputation:irmovq
• UseALUforaddresscomputation
irmovq V,rBicode:ifun¬M1[PC]rA:rB¬M1[PC+1]valC¬M8[PC+2]valP¬ PC+10
Fetch
ReadinstructionbyteReadregisterbyteReaddisplacementDComputenextPC
Decode
valE¬ 0 +valCExecute
Computeeffectiveaddress
R[rB]¬ valAMemory WritevaluetomemoryWrite
backPC¬ valPPCupdate UpdatePC
ifMEM[PC]==irmovq V, rBR[rB]¬ V + 0PC¬ PC+10
35
irmov Datapath:Option1
ifMEM[PC]==irmovq V, rBR[rB]¬ V + 0PC¬ PC+10 Combinational
stateupdatelogic
IF ID EX MEM WB
Registerfile
ValA
rB
DestE
valBALU
PC
InstructionMem
InstrAddr Instruction
DataMem
Address ReadData
WriteData
rA
ValE
ADD
RegWrite ALU
OP
MUX
MUXSelect
MUX
rB
rA
MUX
D
FromALU
FromMem
MUX
0
PC
MemWrite
10
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irmov Datapath Option1:readregisterandaddzero
ifMEM[PC]==irmovq V, rBR[rB]¬ V + 0PC¬ PC+10 Combinational
stateupdatelogic
IF ID EX MEM WB
Registerfile
ValA
rB
DestE
valBALU
PC
InstructionMem
InstrAddr Instruction
DataMem
Address ReadData
WriteData
rA
ValE
ADD
RegWrite ALU
OP
MUX
MUXSelect
MUX
rB
rA
MUX
D
FromALU
FromMem
MUX
0
PC
MemWrite
10
37
irmov Datapath Option1:Writeback value
ifMEM[PC]==irmovq V, rBR[rB]¬ V + 0PC¬ PC+10 Combinational
stateupdatelogic
IF ID EX MEM WB
Registerfile
ValA
rB
DestE
valBALU
PC
InstructionMem
InstrAddr Instruction
DataMem
Address ReadData
WriteData
rA
ValE
ADD
RegWrite ALU
OP
MUX
MUXSelect
MUX
rB
rA
MUX
D
FromALU
FromMem
MUX
0
PC
MemWrite
10
38
ifMEM[PC]==irmovq V, rBR[rB]¬ V + 0PC¬ PC+10 Combinational
stateupdatelogic
IF ID EX MEM WB
Registerfile
ValA
rB
DestE
valBALU
PC
InstructionMem
InstrAddr Instruction
DataMem
Address ReadData
WriteData
rA
ValE
ADD
RegWrite ALU
OP
MUX
MUXSelect
MUX
rB
rA
MUX
D
FromALU
FromMem
MUX
0
PC
MemWrite
10
irmovDatapathOption1:Writebackvalue
39
irmov Datapath Option1:UpdatePC
ifMEM[PC]==irmovq V, rBR[rB]¬ V + 0PC¬ PC+10 Combinational
stateupdatelogic
IF ID EX MEM WB
Registerfile
ValA
rB
DestE
valBALU
PC
InstructionMem
InstrAddr Instruction
DataMem
Address ReadData
WriteData
rA
ValE
ADD
RegWrite ALU
OP
MUX
MUXSelect
MUX
rB
rA
MUX
D
FromALU
FromMem
MUX
0
PC
MemWrite
10
40
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irmov Datapath Option2
ifMEM[PC]==irmovq V, rBR[rB]¬ VPC¬ PC+10 Combinational
stateupdatelogic
IF ID EX MEM WB
Registerfile
ValA
rB
DestE
valBALU
PC
InstructionMem
InstrAddr Instruction
DataMem
Address ReadData
WriteData
rA
ValE
ADD
RegWrite ALU
OP
MUX
MUXSelect
MUX
rB
rA
MUX
D
FromALU
FromMem
PC
MemWrite
10
41
irmov Datapath:Option2
ifMEM[PC]==irmovq V, rBR[rB]¬ VPC¬ PC+10 Combinational
stateupdatelogic
IF ID EX MEM WB
Registerfile
ValA
rB
DestE
valBALU
PC
InstructionMem
InstrAddr Instruction
DataMem
Address ReadData
WriteData
rA
ValE
ADD
RegWrite ALU
OP
MUX
MUXSelect
MUX
rB
rA
MUX
D
FromALU
FromMem
PC
MemWrite
10
42
• Tradeoffsbetweenoption1andoption2?
• Extra2-to-1MUX?• 3-to-1MUX?Whatisthecostforn-to-1MUX?• Wirelength?• Generality?
43
Executingrrmovq (MovefromReg toReg)
•Fetch• Read2bytes
•Decode• ReadoperandregisterrA
•Execute• Add0toval rA
•Memory• Donothing
•Writeback• Writeval rA torB
•PCUpdate• IncrementPCby2
2 0 rA rB
rrmovq rA, rB
ifMEM[PC]==rrmovq rA, rBR[rB]¬ R[rA]+0PC¬ PC+2 44
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StageComputation:rrmovqrrmovq rA,rBicode:ifun¬M1[PC]rA:rB¬M1[PC+1]
valP¬ PC+2
Fetch
ReadinstructionbyteReadregisterbyteReaddisplacementDComputenextPC
ValA¬ R[rA]Decode
valE¬ 0 +valAExecute
Computeeffectiveaddress
Memory WritevaluetomemoryR[rB]ß valEWrite
backPC¬ valPPCupdate UpdatePC
ifMEM[PC]==rrmovq rA, rBR[rB]¬ R[rA]+0PC¬ PC+2 45
rrmov Datapath:Option1
ifMEM[PC]==rrmovq rA, rBR[rB]¬ R[rA]+0PC¬ PC+2 Combinational
stateupdatelogic
IF ID EX MEM WB
Registerfile
ValA
rB
DestE
valBALU
PC
InstructionMem
InstrAddr Instruction
DataMem
Address ReadData
WriteData
rA
ValE
ADD
RegWrite ALU
OP
MUX
MUXSelect
MUX
rB
rA
MUX
D
FromALU
FromMem
MUX
0
PC
MemWrite
2
46
rrmov Datapath:Option1
ifMEM[PC]==rrmovq rA, rBR[rB]¬ R[rA]+0PC¬ PC+2 Combinational
stateupdatelogic
IF ID EX MEM WB
Registerfile
ValA
rB
DestE
valBALU
PC
InstructionMem
InstrAddr Instruction
DataMem
Address ReadData
WriteData
rA
ValE
ADD
RegWrite ALU
OP
MUX
MUXSelect
MUX
rB
rA
MUX
D
FromALU
FromMem
MUX
0
PC
MemWrite
2
47
rrmov Datapath:Option1
ifMEM[PC]==rrmovq rA, rBR[rB]¬ R[rA]+0PC¬ PC+2 Combinational
stateupdatelogic
IF ID EX MEM WB
Registerfile
ValA
rB
DestE
valBALU
PC
InstructionMem
InstrAddr Instruction
DataMem
Address ReadData
WriteData
rA
ValE
ADD
RegWrite ALU
OP
MUX
MUXSelect
MUX
rB
rA
MUX
D
FromALU
FromMem
MUX
0
PC
MemWrite
2
48
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rrmov Datapath:Option1
ifMEM[PC]==rrmovq rA, rBR[rB]¬ R[rA]+0PC¬ PC+2 Combinational
stateupdatelogic
IF ID EX MEM WB
Registerfile
ValA
rB
DestE
valBALU
PC
InstructionMem
InstrAddr Instruction
DataMem
Address ReadData
WriteData
rA
ValE
ADD
RegWrite ALU
OP
MUX
MUXSelect
MUX
rB
rA
MUX
D
FromALU
FromMem
MUX
0
PC
MemWrite
2
49
rrmov Datapath:Option2
ifMEM[PC]==rrmovq rA, rBR[rB]¬ R[rA]PC¬ PC+2 Combinational
stateupdatelogic
IF ID EX MEM WB
Registerfile
ValA
rB
DestE
valBALU
PC
InstructionMem
InstrAddr Instruction
DataMem
Address ReadData
WriteData
rA
ValE
ADD
RegWrite ALU
OP
MUX
MUXSelect
MUX
rB
rA
MUX
D
FromALU
FromMem
PC
MemWrite
10 ?50
Single-CycleDatapathforControlFlowInstructions
ExecutingJumps
•Fetch• Read9bytes• IncrementPCby9
•Decode• Donothing
•Execute• Determinewhethertotake
branchbasedonjumpconditionandconditioncodes
•Memory• Donothing
•Writeback• Donothing
•PCUpdate• SetPCtoDest ifbranchtakenor
toincrementedPCifnotbranch
jXX Dest 7 fn Dest
XX XXfallthru:
XX XXtarget:
Nottaken
Taken
jmp 7 0
jle 7 1
jl 7 2
je 7 3
jne 7 4
jge 7 5
jg 7 6
ifMEM[PC]==jmp Destif(cond)PCß Dest elsePCß PC+9 52
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StageComputation:Jumps
• Computebothaddresses• Choosebasedonsettingofconditioncodesandbranchcondition
jXXDesticode:ifun¬M1[PC]
valC¬M8[PC+1]valP¬ PC+9
Fetch
Readinstructionbyte
ReaddestinationaddressFallthroughaddress
Decode
Cnd¬ Cond(CC,ifun)Execute
Takebranch?MemoryWrite
backPC¬ Cnd ?valC :valPPCupdate UpdatePC
ifMEM[PC]==jmp Destif(cond)PCß Dest elsePCß PC+9 53
Jump
ifMEM[PC]==jmp DestPCß Dest Combinational
stateupdatelogic
IF ID EX MEM WB
Registerfile
ValA
rB
DestE
valBALU
PC
InstructionMem
InstrAddr Instruction
DataMem
Address ReadData
WriteData
rA
ValE
ADD
RegWrite ALU
OP
MUX
MUXSelect
MUX
rB
rA
MUX
D
FromALU
FromMem
MUX
0
PC
MemWrite
2 MUX
109
MUX
D
54
UnconditionalJump
ifMEM[PC]==jmp DestPCß Dest Combinational
stateupdatelogic
IF ID EX MEM WB
Registerfile
ValA
rB
DestE
valBALU
PC
InstructionMem
InstrAddr Instruction
DataMem
Address ReadData
WriteData
rA
ValE
ADD
RegWrite ALU
OP
MUX
MUXSelect
MUX
rB
rA
MUX
D
FromALU
FromMem
MUX
0
PC
MemWrite
2 MUX
109
MUX
D
55
ConditionalJump
ifMEM[PC]==jmp Destif(cond)PCß Dest elsePCß PC+9 Combinational
stateupdatelogic
IF ID EX MEM WB
Registerfile
ValA
rB
DestE
valBALU
PC
InstructionMem
InstrAddr Instruction
DataMem
Address ReadData
WriteData
rA
ValE
ADD
RegWrite ALU
OP
MUX
MUXSelect
MUX
rB
rA
MUX
D
FromALU
FromMem
MUX
0
PC
MemWrite
2 MUX
109
MUX
D
56
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Executingcall
•Fetch• Read9bytes• IncrementPCby9
•Decode• Readstackpointer
•Execute• Decrementstackpointerby8
•Memory• WriteincrementedPCtonew
valueofstackpointer
•Writeback• Updatestackpointer
•PCUpdate• SetPCtoDest
call Dest 8 0 Dest
XX XXreturn:
XX XXtarget:
ifMEM[PC]==call DestMEM[R[rsp]-8]ß PC+9R[rsp]ß R[rsp]- 8PCß Dest
57
StageComputation:call
• UseALUtodecrementstackpointer• StoreincrementedPC
call Desticode:ifun¬M1[PC]
valC¬M8[PC+1]valP¬ PC+9
Fetch
Readinstructionbyte
ReaddestinationaddressComputereturnpoint
valB¬ R[%rsp]Decode
ReadstackpointervalE¬ valB +–8
ExecuteDecrementstackpointer
M8[valE]¬ valPMemory WritereturnvalueonstackR[%rsp]¬ valEWrite
backUpdatestackpointer
PC¬ valCPCupdate SetPCtodestination
ifMEM[PC]==call DestMEM[R[rsp]-8]ß PC+9R[rsp]ß R[rsp]- 8PCß Dest
58
Call
ifMEM[PC]==call DestMEM[R[rsp]-8]ß PC+9R[rsp]ß R[rsp]- 8PCß Dest
Combinationalstateupdatelogic
IF ID EX MEM WB
Registerfile
ValA
rB
DestE
valBALU
PC
InstructionMem
InstrAddr Instruction
DataMem
Address
ReadData
WriteData
rA
ValE
ADD
RegWrite ALU
OP
MUX
MUXSelect
MUX
rB
rA
MUX
DFromALU
FromMem
MUX
0
PC
MemWrite
2 MUX
109
MUX
D
MUX
rB
rsp
rsp
8MUX
FromPC+x
59
Call:Decrementstackpointer
ifMEM[PC]==call DestMEM[R[rsp]-8]ß PC+9R[rsp]ß R[rsp]- 8PCß Dest
Combinationalstateupdatelogic
IF ID EX MEM WB
Registerfile
ValA
rB
DestE
valBALU
PC
InstructionMem
InstrAddr Instruction
DataMem
Address
ReadData
WriteData
rA
ValE
ADD
RegWrite ALU
OP
MUX
MUXSelect
MUX
rB
rA
MUX
DFromALU
FromMem
MUX
0
PC
MemWrite
2 MUX
109
MUX
D
MUX
rB
rsp
rsp
8MUX
FromPC+x
60
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16
Call:Writereturnaddress tomemory
ifMEM[PC]==call DestMEM[R[rsp]-8]ß PC+9R[rsp]ß R[rsp]- 8PCß Dest
Combinationalstateupdatelogic
IF ID EX MEM WB
Registerfile
ValA
rB
DestE
valBALU
PC
InstructionMem
InstrAddr Instruction
DataMem
Address
ReadData
WriteData
rA
ValE
ADD
RegWrite ALU
OP
MUX
MUXSelect
MUX
rB
rA
MUX
DFromALU
FromMem
MUX
0
PC
MemWrite
2 MUX
109
MUX
D
MUX
rB
rsp
rsp
8MUX
FromPC+x
61
Call:Updatersp intheregisterfile
ifMEM[PC]==call DestMEM[R[rsp]-8]ß PC+9R[rsp]ß R[rsp]- 8PCß Dest
Combinationalstateupdatelogic
IF ID EX MEM WB
Registerfile
ValA
rB
DestE
valBALU
PC
InstructionMem
InstrAddr Instruction
DataMem
Address
ReadData
WriteData
rA
ValE
ADD
RegWrite ALU
OP
MUX
MUXSelect
MUX
rB
rA
MUX
DFromALU
FromMem
MUX
0
PC
MemWrite
2 MUX
109
MUX
D
MUX
rB
rsp
rsp
8MUX
FromPC+x
62
Call:UpdatePC
ifMEM[PC]==call DestMEM[R[rsp]-8]ß PC+9R[rsp]ß R[rsp]- 8PCß Dest
Combinationalstateupdatelogic
IF ID EX MEM WB
Registerfile
ValA
rB
DestE
valBALU
PC
InstructionMem
InstrAddr Instruction
DataMem
Address
ReadData
WriteData
rA
ValE
ADD
RegWrite ALU
OP
MUX
MUXSelect
MUX
rB
rA
MUX
DFromALU
FromMem
MUX
0
PC
MemWrite
2 MUX
109
MUX
D
MUX
rB
rsp
rsp
8MUX
FromPC+x
63
Executingret
•Fetch• Read1byte
•Decode• Readstackpointer
•Execute• Incrementstackpointerby8
•Memory• Readreturnaddressfromold
stackpointer
•Writeback• Updatestackpointer
•PCUpdate• SetPCtoreturnaddress
ret 9 0
XX XXreturn:
ifMEM[PC]==retPCßMEM[R[rsp]]R[rsp]ß R[rsp]+8 64
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StageComputation:ret
• UseALUtoincrementstackpointer• Readreturnaddressfrommemory
ret
icode:ifun¬M1[PC]
Fetch
Readinstructionbyte
valA¬ R[%rsp]valB¬ R[%rsp]
DecodeReadoperandstackpointerReadoperandstackpointer
valE¬ valB +8Execute
Incrementstackpointer
valM¬M8[valA]Memory ReadreturnaddressR[%rsp]¬ valEWrite
backUpdatestackpointer
PC¬ valMPCupdate SetPCtoreturnaddress
ifMEM[PC]==retPCßMEM[R[rsp]]R[rsp]ß R[rsp]+8 65
ifMEM[PC]==retPCßMEM[R[rsp]]R[rsp]ß R[rsp]+8
Ret
Combinationalstateupdatelogic
IF ID EX MEM WB
Registerfile
ValA
rB
DestE
valBALU
PC
InstructionMem
InstrAddr Instruction
DataMem
Address
ReadData
WriteData
rA
ValE
ADD
RegWrite ALU
OP
MUX
MUXSelect
MUX
rB
rA
MUX
DFromALU
FromMem
MUX
0
PC
MemWrite
2 MUX
109
MUX
D
MUX
rB
rsp
rsp
8
MUX
FromPC+x
MUX
66
ifMEM[PC]==retPCßMEM[R[rsp]]R[rsp]ß R[rsp]+8
Ret:Incrementstackpointer
Combinationalstateupdatelogic
IF ID EX MEM WB
Registerfile
ValA
rB
DestE
valBALU
PC
InstructionMem
InstrAddr Instruction
DataMem
Address
ReadData
WriteData
rA
ValE
ADD
RegWrite ALU
OP
MUX
MUXSelect
MUX
rB
rA
MUX
DFromALU
FromMem
MUX
0
PC
MemWrite
2 MUX
109
MUX
D
MUX
rB
rsp
rsp
8
MUX
FromPC+x
MUX
67
ifMEM[PC]==retPCßMEM[R[rsp]]R[rsp]ß R[rsp]+8
Ret:ReadreturnaddressfromMemory
Combinationalstateupdatelogic
IF ID EX MEM WB
Registerfile
ValA
rB
DestE
valBALU
PC
InstructionMem
InstrAddr Instruction
DataMem
Address
ReadData
WriteData
rA
ValE
ADD
RegWrite ALU
OP
MUX
MUXSelect
MUX
rB
rA
MUX
DFromALU
FromMem
MUX
0
PC
MemWrite
2 MUX
109
MUX
D
MUX
rB
rsp
rsp
8
MUX
FromPC+x
MUX
68
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ifMEM[PC]==retPCßMEM[R[rsp]]R[rsp]ß R[rsp]+8
Ret:UpdatePC
Combinationalstateupdatelogic
IF ID EX MEM WB
Registerfile
ValA
rB
DestE
valBALU
PC
InstructionMem
InstrAddr Instruction
DataMem
Address
ReadData
WriteData
rA
ValE
ADD
RegWrite ALU
OP
MUX
MUXSelect
MUX
rB
rA
MUX
DFromALU
FromMem
MUX
0
PC
MemWrite
2 MUX
109
MUX
D
MUX
rB
rsp
rsp
8
MUX
FromPC+x
MUX
69
ifMEM[PC]==retPCßMEM[R[rsp]]R[rsp]ß R[rsp]+8
Ret:Updatersp
Combinationalstateupdatelogic
IF ID EX MEM WB
Registerfile
ValA
rB
DestE
valBALU
PC
InstructionMem
InstrAddr Instruction
DataMem
Address
ReadData
WriteData
rA
ValE
ADD
RegWrite ALU
OP
MUX
MUXSelect
MUX
rB
rA
MUX
DFromALU
FromMem
MUX
0
PC
MemWrite
2 MUX
109
MUX
D
MUX
rB
rsp
rsp
8
MUX
FromPC+x
MUX
70
Single-CycleDatapath forStackOperations
Executingpopq
•Fetch• Read2bytes
•Decode• Readstackpointer
•Execute• Incrementstackpointerby8
•Memory• Readfromoldstackpointer
•Writeback• Updatestackpointer• Writeresulttoregister
•PCUpdate• IncrementPCby2
popq rA b 0 rA 8
72
ifMEM[PC]==popR[rA]ßMEM[R[rsp]]R[rsp]ß R[rsp]+8
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StageComputation:popq
• UseALUtoincrementstackpointer• Mustupdatetworegisters
• Poppedvalue• Newstackpointer
popq rAicode:ifun¬M1[PC]rA:rB¬M1[PC+1]
valP¬ PC+2
Fetch
ReadinstructionbyteReadregisterbyte
ComputenextPCvalA¬ R[%rsp]valB¬ R[%rsp]
DecodeReadstackpointerReadstackpointer
valE¬ valB +8Execute
Incrementstackpointer
valM¬M8[valA]Memory ReadfromstackR[%rsp]¬ valER[rA]¬ valM
Write
backUpdatestackpointerWritebackresult
PC¬ valPPCupdate UpdatePC
73
ifMEM[PC]==popR[rA]ßMEM[R[rsp]]R[rsp]ß R[rsp]+8
ifMEM[PC]==popR[rA]ßMEM[R[rsp]]R[rsp]ß R[rsp]+8
Pop
Combinationalstateupdatelogic
IF ID EX MEM WB
Registerfile
ValA
rB
DestE
valBALU
PC
InstructionMem
InstrAddr Instruction
DataMem
Address
ReadData
WriteData
rA
ValE
ADD
RegWrite ALU
OP
MUX
MUXSelect
MUX
rB
rA
MUX
DFromALU
FromMem
MUX
0
PC
MemWrite
2 MUX
109
MUX
D
MUX
rB
rsp
rsp
8
MUX
FromPC+x
MUX
74
Pop
Registerfile
ValA
rB
DestE
valBALU
PC
InstructionMem
InstrAddr Instruction
DataMem
Address
ReadData
WriteData
rA
ValE
ADD
RegWrite ALU
OP
MUX
MUXSelect
MUX
rB
rA
MUX
D FromALU
FromMem
MUX
0
MemWrite
2 MUX
109
MUX
D
MUX
rB
rsp
rsp
8
MUX
FromPC+x
MUX
DestM ValM
75
Pop:Incrementstackpointer
Registerfile
ValA
rB
DestE
valBALU
PC
InstructionMem
InstrAddr Instruction
DataMem
Address
ReadData
WriteData
rA
ValE
ADD
RegWrite ALU
OP
MUX
MUXSelect
MUX
rB
rA
MUX
D FromALU
FromMem
MUX
0
MemWrite
2 MUX
109
MUX
D
MUX
rB
rsp
rsp
8
MUX
FromPC+x
MUX
DestM ValM
76
ifMEM[PC]==popR[rA]ßMEM[R[rsp]]R[rsp]ß R[rsp]+8
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20
Pop:ReadpushedvaluefromMemory
Registerfile
ValA
rB
DestE
valBALU
PC
InstructionMem
InstrAddr Instruction
DataMem
Address
ReadData
WriteData
rA
ValE
ADD
RegWrite ALU
OP
MUX
MUXSelect
MUX
rB
rA
MUX
D FromALU
FromMem
MUX
0
MemWrite
2 MUX
109
MUX
D
MUX
rB
rsp
rsp
8
MUX
FromPC+x
MUX
DestM ValM
77
ifMEM[PC]==popR[rA]ßMEM[R[rsp]]R[rsp]ß R[rsp]+8
Pop:Movethevaluetoregisterfile
Registerfile
ValA
rB
DestE
valBALU
PC
InstructionMem
InstrAddr Instruction
DataMem
Address
ReadData
WriteData
rA
ValE
ADD
RegWrite ALU
OP
MUX
MUXSelect
MUX
rB
rA
MUX
D FromALU
FromMem
MUX
0
MemWrite
2 MUX
109
MUX
D
MUX
rB
rsp
rsp
8
MUX
FromPC+x
MUX
DestM ValM
78
ifMEM[PC]==popR[rA]ßMEM[R[rsp]]R[rsp]ß R[rsp]+8
Pop:Writeback rsp value
Registerfile
ValA
rB
DestE
valBALU
PC
InstructionMem
InstrAddr Instruction
DataMem
Address
ReadData
WriteData
rA
ValE
ADD
RegWrite ALU
OP
MUX
MUXSelect
MUX
rB
rA
MUX
D FromALU
FromMem
MUX
0
MemWrite
2 MUX
109
MUX
D
MUX
rB
rsp
rsp
8
MUX
FromPC+x
MUX
DestM ValM
79
ifMEM[PC]==popR[rA]ßMEM[R[rsp]]R[rsp]ß R[rsp]+8
Pop
Registerfile
ValA
rB
DestE
valBALU
PC
InstructionMem
InstrAddr Instruction
DataMem
Address
ReadData
WriteData
rA
ValE
ADD
RegWrite ALU
OP
MUX
MUXSelect
MUX
rB
rA
MUX
D FromALU
FromMem
MUX
0
MemWrite
2 MUX
109
MUX
D
MUX
rB
rsp
rsp
8
MUX
FromPC+x
MUX
DestM ValM
80
2/14/17
21
Pop
Registerfile
ValA
rB
DestE
valBALU
PC
InstructionMem
InstrAddr Instruction
DataMem
Address
ReadData
WriteData
rA
ValE
ADD
RegWrite ALU
OP
MUX
MUX
rB
rA
D FromALUFromMem
MUX
0
MemWrite
2 MUX
109
MUX
D
MUX
rB
rsp
rsp
8
MUX
FromPC+x
MUX
DestM ValM
81
EvaluatingtheSingle-CycleMicroarchitecture
ASingle-CycleMicroarchitecture• Isthis agoodidea/design?
• Whenisthisagooddesign?
• Whenisthisabaddesign?
• Howcanwedesignabettermicroarchitecture?
83
ASingle-CycleMicroarchitecture:Analysis
• Everyinstructiontakes1cycletoexecute• CPI(Cyclesperinstruction)isstrictly1
• Howlongeachinstructiontakesisdeterminedbyhowlongtheslowestinstructiontakestoexecute
• Eventhoughmanyinstructionsdonotneedthatlongtoexecute
• Clockcycletimeofthemicroarchitectureisdeterminedbyhowlongittakestocompletetheslowestinstruction
• Criticalpathofthedesignisdeterminedbytheprocessingtimeoftheslowestinstruction
84
2/14/17
22
WhatistheSlowestInstructiontoProcess?n Let’sgobacktothebasics
n Allsixphasesoftheinstructionprocessingcycletakeasinglemachineclockcycle tocomplete
• Fetch• Decode• EvaluateAddress• FetchOperands• Execute• StoreResult
• Doeachoftheabovephasestakethesametime(latency)forallinstructions?
1. Instruction fetch (IF)2. Instruction decode and
register operand fetch (ID/RF)3. Execute/Evaluate memory address (EX/AG)4. Memory operand fetch (MEM)5. Store/writeback result (WB)
85
Single-CycleDatapath Analysis• Assume
• memoryunits(readorwrite):200ps• ALUandadders:100ps• registerfile(readorwrite):50ps• othercombinationallogic:0ps
steps IF ID EX MEM WBDelay
resources mem RF ALU mem RF
Reg-Reg Op 200 50 100 50 400ir mov 200 50 100 50 400LW 200 50 100 200 50 600SW 200 50 100 200 550Call 200 50 100 200 50 600Jump 200 200 86
Ld Datapath
ifMEM[PC]==mrmovq Disp (rB), rAEA=Disp +R[rB]R[rA]¬MEM[EA]PC¬ PC+10
Combinationalstateupdatelogic
IF ID EX MEM WB
Registerfile
ValA
rB
DestE
valBALU
PC
InstructionMem
InstrAddr Instruction
DataMem
Address ReadData
WriteData
rA
ValE
ADD
RegWrite ALU
OP
MUX
MUXSelect
MUX
rB
rA
MUX
D
FromALU
FromMem10
PC
200ps250ps
350ps
550ps
600ps
100ps
87
SingleCycleuArch:Complexity• Contrived
• Allinstructionsrunasslowastheslowestinstruction
• Inefficient• Allinstructionsrunasslowastheslowestinstruction• Mustprovideworst-casecombinationalresourcesinparallelasrequiredbyanyinstruction
• Needtoreplicatearesourceifitisneededmorethanoncebyaninstructionduringdifferentpartsoftheinstructionprocessingcycle
• NotnecessarilythesimplestwaytoimplementanISA• Single-cycleimplementationofREPMOVS(x86)orINDEX(VAX)?
• Noteasytooptimize/improveperformance• Optimizingthecommoncasedoesnotwork(e.g.commoninstructions)• Needtooptimizetheworstcaseallthetime
88
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23
(Micro)architectureDesignPrinciples• Criticalpathdesign
• Findanddecreasethemaximumcombinationallogicdelay• Breakapathintomultiplecyclesifittakestoolong
• Breadandbutter(commoncase)design• Spendtimeandresourcesonwhereitmattersmost
• i.e.,improvewhatthemachineisreallydesignedtodo• Commoncasevs.uncommoncase
• Balanceddesign• Balance instruction/dataflowthroughhardwarecomponents• Designtoeliminatebottlenecks:balancethehardwareforthework
89
Single-CycleDesignvs.DesignPrinciples
nCriticalpathdesign
nBreadandbutter(commoncase)design
nBalanceddesign
Howdoesasingle-cyclemicroarchitecturefareinlightoftheseprinciples?
90
SamiraKhanUniversityofVirginia
Feb14,2017
IntrotoMicroarchitecture:Single-Cycle
CS3330
StageComputation:Cond.Move
• ReadregisterrA andpassthroughALU• Cancelmovebysettingdestinationregisterto0xF
• Ifconditioncodes&moveconditionindicatenomove
cmovXX rA,rBicode:ifun¬M1[PC]rA:rB¬M1[PC+1]
valP¬ PC+2
Fetch
ReadinstructionbyteReadregisterbyte
ComputenextPCvalA¬ R[rA]valB¬ 0
DecodeReadoperandA
valE¬ valB +valAIf!Cond(CC,ifun)rB¬ 0xF
ExecutePassvalA throughALU(Disableregisterupdate)
MemoryR[rB]¬ valEWrite
backWritebackresult
PC¬ valPPCupdate UpdatePC
92
ifMEM[PC]==cmov rA,rBif(cond)R[rB]ß R[rA]If(!cond)R[rB]ß 0xF
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24
ifMEM[PC]==cmov rA,rBif(cond)R[rB]ß R[rA]If(!cond)R[rB]ß 0xF
Combinationalstateupdatelogic
IF ID EX MEM WB
Registerfile
ValA
rB
DestE
valBALU
PC
InstructionMem
InstrAddr Instruction
DataMem
Address
ReadData
WriteData
rA
ValE
ADD
RegWrite ALU
OP
MUX
MUXSelect
MUX
rB
rA
MUX
DFromALU
FromMem
MUX
0
PC
MemWrite
2 MUX
109
MUX
D
MUX
rB
rsp
rsp
8
MUX
FromPC+x
MUX
93