5/7/2004tomi mansikkala user guide for svt/xtrp tx firmware v1.0 xtrp out control fpga tomi: -...

5/7/2004 Tomi Mansikkala

User guide for SVT/XTRP TX firmware v1.0

XTRP outControl FPGA

Tomi:- Introduction

- Control bit descriptions

- Test Pattern format & rules

- Missing features (to be done)

Frans:- Test setup

- VME user software available to configure the Tx

- Test results

Appendix:- VME address map

- Firmware details

5/7/2004 Tomi Mansikkala 2

- Sends data from RAM after receiving L1A and buffer number from P2 backplane

- 4K word internal RAM where user can load test patterns thru VME (if SRAM is used, 128K words can be loaded)

- RAM is divided to four buffers, each buffer is 1024 words deep

SVT/XTRP Tx firmware features

RAM

Test pattern

Output FIFO

L1A with buffer #

data

data

latency

Can send out different events for a given buffer

Can have delay before sending data- delay word: 12bits counts at CDFCLK (for XTRP)

Can have gaps between data words- gap word: 12bits counts at CDFCLK (for XTRP)

Can have empty events (not needed for SVT/XTRP)- transmitter doesn’t send out anything on certain L1As

Transmitting is disabled by default, needs to be enabled via VME


Block diagram

28bitRAM

Output FIFODataDelay

FF

SM1 SM2

DelayHandler

8bitL1AFIFO

8bit SM2L1AFIFO

Enabledata

data

emptybit

SM2L1A readrq

ready

readrq

FIFOempty

roboclock

roboclock

roboclock

CDFCLK

roboclock

data

trailerbit

databuffer#

ready

counterReset

CDFL1A + bufferCDFCLK

delaybit

outputbuffer select

enable delay

FIFOdatastrobe

L1AFIFO readrq

FIFOempty

FIFOEoE

Gapbit

compareA>=B

counter

gapReady

Start & reset

buffer0

buffer1

buffer2

buffer3

A

B

4096

1024

CDFCLK

CDFCLK

enableenable


Control bits in the user defined test pattern

- Test pattern RAM has 4096 28bit words and is divided to 4 buffers

23 data bits + 5 control bits

Control bits:

1st Delay (Delay before sending data out) 2nd Gap (Gap between data words) 3rd Empty event (Empty event) 4th End of event (EoE for TX) 5th Terminator (user friendly way to mark last event)

Control 5bits Data 23bits

Buffer 0

Buffer 1

Buffer 2

Buffer 3

.

.

1st event

2nd event

nth event

.

.

2nd event

nth event

1st event

4096 RAM


Delay before sending data out:- Set 1st control bit to high for delay control word

- First 12 data bits are used to define delay value

- Delay control word has to be in the beginning of each event, if no delay necessary then delay value is set to 0

- Firmware doesn't send delay words out

Gap between words:- Set 2nd control bit to high for gap words

- First 12 data bits are used to define gap delay value

- Firmware doesn't send gap words out

End of event:- Set 4th control bit to high on the last word of event

- Data bits are used for normal data word


Buffer 0

.

.

.

.

.

delay value

4096 RAM

data word

1

gap value1data word

.

.

gap value1data word

data word1

delay bit

gap bit

EoE bit

Delay and gap


Delay before sending data

CDFCLK

L1A

SVT_DS1,98us

Delay value <= 11(decimal): (Minimum L1A to data out delay)15 * CDFCLK15 * 132ns = 1.98us

Delay value > 11:(Delay value+4) * CDFCLKExample: Delay value is 20(20+4)*132ns = 31.68us


792nsdatastrobe

L1A

SVT_DS

CDFCLK

Gap between data words

Time of gap word delay:

6 * CDFCLK + gap value (gap value = CDFCLKs)

gap value = 0



Buffer 0

.

.

.

.

.

delay value

4096 RAM

data word

1

data word

1

data word1

Terminator: (a user friendly way to mark last event)

- Set 4th and 5th control bits to high for the last word

- After Terminator next event will be the 1st event in the buffer. Otherwise, continue to next event.

Empty event: - Set 3rd control bit to high on the events first word

- Data bits are not sent

- Firmware doesn't send any data out on this event

- not useful for SVT/XTRP

- a feature needed for Cluster

delay bit

EoE bitdata word

delay value

Terminator & empty event

1 data word1

Terminator bit

.

.

.

.

.

.

Buffer 1

data not used

Empty event bit

1

.

.

.

.

.


SVT_DS

L1A

CDFCLK

Empty event

no strobes = empty event



Buffer 0

Buffer 1

Buffer 2

Buffer 3

.

.

1st event

2nd event

14th event

.

.

2nd event

1st event

4096 RAMTest pattern format rules and example

Example

- Event size 72 words, total 14 events loaded

71 data words (includes EoE) 1 control word (delay)=> 1008 words / buffer

- Last word in the 14th event marked with terminator bit

14th event

14th event

14th event

1st event

1st event

.

.

.

.

0 : 080001F ;1 : 0000001 ;2 : 0000002 ;3 : 0000003 ;4 : 0000004 ;5 : 100000A ;6 : 0000005 ;7 : 0000006 ;8 : 0000007 ;9 : 100002B ;10 : 0000008 ;...70 : 0000070 ;71 : C400000 ;

One event:Test pattern format (user has to follow)

- Beginning of each event has to start from the same RAM location for all buffers

- First word in each event has to be either delay word or empty event word

- All buffers should have same number of valid events loaded. Last word on last event should be marked with terminator bit

- Need at least 2 data words first before gap word(s) can be used gap word

delay word

EoE + terminator word



Buffer 0

Buffer 1

Buffer 2

Buffer 3

.

.

1st event

2nd event

14th event

.

.

2nd event

1st event

4096 RAMTest pattern read back from RAM

14th event

14th event

14th event

1st event

1st event

.

.

.

.

Highest two read address bits of the RAM are controlled by L1A buffer number when Tx is enabled(to naturally divide the RAM into for four buffers)

- RAM read back should only be done when the Tx is disabled

- Outgoing events follow L1A buffer number order

Example

L1A order:L1A buffer 0 L1A buffer 1 L1A buffer 0 L1A buffer 2 …

Outgoing data order: 1st event from buffer 0 2nd event from buffer 1 3rd event from buffer 0 4th event from buffer 2 …

One other way is to stamp buffer bits on data word on the fly for a given L1A … and have events sent out in the same order as loaded. Can implement in next version if desired

.

.

4th event

1st

3rd

2nd

4th

3rd event


Missing features (to be done next)

- Current version is for XTRP, the clock is CDFCLK. For SVT data, different clock will be used

- Switch (via VME) to either pass thru real SVT/XTRP input or send fake data

- Actual Bunch Counter value stamped in the outgoing EOE word for each event (needed by SVT group)

5/7/2004 Frans Marjamaa 13

Test setup

SVT / XTRP TX XTRP RX

-Test setup in the lower crate in b0 test stand room

-TS calibration setup readout rate 4 kHz

-Myron mode

L1A L1A

Buffer# Buffer#

SlinkOutput DAQ

Input DAQ Output DAQ


Test software

-Separate (standalone) software for creating a test pattern files

-Text file can be modified later (change delay value, add gap words…) Current version of the software does not put any gap words in the pattern

-Test are run using run control

-Also standalone version for loading test pattern to TX RAM is available for others to use. It can be found in the online machines (~marjamaa/pulsar/utils/loadsvt/)

SVT / XTRP TX

VME BUS

CrateCPU

Text file


Test pattern example

Delay

EOE

Delay

EOE + Terminator


-Tested using variable event sizes (14 different events for every buffer)

-Long test, run ~80M events with 4kHz readout rate

-Different delay and gap values also tested and checked on logic analyzer

-All tests passed error free!

Test results


Appendix

- VME address map

- Delay handler block diagram

- RAM to FIFO SM

- TX FIFO out SM

- Tx enable/disable feature block diagram


TX XTRP Control FPGA

Address Action

32-bit Hex

YY000000 (R) Firmware version

YY000004 (W) Reset

YY000024 (R/W) Enable TX (bit 0: high=enabled, low=disabled)

YY600000 (W) RAM write

YY600004 (W) Reset RAM address counter

YY600008 (W) Advance RAM address counter

YY60000C (R) RAM read

YY100000 – YY10007C (R) IDPROM

YY = VME address bits 31..24. These bits are not used by firmware

Format:Firmware ID + Date + Version number 8-bits 20-bits 4-bits

Current version:Control SVT TX 05/06/04Hex: A6405060

Firmware version


SVT/XTRP: delayhandler component

FF

compare

counter FF

compare

counterFF

compare

counterFF

compare

counter

ready

readyB2 readyB3readyB0 readyB1

Demux

Delay in

Enable delay

Select input buffer

Delay inEnable delay B0

Delay in Enable delay B1 Delay inEnable delay B2

Delay inEnable delay B3

Reset when B0 & L1A

Reset when B1 & L1A

Reset when B2 & L1A

Reset when B3 & L1A

B0 = (((not bufferbit(0)) and (not bufferbit(1)) and ReadyB0) or B1 = (bufferbit(0) and (not bufferbit(1)) and ReadyB1) orB2 = ((not bufferbit(0)) and bufferbit(1) and ReadyB2) orB3 = (bufferbit(0) and bufferbit(1) and ReadyB3));

roboclockCDFCLK

CDFCLK

CDFCLK

Select output buffer

FF


WaitL1A

readBack2

readBack1

readBack0

searchBoE

writeEoE

checkData

waitDataChange3B

waitDataChange2B

waitDataChange1B

waitDataDelay2

waitDataDelay1

enableDelay

readFirst

WaitDataChange3

WaitDataChange2

WaitDataChange1

[L1AFIFOEmpty = ‘1’]

[L1AFIFOEmpty=‘0’] L1AFIFOrdreq = ‘1’

[else]

[DelayBit=‘1’] enableDelay = ‘1’ enableAddrCounter=‘1’

enableDelay = ‘0’

FIFOdatastrobe = ‘1’

[else]

[DelayBit=‘1’ or EmptyBit=‘1’ chgRAMaddrCountDir = ‘0’

enableAddr Counter=‘0’

[Trailer=‘0’ and Terminator=‘0’]

[emptyBit=‘1’] emptyEvent = ‘1’ enableAddrCounter=‘1’


clearAddrCounter=‘1’ FIFOdatastrobe=‘0’


SVT/XTRP: TXRAMtoFIFOInterface

clearAddrCounter=‘0’


[Trailer=‘1’ and Terminator=‘0’]

emptyEvent=‘0’

[else] enableAddrCounter=‘0’

chgRAMaddrCountDir=‘1’


CheckData

CheckGap Ready

Delay2Gap

[SM2L1AFIFOEmpty=‘0’] SML1AFIFOrdreq = ‘1’

SML1AFIFOrdreq = ‘0’

enableData = ‘0’

[FIFOEoE=‘1’] readFIFO = ‘0’ enableData = ‘1’

ResetGapCounter = ‘0’

[GapReady=‘1’ ] EnableGapCounter =‘0’

readFIFO = ‘0’

[FIFOEoE=‘0’ and EmptyEventIn=‘0’ and

GapBit=‘0’]

readFIFO = ‘0’ enableData = ‘1’

First <= false

[SM2L1AFIFOEmpty = ‘1’]

[FIFOEmpty=‘0’ and Ready=‘1’]

readFIFO = ‘1’

readFIFO = ‘0’

[GapReady=‘0’]

SVT/XTRP: TXSTM

[else]

waitL1A

strobeEoE

Delay for ready

Wait data and delay

Delay Data

[EmptyEventIn=‘1’] readFIFO = ‘0’

Delay1Gap

Null

[GapBit=‘1’ and First=False]

EnableGapCounter = ‘1’ ResetGapCounter = ‘1’

readFIFO = ‘0’ enableData=‘0’

Delay1stGap

[GapBit=‘1’ and First=True]

EnableGapCounter = ‘1’ ResetGapCounter = ‘1’

readFIFO = ‘0’ enableData = ‘1’

First <= false

ResetGapCounter = ‘0’ readFIFO=‘0’ enableData=‘0’

SVT DS

readFIFO = ‘1’ enableData=‘0’

delayEoE

enableData = ‘0’


RAM

10b RAM readaddresscounter

12b RAM readaddresscounter

VME bus

L1A

RAM READ address

12b MUXSM1 clr

ena

2bBuffer#

Select (enable tx)

ena clr

12b

L1A & enable tx

L1A

Dual port RAM

Tx enable also selects the control of the two highestbits of RAM read address. User has full control of allread address when Tx is in disabled mode

TX enable/disable feature

5/7/2004tomi mansikkala user guide for svt/xtrp tx firmware v1.0 xtrp out control fpga tomi: -...

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