4k and beyond 17 june 2014 syed athar hussain vesa vice ... · syed athar hussain vesa vice chair...
TRANSCRIPT
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4k and beyond
17 June 2014
Syed Athar Hussain
VESA Vice Chair
AMD Display Domain Fellow
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GLOBAL INDUSTRY ALLIANCE WITH MORE THAN 200 INDUSTRY-LEADING MEMBER
COMPANIES - VESA REPRESENTS THE DISPLAY ECO-SYSTEM
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RECENT VESA ACTIVITY
Display Stream Compression
• Today, DisplayPort already
supports 4kx2k@60 Hz,30bpp
• Getting ready for 8kx4k transition
DockPort
• Single cable that can carry
multiple independent A/V stream,
USB data & optionally power
• Simplified user setup, without
multi-cable hassle
Adaptive Sync
• Power efficient transport of
content
• Smooth, stutter free video and
gaming experience
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WHAT IS DISPLAYPORT ? AN OVERVIEW
• High-speed packet based interface
• Enables multiple independent stream on single cable and allows DisplayPort streams to be
tunneled over different transport layer (Thunderbolt, Wigig Display Extension)
• Flexible pixel packing; Stream rate is decoupled from link rate
• Spread-spectrum clocking and pseudo random coding for RFI mitigation
• With DP connector, one of following fixed rates can be selected (*Target rate for next DP version)
• Flexible lane configuration allows 1, 2, or 4 lanes to be enabled depending on A/V stream
requirements
• DockPort ; 2 lanes are used for A/V data and remaining 2 lanes to steer USB3 traffic
Main Link
Configuration
Raw Bit Rate (includes
coding overhead) - Gbps
Application Bandwidth
Throughput - Gbps
1 lane 1.62, 2.7, 5.4, 8.1* 1.296, 2.16, 4.32, 6.48*
2 lanes 3.24, 5.4, 10.8, 16.2* 2.592, 4.32, 8.64, 12.96*
4 lanes 6.48, 10.8, 21.6, 32.4* 5.184, 8.64, 17.28, 25.92*
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8KX4K CHALLENGE - JUST RAISING THE “LINK” BAR IS NOT ENOUGH!
Flexible pixel packing enables 8kx4k@60 pixel rate at 8bpp with DP1.2a link rates and 10 and 12bpp
with target link rate of next version of DP
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Bandwidth (Gbps; CVT Timing) DP1.2a DP next version
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TO OVERCOME THE HIGH DISPLAY BANDWIDTH CHALLENGE, A HOLISTIC END TO
END APPROACH IS REQUIRED
Source
Processing
Pipeline
Sink
Processing
Pipeline
Cable
• Reduce Frame Timing Transmission
Overhead
• Optimize pixel rate transmission
through the processing pipe line
• Overcome link rate constraints of
today’s passive cable
• Efficient transport of content over the
link
Content Display
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VESA COORDINATED VIDEO TIMING (CVT) SPECIFICATION REDUCES FRAME
TIMING OVERHEAD
• DisplayPort transport decouples the stream rate from link rate allowing for flexible frame timing customization based
on application requirement
• CVT specification can be used to define custom reduced blank timing allowing for reduced pixel rate and lower frame
transmission overhead
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2160p @6030bpp
2160p @6030bpp (CVT)
2160p @6030bpp (CEA)
Bandwidth vs Frame Timing
Bandwidth in Gbps
CEA
CVT
Active
Region
Blank
Region
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DIVIDE AND CONQUER WITH MULTIPLE PROCESSING PIPELINE TO OVERCOME
PIPELINE LIMITATION
Source
Processing
Pipeline
Sink
Processing
Pipeline
Source
Processing
Pipeline
Sink
Processing
Pipeline Cable
• A single stream processing pipeline capability can be challenging at
higher pixel rates.
• Higher resolutions can be addressed by processing sections of the
display in parallel, lowering the pixel rate for each section
• DisplayPort Multi-Stream Transport can subdivide the single display
into sections for more efficient handling by the display processing
pipeline
• This display configuration is known as a “Tiled Display Configuration”
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Resolution Per Pipe Pixel Rate
(Mpix/s)
3840x2160@60 533.250
3840x2160@60
(2x1 Tile of 1920x2160@60)
2x277.250
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SO HOW DOES TILED DISPLAY CONFIGURATION WORK?
Sink
Processing
Pipeline
Sink
Processing
Pipeline Cable
• Sink EDID exposes tile topology
configuration and source automatically
construct the appropriate streams and
maps it to appropriate tile for plug &
play end user experience.
• Enables a single cable experience with
the benefit of using multiple processing
pipeline operating at an optimized pixel
rate.
• Can be extended to more tiles for even
higher resolution
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Source
Processing
Pipeline
Source
Processing
Pipeline
Display
Left
Tile
Display
Right
Tile
Content
Left
Tile
Content
Right
Tile
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LINK IS NOT KEEPING UP WITH HIGHER DISPLAY BANDWIDTH DEMANDS
Source
Processing
Pipeline
Sink
Processing
Pipeline
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• To maximize current link capability, a standard compression solution is required
• Last year, 4kx2k@60 solution used 2 streams over DP MST in a Tiled Display Configuration
• This year’s 4kx2k@60 products are launched with single stream transport.
• Processing capability is evolving over time, but links are not keeping up
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VESA DISPLAY STREAM COMPRESSION (DSC) SPECIFICATION ENABLES HIGHER
RESOLUTION ON BANDWIDTH CONSTRAINED LINK
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• Visually lossless compression algorithm that guarantees a constant compressed data rate target to meet the
link requirement
• Low buffering overhead with a single line of storage
• Enables both higher resolution or link power savings at existing resolution
• Part of embedded DisplayPort and external DisplayPort standard
Source
Processing
Pipeline
Sink
Processing
Pipeline
Decompression
Block
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Compression
Block
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Bandwidth (Gbps, CVT Timing) DP1.2a DP Next Version
8K X 4K @60HZ CHALLENGE REVISITED WITH DSC
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Cable
VESA DSC SUPPORTED FOR BOTH SINGLE AND MULTI-STREAM TRANSPORT
Source
Processing
Pipeline
Source
Processing
Pipeline
Source
Processing
Pipeline
Source
Processing
Pipeline
Sink
Processing
Pipeline
Sink
Processing
Pipeline
Sink
Processing
Pipeline
Sink
Processing
Pipeline
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• Tiled Display configuration will allows multiple processing pipe to
divide the pixel rate as opposed to having a singe processing
pipeline run over 2Gpix/s for 8kx4k@60
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CONTENT UPDATE RATE DEPENDS ON THE USAGE SCENARIO
• Interactive desktop updates at nominal rate
• Gaming content update rate changes every frame depending on the
frame rendering complexity
• Web browsing, static desktop update are much slower
• Video update rate is fixed and depends on the video content
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TRADITIONALLY CONTENT IS TRANSPORTED AT FIXED DISPLAY RATE
Cable Source
Processing
Pipeline
Sink
Processing
Pipeline
Content Independent Fixed Frame Rate
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VESA ADAPTIVE SYNC TECHNOLOGY ENABLES SOURCE TO UPDATE DISPLAY AT
CONTENT UPDATE RATE
Cable
24 Hz Video 24 Hz Video
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Content Adaptive Frame Rate
24 Hz Video
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SUMMARY: DISPLAYPORT OFFERS FLEXIBLE ARCHITECTURE AND KEY
TECHNOLOGIES TO ENABLE HIGH RESOLUTION DISPLAYS BEYOND 4K
Optimized frame timing definition
Tiled Display support with Multi-Stream transport
Display Stream Compression Technology for link
constrained scenario
Adaptive Sync Technology for efficient transport of content
over the link