F.N.E.

S.C. JUN

Dept. of Mechanical Engineering

C h a p t e r

1

F.N.E.

S.C. JUN

Dept. of Mechanical Engineering

• The problem of shrinking the size of devices fabricated through optical

lithography can be readily understood.

• One can broadly define lithography as the process of

1 Lithography

F.N.E.

S.C. JUN

Dept. of Mechanical Engineering

• Using electromagnetic energy to transfer a pattern from a mask to a resist layer

deposited on the surface of a substrate.

• 1. A photosensitive emulsion called a photoresist is applied to the wafer

• 2. Optical energy (light† ) is directed at a photomask containing opaque and

transparent regions that correspond to the desired pattern.

• (a) For a negative photoresist, the resist material is initially soluble(for a

particular solvent that will be used in development), and through a chemical

reaction when exposed to light, becomes insoluble.

• (b) In a positive photoresist, the resist material is initially insoluble, and

through a chemical reaction when exposed to light, becomes soluble.

Figure 1. Depiction of steps 1-3 of the

lithography process.

F.N.E.

S.C. JUN

Dept. of Mechanical Engineering

• May then be performed to transfer the pattern from the resist to the wafer.

• (a) Etching may be used to remove substrate material.

• The photoresist serves to resist the etching and protect sections of the wafer

that it covers.

• After etching the resist is removed, leaving the desired structure.

• (b) Material may be deposited, for example, me0tallization, onto the wafer.

• Then the photoresist can be removed( the material deposited on the

photoresist is also thereby removed, which is known as lift-off)

• Leaving the deposited material in areas that were not covered by the resist.

• (c) Doping can occur.

• A beam of dopant ions can be accelerated towards the wafer.

• Thus creates regions of doping in areas not covered by the resist.

• This is known as ion implantation.

Figure 2 Depiction of light diffraction

through an aperture in an opaque screen.

F.N.E.

S.C. JUN

Dept. of Mechanical Engineering

• The resolution R of an optical lithography process describes the ability of an

imaging system to resolve two closely spaced objects.

• And is not actually the smallest feature size of a printed object.

• The general problem of achieving good resolution can be appreciated by

considered the pattern of light.

• Forms in passing through the transparent regions of the photomask.

• By a process known as diffraction,

• Basically the ability of light to “bend” around corners, as light passes through an

aperture on the mask, it tends to smear out

• There is an interplay between the aperture size 2ω, wavelength λ, and position z.

• Although, in general, at a fixed position z the smaller the aperture compared to

wavelength.

• The resolution of an optical lithography process.

• k1 is a constant, λ is the wavelength of the source, and N A is called the

numerical aperture.

R = k1 NA

λ

F.N.E.

S.C. JUN

Dept. of Mechanical Engineering

• In contrast to the “top-down” approach, this nano scale building is called the

“bottom-up” approach, and represent a much more radical technology shift,

which is currently being explored in research laboratories.

• The development of nanoscopic devices includes the possibility of ultrasmall,

low power electronic products, such as communication and computing devices

and embedded sensors.

• Furthermore, as electronics shrink, the possibility of further incorporating

electronics with biological systems rapidly expands.‡

• Therefore, there are many factors driving the miniaturization of electronic

devices.

1.2 THE “BOTTOM-UP” APPROACH

1.3 WHY NANOELECTRONICS?

F.N.E.

S.C. JUN

Dept. of Mechanical Engineering

• Thus, the question “Why nanoelectronics?” seems to have an obvious answer.

• In addition to the benefits of smaller transistors, there are significant problems in

shrinking conventional devices to the nanoscale. For example,

•

• 1. Device fabrication: it may be difficult to extend optical lithography into the

realm of low tens of nanometers

• Other fabrication methods (such as the bottom-up approach) for high-

throughput, commercial-laver production are not

• 2. Device operation: As device dimensions are reduced, voltage levels also need to

be reduced accordingly.

• This lowers the threshold voltage of MOSFET devices, and makes it difficult

to completely turn the device off, wasting power.

• Tunneling and ballistic transport are two prominent quantum effects that will

be discussed.

F.N.E.

S.C. JUN

Dept. of Mechanical Engineering

• 3. Heat dissipation: As device density increase, the dissipation of heat

becomes a major problem

• Reducing circuit reliability and leading to shorter device lifetimes, or to

device failure.

• If the rate of increasing device density were to continue, microprocessors

would soon be producing more heat per square centimeter than the

surface of the sun!§

• § Current ICs have power densities in the order of 100 W/cm2, up from

10 W/cm2 a decade ago.

• The power density of a typical hot plate is 10 W/cm2 , whereas the

surface of the sun has 7000 W/cm2 .