390129 introduction to logic gates

8/8/2019 390129 Introduction to Logic Gates

1/38

Introduction to Logic Gates

Logic Gates

The Inverter

The AND Gate

The OR Gate The NAND Gate

The NOR Gate

The XOR Gate

The XNOR Gate

Drawing Logic Circuit

Analysing Logic Circuit


2/38

Introduction to Logic Gates Universal Gates: NAND and NOR

NAND Gate

NOR Gate

Implementation using NAND Gates

Implementation using NOR Gates

Implementation of SOP Expressions

Implementation of POS Expressions

Positive and Negative Logic

Integrated Circuit Logic Families


3/38

Logic Gates

Gate Symbols

EXCLUSIVE OR

a

ba.b

a

ba+b

a a'

a

b(a+b)'

a

b(a.b)'

a

ba b

a

ba.b&

a

ba+bu1

AND

a a'1

a

b(a.b)'&

a

b(a+b)'u1

a

ba b=1

OR

NOT

NAND

NOR

Symbol set 1 Symbol set 2

(ANSI/IEEE Standard 91-1984)


4/38

Logic Gates: The Inverter

The InverterA A'

0 1

1 0

A A' A A'

Application of the inverter: complement.

1

0

0

1

0

1

0

1

1

0

0

1

1

0

1

0

Binary number

1s Complement


5/38

Logic Gates: The AND Gate

TheAND Gate

A B A . B

0 0 0

0 1 0

1 0 0

1 1 1

A

BA.B

&A

BA.B


6/38

Logic Gates: The AND Gate

Application of the AND Gate

1 sec

A

1 sec

Enable

A

EnableCounter

Reset to zero

betweenEnable pulses

Register,

decode

andfrequency

display


7/38

Logic Gates: The OR Gate

The OR Gate

u1A

BA+B

A

BA+B

A B A+B

0 0 0

0 1 1

1 0 1

1 1 1


8/38

Logic Gates: The NAND Gate

The NAND Gate

&A

B(A.B)'

A

B(A.B)'

A

B(A.B)'|

NAND Negative-OR

|

A B (A.B)'

0 0 1

0

1 11 0 1

1 1 0


9/38

Logic Gates: The NOR Gate

The NOR Gate

NOR Negative-AND

|

u1A

B(A+B)'|

A

B(A+B)'

A

B(A+B)'

A B (A+B)'

0 0 1

0 1 0

1 0 0

1 1 0


10/38

Logic Gates: The XOR Gate

The XOR Gate

=1A

BA B

A

BA B

A B AB

0 0 0

0 1 1

1 0 1

1 1 0


11/38

Logic Gates: The XNOR Gate

The XNOR Gate

A

B(A B)'

=1A

B(A B)'

A B (AB)'

0 0 1

0 1 0

1 0 0

1 1 1


12/38


When a Boolean expression is provided, we caneasily draw the logic circuit.

Examples:

(i) F1 = xyz' (note the use of a 3-input AND gate)

x

y

z

F1

z'


13/38


(ii) F2 = x + y'z (can assume that variables and theircomplements are available)

(iii) F3 = xy'+x'z

x

y'z

F2

y'z

x'

z

F3

x'z

xy'x

y'


14/38

Problem

Q1. Draw a logic circuit for BD + BE + DF

Q2. Draw a logic circuit forABC + BCD + BCD + ABD


15/38

Analysing Logic Circuit

When a logic circuit is provided, we can analyse thecircuit to obtain the logic expression.

Example: What is the Boolean expression of F4?

A'B'

A'B'+C (A'B'+C)'

A'

B'

CF4

F4 = (A'B'+C)' = (A+B).C'


16/38

Problem

What is Boolean expression of F5?

z

F5

x

y


17/38

Universal Gates: NAND andNOR

AND/OR/NOT gates are sufficient for building anyBoolean functions.

However, other gates are also used because:

(i) usefulness(ii) economical on transistors

(iii) self-sufficient

NAND/NOR: economical, self-sufficientXOR: useful (e.g. parity bit generation)


18/38

NAND Gate

NAND gate is self-sufficient(can build any logiccircuit with it).

Can be used to implement AND/OR/NOT.

Implementing an inverter using NAND gate:

(x.x)' = x' (T1: idempotency)

x x'


19/38

NAND Gate

((xy)'(xy)')' = ((xy)')' idempotency

= (xy) involution

((xx)'(yy)')' = (x'y')' idempotency

= x''+y'' DeMorgan= x+y involution

Implementing AND using NAND gates:

Implementing OR using NAND gates:

xx.y

y

(x.y)'

x

x+y

y

x'

y'


20/38

NOR Gate

NOR gate is also self-sufficient.

Can be used to implement AND/OR/NOT.

Implementing an inverter using NOR gate:

(x+x)' = x' (T1: idempotency)

x x'


21/38

NOR Gate

((x+x)'+(y+y)')'=(x'+y')' idempotency= x''.y'' DeMorgan

= x.y involution

((x+y)'+(x+y)')' = ((x+y)')' idempotency

= (x+y) involution

Implementing AND using NOR gates:

Implementing OR using NOR gates:

x x+yy

(x+

y)'

x

x.y

y

x'

y'


22/38

Implementation using NANDgates

Possible to implement any Boolean expression usingNAND gates.

Procedure:

(i) Obtain sum-of-products Boolean expression:e.g. F3 = xy'+x'z

(ii) Use DeMorgan theorem to obtain expressionusing 2-level NAND gates

e.g. F3 = xy'+x'z= (xy'+x'z)' ' involution

= ((xy')' . (x'z)')' DeMorgan


23/38

Implementation using NANDgates

F3 = ((xy')'.(x'z)') ' = xy'+x'z

x'

z

F3

(x'z)'

(xy')'x

y'


24/38

Implementation using NORgates

Possible to implement boolean expression using NORgates.

Procedure:

(i) Obtain product-of-sums Boolean expression:e.g. F6 = (x+y').(x'+z)

(ii) Use DeMorgan theorem to obtain expressionusing 2-level NOR gates.

e.g. F6 = (x+y').(x'+z)= ((x+y').(x'+z))' ' involution

= ((x+y')'+(x'+z)')' DeMorgan


25/38

Implementation using NORgates

F6 = ((x+y')'+(x'+z)')' = (x+y').(x'+z)

x'

z

F6

(x'+z)'

(x+y')'x

y'


26/38

Implementation of SOPExpressions

Sum-of-Products expressions can be implementedusing:

2-level AND-OR logic circuits

2-level NAND logic circuits

AND-OR logic circuit

F = AB+ CD+ E

F

A

B

D

C

E


27/38

Implementation of SOPExpressions

NAND-NAND circuit (bycircuit transformation)

a) add double bubbles

b) change OR-with-inverted-inputs to NAND& bubbles at inputs totheir complements

F

A

B

D

C

E

A

B

D

C

E'

F


28/38

Implementation of POSExpressions

Product-of-Sums expressions can be implementedusing:

2-level OR-AND logic circuits

2-level NOR logic circuits

OR-AND logic circuit

G = (A+B).(C+D).E

G

A

B

D

C

E


29/38

Implementation of POSExpressions

NOR-NOR circuit (bycircuit transformation):

a) add double bubbles

b) changed AND-with-inverted-inputs to NOR& bubbles at inputs totheir complements

G

A

B

D

C

E

A

B

D

C

E'

G


30/38

Solve it yourself (Exercise4.3)

Q1. Draw a logic circuit for BD + BE + DF using onlyNAND gates. Use both DeMorgan method and SOPmethod.

Q2. Transform the following AND-OR Circuit to NANDcircuit.

Q3. Using only NOR gates, draw a logic circuit using POSmethod for (A+B+C)(B+C+D)

z

F

x

y


31/38

Positive & Negative Logic

In logic gates, usually:

H (high voltage, 5V) = 1

L (low voltage, 0V) = 0

This convention positive logic.

However, the reverse convention, negative logicpossible:

H (high voltage) = 0

L (low voltage) = 1

Depending on convention, same gate may denotedifferent Boolean function.


32/38


A signal that is set to logic 1 is said to be asserted, oractive,

ortrue.

A signal that is set to logic 0 is said to be deasserted, or

negated, orfalse.

Active-high signal names are usually written in

uncomplemented form.

Active-low signal names are usually written in complemented

form.


33/38


Positive logic:

Negative logic:

Enable

Active High:

0: Disabled

1: Enabled

Enable

Active Low:

0: Enabled

1: Disabled


34/38

Integrated Circuit LogicFamilies

Some digital integrated circuit families: TTL, CMOS, ECL.

TTL: Transistor-TransistorLogic.

Uses bipolar junction transistors

Consists of a series of logic circuits: standard TTL, low-power TTL,

Schottky TTL, low-power Schottky TTL, advanced Schottky TTL,

etc.


35/38


36/38


CMOS: ComplementaryMetal-Oxide Semiconductor.

Uses field-effect transistors

ECL: EmitterCoupled Logic.

Uses bipolar circuit technology.

Has fastest switching speed but high power consumption.


37/38


Performance characteristics

Propagation delay time.

Power dissipation.

Fan-out: Fan-out of a gate is the maximum number of inputs that thegate can drive.

Speed-power product (SPP): product of the propagation delay time

and the power dissipation.


38/38

Summary

Logic Gates

AND,

OR,NOT

NAND

NOR

Drawing Logic

Circuit

Analyzing

Logic Circuit

Given a Boolean

expression, draw thecircuit.

Given a circuit, find

the function.

Implementation of a

Boolean expressionusing these

Universal gates.

Implementation

of SOP and POS

Expressions

Positive and

Negative Logic

Concept of Minterm

and Maxterm

390129 introduction to logic gates

Documents