introduction to computing systems from bits & gates to c & beyond chapter 3 digital logic...
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Introduction to Computing Systemsfrom bits & gates to C & beyond
Chapter 3Chapter 3
Digital Logic Structures
Transistors Logic gates & Boolean logic
Combinational logic Storage Elements
Memory
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TransistorsTransistors
An electronic switchlike light switch or faucetswitches between insulator and conductor switch is closed (conducts) between A & B depending on the voltage on G (gate)
Open switch: no current flows
Closed switch: current flows
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A
B
G
A
B
GN
Closed if gate is “on”Open if gate is “off”
P
Open if gate is “on”Closed if gate is “off”
A
B
G
CMOS TransistorsCMOS Transistors
CMOS= Complementary Metal-Oxide SemiconductorStandard type for digital applicationsTwo types: N (negative) and P (positive)N and P transistors operate in inverse modes
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2.9 v
0 v
OutIn
In Out0 11 0
Inverter GateInverter Gate
When the input is on (In = high voltage), the P-type transistor is open and the N-type is closed, so the output is off (Out = low voltage).
Vice-versa: when the Input is off (In = low voltage), the output is connected to the high voltage.
P
N
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NOR GateNOR Gate
A B C0 0 10 1 01 0 01 1 0
C
A
B
2.9 v
0 v0 v
P
N
P
N
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NOR Gate - OperationNOR Gate - Operation2.9 v
0 v0 v
P
N
P
0 v
0 v2.9 v
2.9 v
0 v0 v
N
P
N
2.9 v
2.9 v
0 v
N
0 v0 v
P
N
P
N
2.9 v
2.9 v
0 v
0 v
P
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OR GateOR Gate
D
A
B C
A B C D0 0 1 00 1 0 11 0 0 11 1 0 1
= a NOR gate followed by an inverter
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NAND & AND GatesNAND & AND Gates
A B C D0 0 1 00 1 1 01 0 1 01 1 0 1
A
B
C D
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Logic Gates & SymbolsLogic Gates & Symbols
Note: gates can have more than two inputs.
Inverter (=NOT)inverts 0 to 1 and 1 to 0
AND gatec is 1 only if both a and b are 1
a
bc
OR gatec is 1 if either a or b is 1
a
bc
NAND gatec is 0 only if both a and b are 1
a
bc
NOR gatec is 0 if either a or b are 1
a
bc
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De Morgan’s LawDe Morgan’s Law A and B = not((not A) or (not B))
A or B = not((not A) and (not B))
Completeness AND, OR and NOT are sufficient to represent any truth table. Actually: AND & NOT, or OR & NOT are separately sufficient. So: all we need are NOR or NAND gates.
Bor AB andA =
B and ABor A =
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Representation of Logic FunctionsRepresentation of Logic FunctionsA logic function can be represented as
a truth tablea logic expressiona logic circuit
Example
.ca a.d a.b.c .c a d) a.(b.c f
a b c d f0 0 0 0 00 0 0 1 00 0 1 0 10 0 1 1 10 1 0 0 00 1 0 1 00 1 1 0 10 1 1 1 11 0 0 0 01 0 0 1 11 0 1 0 01 0 1 1 11 1 0 0 01 1 0 1 1
1 1 1 0 11 1 1 1 1
ba
c
d f
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Types of Logic StructuresTypes of Logic StructuresTwo types of logic structures (devices)
Storage structures: permit the storage of information (1 bit). Decision structures: can make a decision but do not remember what it
was: gates belong to this category.
Combinational logic a logic structure is combinational if it is constructed from decision
elements only: gates or other combinational logic structures. the output of a combinational logic structure depends strictly on its
current input.
Three examples Decoder Multiplexer (MUX) Full adder
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DecoderDecoder
An n input decoder has 2n
outputs.
Outputi is 1 iff the binary
value of the n-bit input is i.
At any time, exactly one output is 1, all others are 0.
1, iff A,B is 00AB
1, iff A,B is 01
1, iff A,B is 10
1, iff A,B is 11
i = 0
i = 1
i = 2
i = 3
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Multiplexer (MUX)Multiplexer (MUX) In general, a MUX has
2n data inputs n select (or control) lines and 1 output.
It behaves like a channel selector.
A 4-to-1 MUX: Out takes the value of A,B, C or Ddepending on the value of S (00, 01, 10, 11)
S[1:0]
A B C D
Out
.S D.S S. C.S .S SB. S. SA. Out 10101010
A B C D
Out
S0
S1
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AdderAdderHalf Adder
2 inputs2 outputs: sum and carry
Full Adderperforms the addition in column i3 inputs: ai, bi and ci
2 outputs: si and ci+1
ci is the carry in from bit position i-1
ci+1 is the carry out to bit position i+1
A B C S0 0 0 00 1 0 11 0 0 11 1 1 0
Half-adder truth table
012n1n
012n1n
012n1n
12n1n
s s ... s s
b b ... b b
a a ... a a
0 c ... c c
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Gate Level Full AdderGate Level Full Adder
Ai Bi Ci Ci+1 Si
0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1
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Full Adder - ExpressionsFull Adder - Expressions
).(.1 iiiiii
iiii
bacbac
cbas
where
operation OR theis
operation AND theis .
OR exclusive is
- verify that this corresponds to the gate-level implementation.
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A 4-bit Ripple-Carry AdderA 4-bit Ripple-Carry Adder
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Carry Lookahead AdditionCarry Lookahead AdditionWe can pre-compute the carry
The carry in bit 4 (C4) is 1 if any two of A3, B3 or C3 are 1.
P3 is called the propagate bit, and G3 the generate bit
So every carry bit can be pre-computed using all the previous inputs.
Pre-computation can be done in 2 gate delays.
333
33333
3333334
CPG
)B(AC.BA
BCACBAC
01231123123233
1112233222333334
CPPPGPPPGPPGPG
))CP(GP(GPG)CP(GPGCPGC
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Storage Elements: R-S LatchStorage Elements: R-S LatchThe R-S Latch
•The output (a) of the R-S latch can be set to 1 by momentarily setting S to 0 while keeping R at 1.•If S is set to 1 the output stays at 0.
1
0
•Conversely, the output can be set to 0 by keeping S at 1 and momentarily setting R to 0.•When R is set back to 1, the output stays at 0.
1
00
1 0
1
The flip-flop (R-S latch) is a bi-stable element
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Storage Elements: Gated D LatchStorage Elements: Gated D LatchThe R-S Latch
•The gated D larch is an extension of the R-S latch•Two inputs: data (D) and write enable (WE)•When the WE (write enable) is set to 1, the output of the latch is set to the value of D.•The output is held until WE is “asserted” (set to 1) again.
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RegistersRegisters
A 4-bit register made of four D latches
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Memory - 1Memory - 1
Address Space
n bits allow the addressing of 2n memory locations. Example: 24 bits can address 224 = 16,777,216 locations
(i.e. 16M locations).
If each location holds 1 byte then the memory is 16MB.
If each location holds one word (32 bits = 4 bytes) then it is 64 MB.
A large number of addressable fixed size locations
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Memory - 2Memory - 2Addressability
Computers are either byte or word addressable - i.e. each memory location
holds either 8 bits (1 byte), or a full standard word for that computer
(typically 32 bits, though now many machines use 64 bit words).
Normally, a whole word is written and read at a time:
If the computer is word addressable, this is simply a single address location.
If the computer is byte addressable, and uses a multi-byte word, then the word
address is conventionally either that of its most significant byte (big endian
machines) or of its least significant byte (little endian machines).
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Building a MemoryBuilding a Memory
Each bit is a gated D-latch
Each locationconsists of w bits (here w = 1)w = 8 if the memory is byte
addressable
Addressingn locations means log2n
address bits (here 2 bits => 4 locations)
decoder circuit translates address into 1 of n addresses
WE
A[1:0] D
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Memory ExampleMemory Example
A 22 by 3 bits memory:•two address lines: A[1:0]•three data lines: D[2:0]•one control line: WE
One gated D-latch
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Using Memory Building BlocksUsing Memory Building BlocksBuilding an 8K byte memory using chips that are 2K by 4 bits.
CS = chip select:
when set, it enables the addressing, reading and writing of that chip.
This is an 8KBbyte addressable
memory
decoder
CS CS
CS CS
CS CS
CS CS
A10-A0
A12-A11
2K x 4 bits 2K x 4 bits
2K x 4 bits2K x 4 bits
2K x 4 bits 2K x 4 bits
2K x 4 bits2K x 4 bits
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Memory One Word WideMemory One Word Wide
Use the previous memory block of 8K x 1 byte to build a memory that is 64K words, with each location one word of 32 bits.
what are the address lines if the memory is word addressed? or byte addressed?
A? - A?
decoder
A? - A?
8K x 1B
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Finite-State MachinesFinite-State Machines
Output is a function of the input and the state The function is computed by the combinatorial logic circuit The state is stored in the storage element The state is also a function of itself and the input
Combinational Logic Circuit
StorageElement
outputinput
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FSM ExampleFSM Example
Three groups of lights to be lit in a sequence: group 1 on, groups 1 & 2 on, all groups on, all off.
The lights are on only if the main switch is on.
Four states: so we need two bits to identify each state.
DETOUR
Combinational Logic Circuit
Two bit Storage
switch
clock
22
out1out2out3
all on grp 1,2 on
all off grp 1 on
1
1
0
0
0
1
0,1
01
10
11
00
S d[1:0]
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FSM ExampleFSM ExampleWhen is group 1 on?
in states 01, 10 and 11 - but only when the switch is on!
When do we switch to the next state? at every clock cycle the two bits are updated d[1:0] is the state at the next clock cycle; it is a function of the
input (switch) and the current state. can you come up with a logic expression for d0 and d1?
).switch.S(Sout3
).switch.SS S(Sout2
).switch.SS SS.SS(out1
10
1010.
1010.10
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The LC-2 The LC-2 as a as a
Finite Finite State State
MachineMachine
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Data Path of Data Path of the LC-2the LC-2