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Energy-Efficient Domino VLSI Circuits and their

Performance with PVT Variations in DSM

TechnologySalendra.Govindarajulu1, Dr.T.Jayachandra Prasad2, Chimakurthy.Sreelakshmi3, C.H.Balaji4,

1Associate Professor, ECE, RGMCET, Nandyal, JNTU, A.P.State, India, Email: [email protected]

2Principal, RGMCET, Nandyal, JNTU, A.P.State, India, Email: [email protected]

3PG Student, ECE, RGMCET, Nandyal, JNTU, A.P.State, India, Email: [email protected] 4UG Student, KLU, Vijayawada.

Abstract— Compared to static CMOS logic, dynamic logic offers

good performance. Wide fan-in dynamic logic such as domino is

often used in performance critical paths, to achieve high speeds

where static CMOS fails to meet performance objectives.

However, domino gates typically consume higher dynamic

switching and leakage power and display weaker noise immunity

as compared to static CMOS gates. Keeping in view of the above

stated problems in previous existing designs, novel energy-efficient domino circuit techniques are proposed. The proposed

circuit techniques reduced the dynamic switching power

consumption; short-circuit current overhead, idle mode leakage

power consumption and enhanced evaluation speed and noise

immunity in domino logic circuits. Also regarding performance,

these techniques minimize the power-delay product (PDP) as

compared to the standard full-swing circuits in deep sub micron

CMOS technology.

Also the effect of the Process, Voltage and Temperature

(PVT) variations on the performance of the CMOS Domino

circuits with various techniques are analyzed.

Key words: Dynamic, Domino, Noise Margin, Deep submicron

technology (DSM), High speed, Power consumption, Power delayproduct (PDP), PVT variations, Reduced dynamic swing.

I. I NTRODUCTION

Dynamic domino logic circuits are widely used in moderndigital VLSI circuits. These dynamic circuits are oftenfavoured in high performance designs because of the speedadvantage offered over static CMOS logic circuits. The main

drawbacks of dynamic logic are a lack of design automation,a decreased tolerance to noise and increased power dissipation. However, domino gates typically consume higher

dynamic switching and leakage power and display weaker noise immunity as compared to static CMOS logic circuits. In

this paper novel energy-efficient domino circuit techniquesare proposed.

This paper is organized as follows. In section II, Dual-raildomino circuit with self-timed precharge scheme is proposed.The Reduced dynamic swing domino logic is presented in

section III. Section IV describes performance evaluationresults of energy-efficient dynamic node low voltage swingwith dual supply, dual grounds and dual-Vt domino logic.Section V describes the effect of PVT variations on dominologic presented in section II, III, IV. Then conclusions are presented in section VI.

II. DUAL-RAIL DOMINO FOOTLESS CIRCUIT WITHSELF- TIMED PRECHARGE SCHEME (DRDFSTP):

Conventional domino circuits:In this section, several conventional domino circuits with

their own clocking schemes are briefly reviewed.

A. Dynamic DCVSL Footed Circuit (DDCVSLF):

Fig.1 shows AND/NAND dynamic DCVSL Footedcircuit. One of the disadvantages of this kind of dominocircuit is that the existence foot transistor slows the gates

somewhat, as it presents an extra series resistance. Moreover,simultaneous precharge may cause an unacceptable IR-dropnoise.

Fig.1. Dynamic DCVSL AND/NAND Footed gate

B. Dynamic DCVSL Footless Circuit (DDCVSLFL):

Fig.2 shows AND/NAND dynamic DCVSL Footlesscircuit. Two benefits come from the usage of footless dominogates: improved pull-down speed and reduced precharge

signal load. Main disadvantage is simultaneous precharge willcause short-circuit current.

Fig. 2. Dynamic DCVSL AND/NAND Footless gate

Salendra.Govindarajulu et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES

Vol No. 5, Issue No. 2, 319 - 331

ISSN: 2230-7818 @ 2011 http://www.ijaest.iserp.org. All rights Reserved. Page 319



C. Delayed-Reset Domino Circuit (DRDC ):

Fig.3 illustrates the delayed-reset domino AND/NANDcircuit [3]. However, the use of delay elements, together withthe need of both footed and footless cell libraries tends toincrease design complexity.

Fig:3. The delayed-reset domino AND/NAND circuit

D. Dual-Rail Data-Driven Dynamic Logic (D4

L):

D4L circuit uses input signals instead of precharge signalfor correct precharge and evaluation sequencing [5].

Correspondingly, clock-buffering and clock-distribution problems can be eliminated. Furthermore, the foot transistor can be eliminated without causing a short-circuit problem. A

D4L two-input AND/NAND gate is shown in Fig.4.

Fig.4. Dual-Rail Data-Driven Dynamic AND/NAND Logic (D

4L)

Dual-Rail Domino Footless Circuit with Self- Timed

Precharge Scheme (DRDFSTP):

The presence of the foot transistor in the conventional

dynamic DCVSL circuit shows the gate somewhat, as it presents an extra series resistance. To safely remove the

transistor, two constraints must be met: (1) gate changes toevaluation phase before valid input come; (2) gate changes to precharge phase only after inputs change to zero. We proposea footless duail-rail domino circuit with self-timed precharge

scheme to realize a high performance footless domino circuitwhile meeting the constraints mentioned above. It is expectedthat the peak of precharge current could be reduced due to theself-timed precharge scheme. Fig. 9 shows the AND/NANDgate of the proposed footless dual-rail domino circuit with

self-timed precharge scheme. The self-timed precharge controllogic consists of static CMOS inverter whose source of NMOS

transistors are tied to input signals, which generate sub- precharge signals (PC1-PC4) from precharge signal P in casesof the corresponding input signals are zero. The PMOS precharge tree above the pull down network (PDN) is used for precharging the corresponding gate.

Fig:5. Dual-rail footless domino AND/NAND gate with self-timed precharge scheme.

Simulation results:

In this work, we have implemented a Dynamic DCVSLcircuit, Dual-Rail Data-Driven Dynamic Logic and a proposedcircuit Dual-Rail Domino Footless Circuit with Self-Timed

Precharge Scheme. The results of simulation are shown in the below TABLES1-3.

Table1. AND/NAND GATE

Technique Power (µw)

CriticalDelay(ns)

PDP(10

-15w-

s)

Area(µ.sqm)

DDCVSLF 7.6 0.088 0.6688 69.62

DDCVSLFL

152 0.025 3.8 65.41

DRDC 205 0.137 28.085 252.9

D4L 72.555 0.111 8.053606 93.3

DRDFSTP 7.676 0.042 0.322392 177.6


Vol No. 5, Issue No. 2, 319 - 331




Table2. OR/NOR GATE

Table3. XOR/XNOR GATE

III. REDUCED DYNAMIC SWING DOMINO (RDS-DOMINO):

A. Reduced – Swing Domino with Dual supply (RSDLS):

The first circuit configuration proposed to reduce thedynamic node voltage swing is obtained by simply altering theappropriate supply voltages of the standard domino gates asshown in fig.6.

Fig.6. Reduced–Swing Domino with Dual Supply

This circuit is here after referred to as a reduced–swing(RSDLS) domino gate with dull supply.

B. Reduced–Swing Domino with Single supply (RSSLS):

The RSDLS circuit shown above is simplified by replacingthe extra supply voltages with transistors providing the desiredthreshold voltage drops. The configuration is shown in fig.7.

Fig.7.Reduced – Swing Domino with Single supply

C. Reduced Swing Mirror Domino (RSMRD):

This is one of the alternative approaches for havingreduced swing, which is shown in fig.8. This is anarrangement in which the precharge and footer transistors are

exchanged with an NMOS and PMOS transistor respectively.

Fig.8.Reduced Swing with Mirror Domino

This arrangement dictates that the precharge and evaluatecycles be reversed with regard to clock. That is, clock beginshigh corresponding to precharge and clock goes low

corresponding to the evaluate cycle. Given this arrangement,the voltage swing of the internal dynamic node is limited by

the transistor thresholds. The supply voltage and theinput/output signals all remain unmodified.

Simulation results:

The benchmark circuits using the stated four techniques areimplemented. The figures of merits used to compare thesetechniques are power consumption, propagation delay and power delay product (PDP). The benchmark circuits

implemented are OR2 gate, AND2 gate, XOR2 gate, 16-bitFull adder, 16-bit Comparator , D-flip flop and 4-bit LFSR (Linear Feedback Shift Register).

Technique Power

(µw)

Critical

Delay(ns)

PDP

(10-15

w-s)

Area

(µ.sqm)

DDCVSLF 11.7 0.032 0.3744 99.2

DDCVSLFL

99.023 0.032 3.1687 92.17

DRDC 231 0.091 21.021 391.9

D L 16.802 0.029 0.487258 100.5

DRDFSTP 11.642 0.04 0.46568 200.13

Technique Power (µw)

CriticalDelay(ns)

PDP(10

-15w-

s)

Area(µ.sqm)

DDCVSLF 7.58 0.087 0.65946 74.82

DDCVSLFL

145 0.090 13.05 66.59

DRDC 220 0.403 88.66 290

D L 10.163 0.112 1.138256 78.48

DRDFSTP 7.583 0.042 0.318486 130.18


Vol No. 5, Issue No. 2, 319 - 331

ISSN: 2230-7818 @ 2011 http://www.ijaest.iserp.org. All rights Reserved. 21



Table4. Optimum values of different techniques of 2-input OR Gate

Table5. Optimum values of different techniques of 2-input

AND Gate

Table6. Optimum values of different techniques of 2-inputXOR Gate

Table7. Optimum values of different techniques of 16-bit

adder

Table8. Optimum values of different techniques for 16-bit

comparator

Table9. Optimum values of different techniques for D-Flipflop

Table10. Optimum values of different techniques for 4-bitLFSR

Techniques Power(µ

Watts) Delay(ns)

Power

Delay

Product

(*10-15 Watt-Sec)

RSDLS 65nm 0.007 0.032 0.0000224

RSSLS 65nm 17.094 0.023 0.393162

RSMRD 65nm 0.0322 0.016 0.0005152

Std-

Domino 65nm 0.433 0.054 0.023382

Techniques

Power(µ

watts)

Delay

(ns)

Power Delay

Product

(*10-15 Watt-

Sec)

RSDLS 65nm 21.635 0.026 0.56251RSSLS 65nm 32.102 0.017 0.545734

RSMRD 65nm 0.355 0.044 0.01562

Std-

Domino 65nm 0.506 0.102 0.051612

TECHNIQUES

Power

(µ

Watts) Delay(ns)

Power

Delay

Product

(*10-15

Watt-Sec)

RSDLS 65nm 22.881 0.046 1.052526

RSSLS 65nm 23.002 0.067 1.541134

RSMRD 65nm 1.592 0.067 0.106664

Std-

Domino 65nm 1.711 0.102 0.174522

Techniques

Power

(µ

Watts) Delay(ns)

Power

Delay

Product

(*10-15

Watt-Sec)

RSDLS 65nm 0.15 0.025 0.00375

RSSLS 65nm 0.649 0.073 0.009735

RSMRD 65nm 1.909 1.682 0.03818

Std-

Domino 65nm 0.586 24.825 0.015236

Techniques

Power

Delay

(ns)

Power Delay

Product

(m

Watts)

(*10 -12 Watt-

Sec)

RSDLS 65nm 1.053 0.069 0.072657

RSSLS 65nm 1.07 0.058 0.06206

RSMRD 65nm 6.901 0.041 0.282941

STD-

DOMINO 65nm 0.833 0.033 0.027489

Techniques

Power

(m

Watts) Delay(ns)

Power

Delay

Product

(*10-12

Watt-Sec)

RSDLS 65nm 0.01925 0.118 0.0022715

RSSLS 65nm 0.115 0.083 0.009545

RSMRD 65nm 0.118 0.075 0.00885

STD-

DOMINO 65nm 0.05964 0.270 0.0161028

Techniques

Power

Delay

(ns)

Power Delay

Product

(m

Watts)

(*10-12Watt-

Sec)

RSDLS 65nm 0.0244 0.780

0.01

9032

RSSLS 65nm 0.683 0.275

0.18

7825

RSMRD 65nm 0.293 0.299

0.08

7607

STD-

DOMINO 65nm 1.455 2.156

3.13

698


Vol No. 5, Issue No. 2, 319 - 331




IV. DYNAMIC NODE LOW VOLTAGE SWING DOMINO

LOGIC CIRCUITS WITH DUAL POWERS, GROUNDS

AND DUAL VT:

This section discusses several dual threshold voltagedomino circuit design techniques to reduce the power

dissipation of domino logic while simultaneously improving

noise immunity. The benefits are achieved by limiting thevoltage swing of the internal dynamic node in a typical

domino gate. This dynamic storage node is the node connectedto the input of the output inverter of a domino gate as shownin fig.9.

Fig.9. Dynamic node low voltage swing domino logic circuitThe above circuit is used to reduce the voltage swing at the

dynamic node of a domino gate. A complete analysis of theeffects of the reduced swing at the dynamic node on both noisetolerance and propagation delay is presented with respect tospecific circuit configurations below.

A. Single V t domino logic circuit with keeper: (NORMAL)

The single Vt domino logic circuit with keeper is shown inFig.10. Keeper circuit is used to maintain the voltage level atdynamic node which also increases the noise immunity. Thevoltage at the dynamic node should be VDD but gets

diminished due to several reasons, by using the keeper in theabove circuit with P2, N2 transistors pair forming inverter turns ON Pk transistor which pulls dynamic node to VDD.

Fig.10. Domino logic circuit with keeper.

B.Single V t domino logic circuit with dual power supply, dual ground : (DUAL SUPPLY)

The single Vt domino logic circuit with dual power supply,dual ground is shown in Fig.11.

Fig.11. The dynamic node low voltage swing domino circuit

technique with dual power supplies and ground voltagesVDDL<VDD , VgndH>Vgnd

C. Dual V t Domino Logic circuit With Dual power supply,Dual Ground(N1 High Threshold): (DUAL N1)

The dual Vt domino logic circuit with dual power supply,dual ground (N1 high threshold) is shown in Fig.12. The NMOS transistor in the output inverter has high Vt. Shortcircuit current is therefore reduced only in the evaluation phase if the inputs are high. Hence evaluation speed of the

circuit is higher as compared to N1, P1 high thresholdtechnique.

Fig.12. The dynamic node low voltage swing domino circuittechnique with dual power supplies and ground voltages

VDDL<VDD , VgndH>Vgnd and with N1 high threshold

D. Dual V t domino logic circuit with dual power supply,dual ground (N2 ground):

The dual Vt domino logic circuit with dual power supply,

dual ground (N1 high threshold) is shown in Fig.13. N2 FET


Vol No. 5, Issue No. 2, 319 - 331




is grounded; these modifications are made to the basic circuitin order to analyze the variations in the parameters like power,delay, area, power delay product (PDP) and to find the

efficient technique.

Fig.13. The dynamic node low voltage swing domino circuittechnique with dual power supplies and ground voltages

VDDL<VDD , VgndH>Vgnd and with N2 Ground

E. Dual V t domino logic circuit with dual power supply,

dual ground (N1, P1 high threshold): (DUAL N1,P1)

The dual Vt domino logic circuit with dual power supply,dual ground (N1, P1 High Threshold) is shown in Fig.14. Theshort circuit current produced by the output inverter is

suppressed during both the precharge and evaluation phases of operation, since the NMOS and PMOS transistors in theoutput inverter have high Vt. However, evaluation speed isalso degraded due to the weaker pull-up strength of high V t

PMOS transistor.

Fig.14. The dynamic node low voltage swing domino circuit

technique with dual power supplies and ground voltagesVDDL<VDD , VgndH>Vgnd and with N1, P1 high thresholds

F. Dual V t domino logic circuit with dual power supply,

dual ground (Pk, P2, N1 high threshold):

The dual Vt domino logic circuit with dual power supply,

dual ground (Pk, P2, N1 high threshold) is shown in Fig15.

P2, N1 FETs threshold voltages are increased, these

modifications are made to the basic circuit in order to analyzethe variations in the parameters like power, delay, area, power delay product (PDP) and to find the efficient technique.

Fig.15. dynamic node low voltage swing domino circuittechnique with dual power supplies and ground voltages

VDDL<VDD , VgndH>Vgnd and with N1, P2, Pk high thresholds

G. Dual V t domino logic circuit with dual power supply,dual ground (P11,PK,P1 high threshold):

The dual Vt domino logic circuit with dual power supply,dual ground (P11, PK, P1 High threshold) is shown in fig.16.P11, Pk, P2 FETs threshold voltages are increased, thesemodifications are made to the basic circuit in order to analyze

the variations in the parameters like power, delay, area, power delay product (PDP) and to find the efficient technique.

Fig.16. dynamic node low voltage swing domino circuit

technique with dual power supplies and ground voltagesVDDL<VDD , VgndH>Vgnd and with Pk, P1, P11 High thresholds

Simulation results:

In this work, the benchmark circuits using the stated seventechniques are implemented. The benchmark circuitsimplemented are OR2, AND2, XOR2, 16-bit Full Adder, 16-

bit Comparator, D-Latch, 4-bit LFSR. Here the results aregiven for 16-bit Full Adder, 16-bit Comparator, D-Latch, 4-bitLFSR.


Vol No. 5, Issue No. 2, 319 - 331




Table11. Optimum values of different techniques for 16-bitadder

S.N

o

TECHNIQU

ES

POWER(m

w)

DELAY(

ns)

PDP(10-12

w-s)

Area(mic

ro

sq.meter)

1 NORMAL 11.062 127.081

1405.7589

6 12809.5

2

N2

GROUND 10.958 99.218

1087.2308

44 12826.9

3

DUAL

POWER

SUPPLY 11.402 100.63

1147.3832

6 13782

4 PK ,P11, P1 12.088 61.160 739.30208 12159.48

5 PK ,P2, N1 20.15 42.118 848.6777 15409.67

6

DUAL P1,

N1 21.88 100.633

2210.8500

4 15269

7 DUAL N1 10.245 90.907

931.34221

5 10371


comparator

S.N

O

TECHNIQU

ES

POWER(m

w)

DELAY(

ns)

PDP(10-12

w-s)

Area(mic

ro

sq.meter)

1 NORMAL 10.475 104.86 1098.4085 18914

2

N2

GROUND 8.204 156.921

1287.3798

84 19316

3

DUAL

POWER

SUPPLY 7.795 209.5 1633.0525 18329.6

4 PK ,P11, P1 8.457 150.312

1271.1885

8 18369.4

5 PK ,P2, N1 8.506 148.72

1265.0123

2 20240.6

6

DUAL P1,

N1 10.432 119.209

105.00109

31 18453

7 DUAL N1 8.56 149.478

1279.5316

8 18840


LFSR

S.NOTECHNIQU

ESPOWER(m

w)DELAY(

ns)

PDP(10-

12 w-s) Area(mic

rosq.meter)

1 NORMAL 4.587 6.797

31.1778

39 2255.05

2

N2

GROUND 2.976 8.245

24.5371

2 2493.05

3

DUAL

POWER

SUPPLY 2.882 7.434

21.4247

88 2472.36

4 PK ,P11, P1 3.08 5.436

16.7428

8 2468.4

5 PK ,P2, N1 2.929 5.452

15.9689

08 2482.7

6

DUAL P1,

N1 2.889 5.409

15.6266

01 2463.3

7 DUAL N1 2.968 5.404

16.0390

72 2483.34

Table 14. Optimum values of different techniques for D-Latch

S.N

O

TECHNIQU

ES

POWER(m

w)

DELAY(n

s)

PDP(10-12 w-s)

Area(mic

ro

sq.meter)

1 NORMAL 0.158 0.572

0.09037

6 215.56

2

N2

GROUND 0.163 0.467

0.07530

6 254.92

3

DUAL

POWER

SUPPLY 0.22 0.535 0.1177 261.41

4 PK ,P11, P1 0.169 0.385

0.06506

5 258.69

5 PK ,P2, N1 0.169 0.383

0.06472

7 262.885

6

DUAL P1,

N1 0.169 0.368

0.06219

2 256.11

7 DUAL N1 0.169 0.358

0.06050

2 262.59


Vol No. 5, Issue No. 2, 319 - 331




V. PROCESS, VOLTAGE AND TEMPERATURE

VARIATIONS (PVT) ON THE PERFORMANCE OF

DOMINO LOGIC:

The effect of PVT variations on the domino logic circuit

techniques which are explained in sections II, III, IV are

studied and analyzed in this section. The process variations

considered are VTHO (Threshold voltage at zero bias), TOXE

(Oxide layer thickness) and UO (carrier mobility). The

- The PVT variances

on the domino logic in sections II, III, IV are given in below

Tables15-23.

PVT Variations for section II:

Table15.PROCESS VARIATIONS (V AND T CONSTANT)BENCHMARK

CIRCUITS

AND/NAND OR/NOR XOR/XNOR

VTHO=

0.3

TOXE=

0.7

UO=0.0

30

VTHO=

0.35

TOXE=

1.1

UO=0.0

55

VTHO=

0.4

TOXE=

1.6

U0=0.08

VTHO=

0.3

TOXE=

0.7

UO=0.0

30

VTHO=

0.35

TOXE=

1.1

UO=0.0

55

VTHO=

0.4

TOXE=

1.6

U0=0.08

VTHO=

0.3

TOXE=

0.7

UO=0.0

30

VTHO=

0.35

TOXE=

1.1

UO=0.0

55

VTHO=

0.4

TOXE=

1.6

U0=0.08

Dynamic

DCVSL

Footed

POWER

DISSIPATIO

N(µW)

7.520 7.6 7.623 7.565 7.58 7.45 11.330 11.7 11.23

ION

(ma)

0.120 0.250 0.358 0.120 0.250 0.358 0.120 0.250 0.358

IOFF

(na)

2 0 0 2 0 0 2 0 0

Dynamic

DCVSL

Footless

POWER

DISSIPATIO

N

(µW)

100 152 153 102 145 161 98.427 99.023 99.400

ION

(ma)

0.120 0.250 0.358 0.120 0.250 0.358 0.120 0.250 0.358

IOFF

(na)

2 0 0 2 0 0 2 0 0

Delay Reset

Domino

Circuit

POWER

DISSIPATIO

N

(µW)

201.872 205 204.347 94.254 220 221.392 230.013 231 231.925

ION

(ma)

0.051 0.107 0.153 0.051 0.107 0.105 0.051 0.107 0.105


Vol No. 5, Issue No. 2, 319 - 331




IOFF

(na)

1 0 0 1 0 0 1 0 0

Duail-Rail

Data Driven

Dynamic

Logic

POWER

DISSIPATIO

N

(µW)

48.316 72.555 85.268 8.846 10.163 10.475 13.914 16.802 13.85

ION

(ma)

0.120 0.250 0.358 0.120 0.250 0.358 0.12 0.250 0.358

IOFF

(na)

2 0 0 2 0 0 2 0 0

Foot Less

Duail-Rail

Domino

Circuit with

Self Timed

Precharge

Scheme

Logic

POWER

DISSIPATIO

N

(µW)

7.446 7.676 7.765 7.400 7.583 7.773 11.61 11.642 10.007

ION

(ma)

0.120 0.205 0.358 0.120 0.205 0.358 0.120 0.250 0.247

IOFF

(na)

2 0 0 2 0 0 2 0 0

Table16.VOLTAGE VARIATIONS (P AND T CONSTANT)BENCHMARK

CIRCUITS


VDD=0.7 VDD=0.

8

VDD=1 VDD=0.

7

VDD=0.

8

VDD=1 VDD=0.

7

VDD=0.

8

VDD=1

Dynami

c

DCVS

L

Footed

POWER

DISSIPATION(µ

W)

7.152 7.153 7.6 7.141 7.524 7.58 9.345 11.809 11.7

ION(ma) 0.131 0.171 0.250 0.131 0.171 0.250 0.131 0.171 0.250

IOFF(na) 0 0 0 0 0 0 0 0 0

Dynamic

DCVS

L

Footles

s

POWER

DISSIPATION(µ

W)

100.714 101.621 152 102.185 145.317 145 98.264 99.821 99.023

ION(ma) 0.131 0.171 0.250 0.131 0.171 0.250 0.131 0.171 0.250

IOFF(na) 0 0 0 0 0 0 0 0 0

Delay

Reset

Domin

o

POWER

DISSIPATION(µ

W)

67.053 102 205 94.217 94.712 220 220.013 230.983 231


Vol No. 5, Issue No. 2, 319 - 331




Circuit ION(ma) 0.131 0.171 0.107 0.131 0.171 0.107 0.131 0.171 0.107

IOFF(na) 0 0 0 0 0 0 0 0 0

Duail-

Rail

Data

Driven

Dynami

c Logic

POWER

DISSIPATION(µ

W)

54.187 72.868 72.555 9.127 9.217 10.163 14.717 16.504 16.802

ION(ma) 0.131 0.171 0.250 0.131 0.171 0.250 0.131 0.171 0.250

IOFF(na) 0 0 0 0 0 0 0 0 0

Foot

Less

Duail-

Rail

Domin

o

Circuit

with

Self

Timed

Prechar

geScheme

Logic

POWER

DISSIPATION(µ

W)

7.885 7.278 7.676 7.317 7.155 7.583 11.521 11.504 11.642

ION(ma) 0.131 0.171 0.250 0.131 0.171 0.250 0.131 0.171 0.250

IOFF(na) 0 0 0 0 0 0 0 0 0

Table17.TEMPERATURE VARATIONS (P AND V CONSTANT)BENCHMARK

CIRCUITS


-73 27 127 -73 27 127 -73 27 127

Dynamic

DCVSL

Footed

POWER

DISSIPATION(µ

W)

7.503 7.6 7.768 7.425 7.58 8.025 11.369 11.7 11.691

ION(ma) 0.445 0.250 0.163 0.445 0.250 0.163 0.445 0.250 0.163

IOFF(na) 0 0 27 0 0 27 0 0 27

Dynamic

DCVSL

Footless

POWER

DISSIPATION(µW)

246 152 108 247 145 112 169 99.023 77.078

ION(ma) 0.445 0.250 0.163 0.445 0.250 0.163 0.445 0.250 0.163

IOFF(na) 0 0 27 0 0 27 0 0 27

Delay

Reset

Domino

Circuit

POWER

DISSIPATION(µ

W)

208.507 205 217.451 162 220 72.266 116 231 248.93

7

ION(ma) 0.190 0.107 0.069 0.190 0.107 0.069 0.107 0.107 0.069


Vol No. 5, Issue No. 2, 319 - 331




IOFF(na) 0 0 11 0 0 11 0 0 11

Duail-Rail

Data

Driven

Dynamic

Logic

POWER

DISSIPATION(µ

W)

94.835 72.555 59.951 4.072 10.163 11.788 5.767 16.802 22.507

ION(ma) 0.445 0.250 0.163 0.445 0.250 0.163 0.445 0.250 0.163

IOFF(na) 0 0 27 0 0 27 0 0 27

Foot Less

Duail-Rail

Domino

Circuit

with Self

Timed

Precharge

Scheme

Logic

POWER

DISSIPATION(µ

W)

7.555 7.676 8.355 7.408 7.583 8.358 9.024 11.642 13.708

ION(ma) 0.445 0.250 0.163 0.445 0.250 0.163 0.445 0.250 0.163

IOFF(na) 0 0 27 0 0 27 0 0 27

PVT Variations for section III:

Table18.PROCESS VARIATIONS (V AND T CONSTANT)BENCHMARKCIRCUI

TS

AND2 OR2 XOR2 D-LATCH 4-BITLFSR

VTHO

=0.3

TOXE

=0.7

UO=0.

030

VTHO

=0.4

TOXE=

1.6

U0=0.8

VTHO

=0.3

TOXE=

0.7

UO=0.

030

VTHO

=0.4

TOXE=

1.6

U0=0.8

VTHO=0.

3

TOXE=0.7

UO=0.030

VTHO=0.

4

TOXE=1.

6

U0=0.8

VTHO=

0.3

TOXE=0

.7

UO=0.0

30

VTHO

=0.4

TOXE

=1.6

U0=0.8

VTHO=

0.3

TOXE=

0.7

UO=0.0

30

VTHO=

0.4

TOXE=

1.6

U0=0.8

STD

DOMINO POWER

DISSIPAT

ION(µW)

6.238 18.390 15.099 0.846 11.264 31.786 31.281 89.351 157 451

ION(ma) 0.120 0.358 0.051 0.153 0.120 0.358 0.051 0.183 0.051 0.153

IOFF(na) 2 0 1 0 2 0 1 0 1 0

RSSLS

POWER

DISSIPATION(µW)

11.958 17.044 11.325 15.834 15.910 22.471 54.203 76.475 264 389

ION(ma) 0.051 0.139 0.120 0.358 0.51 0.153 0.051 0.139 0.051 0.153

IOFF(na) 1 0 2 0 1 0 0 0 1 0

RSDLS

POWER

DISSIPAT

ION(µW)

7.90 3.604 0.004 0.004 29.521 4.719 37.451 34.612 778 393

ION(ma) 0.449 0.438 0.304 0.280 2.794 0.438 7.012 0.449 2.794 7.012


Vol No. 5, Issue No. 2, 319 - 331




IOFF(na) 6 1 2 0 37 1 9 6 37 9

RSMRD

POWER

DISSIPAT

ION(µW)

8.109 13.437 0.234 0.227 7.254 12.033 30.259 49.151 284 0.591

ION(ma) 0.120 0.358 0.120 0.358 0.12 0.358 0.120 0.358 0.120 0.358

IOFF(na) 2 0 2 0 2 0 2 0 2 0

Table19.VOLTAGE VARIATIONS (P AND T CONSTANT):BENCHMARKCIRCUITS AND2 OR2 XOR2 D-LATCH 4-BITLFSR

VDD=0.

7

VDD=0.

8

VDD=0

.7

VDD=0.

8

VDD=0.

7

VDD=0.

8

VDD=0.

7

VDD=0.

8

VDD=0.

7

VDD=0.

8

STD

DOMINO POWER

DISSIPATION(

µW)

11.878 12.263 0.558 26.48 15.438 18.255 38.655 47.105 361 348

ION(ma) 0.250 0.250 0.250 0.107 0.250 0.250 0.107 0.107 0.107 0.107

IOFF(na) 0 0 0 0 0 0 0 0 0 0

RSSLS POWER

DISSIPATION(

µW)

2.598 6.081 6.824 11.221 0.7 6.97 8.108 26.114 41.306 125

ION(ma) 0.107 0.107 0.107 0.107 0.958 0.107 0.107 0.107 1.337 0.107

IOFF(na) 0 0 0 0 0 0 0 0 0 0

RSDLS

RSMRD

POWER

DISSIPATION(

µW)

1.464 2.431 0.003 0.003 1.167 4.329 5.743 14.256 54.152 156

ION(ma) 1.337 1.337 0.446 0.446 1.337 1.337 1.337 1.337 1.337 1.337

IOFF(na) 0 0 0 0 0 0 0 0 0 0

POWER

DISSIPATION(µW)

0.171 0.375 0.152 0.176 0.737 0.889

0.788

0.942 2.410 2,737

ION(ma) 0.120 0.120 0.594 0.594 0.594 0.594

IOFF(na) 2 2 0 0 0 0


Vol No. 5, Issue No. 2, 319 - 331




Table20.TEMPERATURE VARATIONS (P AND V CONSTANT)BENCHMARKCIRCUITS AND2 OR2 XOR2 D-LATCH 4-BITLFSR

127 -73 127 -73 127 -73 127 -73 127 -73

STD DOMINO

POWER

DISSIPATION

(µW)

8.550 54.746 20.057 138 16.108 92.667 365 112 184

2

564

ION(µA) 0.163 1.193 0.069 0.530 0.069 1.193 0.655 0.190 0.65

5

0.190

IOFF(nA) 27 0 11 0 11 0 0 0 0 0

RSSLS

POWER

DISSIPATION(µW)

10.166 17.435 9.406 18.880 18.206 6.690 58.01

8

17.873 299 114

ION

(µA)

0.266 0.586 0.266 0.586 0.266 0.586 0.266 0.586 0.586

IOFF(nA) 3762 0 3762 0 3762 0 3762 0 0

RSDLS

POWER

DISSIPATION

(µW)

14.136 0.128 0.004 0.004 30.618 0.714 16.39

7

1.782 24.4

20

267

ION

(µA)

0.234 0.320 0.169 0.184 0.234 0.320 1.470 1.193 1.19

3

1.474

IOFF 196 0 54 0 186 0 0 0 0 0

RSMRD POWER

DISSIPATION

(µW)

9.715 12.585 0.302 0.233 7.392 13.922 28.35

2

63.166 270 504

ION

(µA)

0.266 0.586 0.266 0.586 0.266 0.586 0.266 0.586 0.26

6

0.586

IOFF(nA) 3762 0 3762 0 3762 0 3762 0 376

2

0


Vol No. 5, Issue No. 2, 319 - 331




PVT Variations for section III:

Table21.PROCESS VARIATIONS (V AND T CONSTANT):BENCHMARKCIRCUIT

S

AND2 OR2 XOR2 D-LATCH 4-BITLFSR

VTHO

=0.3

TOXE=

0.7

UO=0.0

30

VTHO

=0.4

TOXE=

1.6

U0=0.8

VTHO

=0.3

TOXE=

0.7

UO=0.0

30

VTHO

=0.4

TOXE=

1.6

U0=0.8

VTHO=0.3

TOXE=0.7

UO=0.030

VTHO=0.

4

TOXE=1.6

U0=0.8

VTHO=

0.3

TOXE=0

.7

UO=0.03

0

VTHO

=0.4

TOXE

=1.6

U0=0.8

VTHO=

0.3

TOXE=0

.7

UO=0.03

0

VTHO=

0.4

TOXE=1

.6

U0=0.8

DSTDK

POWER

DISSIPAT

ION(µW)

0.397 0.369 7.270 1.134 11.292 33.026 126 322 464 1260

ION(ma) 0.120 0.358 0.120 0.358 0.120 0.358 0.051 0.153 0.051 0.153

IOFF(na) 2 0 2 0 2 0 1 0 1 0

DDSDG

POWER

DISSIPAT

ION(µW)

0.207 0.155 41.559 1.167 13.181 38.672 107 303 513 1412

ION(ma) 0.120 0.358 0.120 0.358 0.120 0.358 0.051 0.153 0.051 0.153

IOFF(na) 2 0 2 0 2 0 1 0 1 0

DN1HVT

POWER

DISSIPAT

ION(µW)

25.752 26.708 40.951 1.182 16.784 43.690 107 303 513 1412

ION(ma) 0.030 0.099 0.120 0.358 0.120 0.358 0.051 0.153 0.051 0.153

IOFF(na) 0 0 2 0 2 0 1 0 1 0

DN2GD

POWER

DISSIPAT

ION(µW)

0.030 0.030 41.359 15.148 16.762 46.690 108 303 485 1350

ION(ma) 0.120 0.358 0.120 0.358 0.120 0.358 0.051 0.153 0.051 0.153

IOFF(na) 2 0 2 0 2 0 1 0 1 0

DN1P1HV

T POWER

DISSIPAT

ION(µW)

23.576 26.875 40.977 1.350 16.823 43.733 107 303 513 1412

ION(ma) 0.030 0.099 0.120 0.358 0.120 0.358 0.051 0.153 0.051 0.153

IOFF(na) 0 0 2 0 2 0 1 0 1 0

DN1PKP2

POWER

DISSIPAT

0.042 0.04 0.105 0.104 1.121 2.31 108 303 513 1412


Vol No. 5, Issue No. 2, 319 - 331




ION(µW)

ION(ma) 0.03 0.099 0.120 0.358 0.120 0.358 0.051 0.153 0.051 0.153

IOFF(na) 0 0 2 0 2 0 1 0 1 0

DP11PKP

1 POWER

DISSIPATION(µW)

0.038 0.036 0.16 1.167 0.188 1.039 107 303 513 1412

ION(ma) 0.120 0.358 0.120 0.358 0.120 0.358 0.051 0.153 0.051 0.153

IOFF(na) 2 0 2 0 2 0 1 0 1 0

Table 22.VOLTAGE VARIATIONS (P AND T CONSTANT):

BENCHMARKCIRCUITS AND2 OR2 XOR2 D-LATCH 4-BITLFSR

VDD=0.

7

VDD=0.

8

VDD=

0.7

VDD=0.

8

VDD=0.

7

VDD=0.

8

VDD=0.

7

VDD=0.

8

VDD=0.

7

VDD=0.

8

DSTDK

POWER

DISSIPATION(µ

W)

0.321 0.160 0.590 1.221

4.032

17.155 123 159 444 545

ION(ma) 0.267 0.250 0.267 0.250 0.107 0.107 0.107 0.107 0.107 0.107

IOFF(na) 1 0 1 0 0 0 0 0 0 0

DDSDG

POWER

DISSIPATION(µ

W)

0.148 0.167 0.665 1.637 3.790 1.882 176 191 728 829

ION(ma) 0.267 0.250 0.267 0.250 0.250 0.250 0.107 0.107 0.107 0.107

IOFF(na) 1 0 1 0 0 0 0 0 0 0

DN1HVT

POWER

DISSIPATION(µ

W)

20.942 11.441

0.676

0.837 4.661 22.251 176 191 728 829

ION(ma) 0.177 0.065 0.267 0.250 0.250 0.250 0.107 0.107 0.107 0.107

IOFF(na) 0 0 1 0 0 0 0 0 0 0

DN2GD

POWER

DISSIPATION(µ

W)

0.033 46.685 0.898 8.877 16.823 22.963 176 191 730 830

ION(ma) 0.267 0.0250 0.267 0.250 0.250 0.250 0.107 0.107 0.107 0.107


Vol No. 5, Issue No. 2, 319 - 331




IOFF(na) 1 0 1 0 0 0 0 0 0 0

DN1P1H

VT

POWER

DISSIPATION(µ

W)

21.271 0.006 0.735 0.943 4.799 22.282 176 191 728 829

ION(ma) 0.177 0.065 0.267 0.250

0.250

0.250 0.107 0.107 0.107 0.107

IOFF(na) 0 0 1 0 0 0 0 0 0 0

DN1PKP2

POWER

DISSIPATION(µ

W)

0.048 0.039 0.105 0.091 1.263 1.474 176 191 728 829

ION(ma) 0.177 0.065 0.267 0.250 0.250 0.250 0.107 0.107 0.107 0.107

IOFF(na) 0 0 1 0 0 0 0 0 0 0

DP11PK

P1 POWER

DISSIPATION(µ

W)

0.044 0.128 0.137 82.172 0.803 0.924 176 191 728 829

ION(ma) 0.267 0.250 0.267 0.250 0.250 0.250 0.107 0.107 0.107 0.107

IOFF(na) 1 0 1 0 0 0 0 0 0 0

Table23.TEMPERATURE VARATIONS (P AND V CONSTANT)BENCHMARKCIRCUITS AND2 OR2 XOR2 D-LATCH 4-BITLFSR

127 -73 127 -73 127 -73 127 -73 127 -73

DSTDK

POWER

DISSIPATION

(µW)

0.538 0.392 7.027 25.626 16.495 38.504 273 673 658 1515

ION(µA) 0.266 0.445 0.266 0.445 0.266 0.190 0.266 0.586 1.82

0

1.996

IOFF(nA) 0 0 3762 0 3762 0 3762 0 0 0

DDSDG

POWER

DISSIPATION(µW)

0.619 0.149 9.725 16.85 21.230 54.302 160 364 758 1677

ION

(µA)

0.266 0.445 0.266 0.445 0.266 0.190 0.266 0.586 1.82

0

1.996

IOFF(nA) 0 0 3762 0 3762 0 3762 0 0 0

DN1HVT

POWER

DISSIPATION

(µW)

33.272 0.05 7.742 15.907 22.845 54.347 160 364 758 1677

ION

(µA)

0.098 0.133 0.266 0.445 0.266 0.190 0.266 0.586 1.82

0

1.996


Vol No. 5, Issue No. 2, 319 - 331




IOFF 1 0 3762 0 3762 0 3762 0 0 0

DN2GD

POWER

DISSIPATION

(µW)

0.030 10.236 68.123 0.137 25.864 23.145 160 364 730 1685

ION

(µA)

0.266 0.445 0.266 0.445 0.266 0.190 0.266 0.586 1.82

0

1.996

IOFF(nA) 3762 0 3762 0 3762 0 3762 0 0 0

DN1P1HV

T POWER

DISSIPATION

(µW)

33.269 76.778 7.850 16.035 22.878 54.378 160 364 758 1677

ION

(µA)

0.098 0.133 0.266 0.445 0.266 0.190 0.266 0.586 1.82

0

1.996

IOFF(nA) 1 0 3762 0 3762 0 3762 0 0 0

DN1PKP2

POWER

DISSIPATION(µW)

0.049 0.058 0.111 0.04 16.02 1.876 160 364 756 1677

ION(µA) 0.098 0.133 0.266 0.445 0.266 0.190 0.266 0.586 1.82

0

1.996

IOFF(nA) 1 0 3762 0 3762 0 3762 0 0 0

DPKP11P

1 POWER

DISSIPATION(µW)

0.045 0.157 0.171 0.164 1.124 1.174 160 364 75

8

167

9

ION(µA) 0.266 0.445 0.266 0.445 0.266 0.190 0.26

6

0.586 1.

82

0

1.99

6

IOFF(nA) 3762 0 3762 0 3762 0 3762 0 0 0

V. CONCLUSIONS

This work consists of four different parts. In section II, thecircuits Dynamic DCVSL footed circuit, Dynamic DCVSLfootless circuit; Dual-Rail Data-Driven Dynamic Logic and

Dual-rail Footless domino gate with self-timed prechargescheme are successfully implemented using CMOS dominologic. The proposed circuits have offered an improved performance in power dissipation, speed and noise tolerance

when compared with standard domino circuit.

In section III, an attempt has been made to simulate the

benchmark circuits AND2, OR2, XOR2, 16-bit full adder, 16- bit comparator, D-flip-flop, 4-bit LFSR by the three reduced

swing domino logic circuits. The proposed circuits haveoffered an improved performance in power dissipation, speedand noise tolerance when compared with standard dominocircuit. As it is observed from the results, of all the three

reduced swing circuits, reduced swing domino with dualsupply has low power dissipation, PDP and more tolerance tonoise.

In section IV, the circuit techniques employing dualthresholds, dual voltages, and dual grounds are presented for simultaneously reducing power dissipation and delay in

domino circuits and also to increase the noise immunity. The benchmark circuits AND2, OR2, XOR2, 16-bit full adder, 16- bit comparator, D-flip-flop, 4-bit LFSR are simulated with the proposed different energy efficient domino logic circuit

techniques in 65nm technology. From the results, it isobserved that the proposed logic technique which is dualthreshold, dual ground and dual supply voltage with N2 highthreshold shows good performance when compared to single

threshold (vt) domino logic techniques. Hence, it is concludedthat the proposed designs will provide a platform for designinghigh performance and low power digital circuits and high

noise immune digital circuits such as, processors andmultipliers.

In section V, an attempt has been made to study the effectof the PVT variations on the domino circuits with differenttechniques given in sections II, III, IV. As it is observed from

the results, when process variations decrease power dissipation increases, and vice versa. When temperaturevariations increase, power dissipation increases and vice versa.When voltage variations decrease power dissipation decreases.


Vol No. 5, Issue No. 2, 319 - 331




REFERENCES

[1] L. G. Heller, W. R. Griffin, J. W. Davis, and N. G. Thoma,“Cascode voltage switch logic: A differential CMOS logic family,”in Proc. IEEE Int. Solid-State Circuits Conf., pp. 16-17, 1984.

[2] P. Ng, P. T. Balsara, and D. Steiss, “Performance of CMOSDifferential Circuits,” IEEE J. of Solid-State Circuits, vol. 31, no.6, pp. 841-846, June 1996.

[3] P. Hofstee, et al., “A 1 GHz Single-Issue 64b PowerPC

Processor,” in Proc. IEEE Int. Solid-State Circuits Conf., pp. 92-93, 2000.[4] J. Wang, S. Shieh, C. Yeh, and Y. Yeh, “Pseudo-Footless

CMOS Domino Logic Circuits for High-Performance VLSIDesigns,” in Proc. Int. Symp. on Circuits and Systems, vol. 2, pp.401-404, 2004.

[5] R. Rafati, A. Z. Charaki, G. R. Chaji, S. M. Fakhraie, and K. C.Smith, “Comparison of a 17b Multiplier in Dual-Rail Domino andin Dual-Rail D

3L (D

4L) Logic Styles,” in Proc. Int. Symp. on

Circuits and Systems, vol. 3, pp. 257-260, 2002.[6] S. Mutoh et al., “1-V power supply high-speed digital

circuit technology with multithreshold-voltage CMOS,” IEEE J.Solid-State Circuits, vol.30, pp. 847–854, Aug. 1995.

[7] V. Kursun and E. G. Friedman, “Domino logic with dynamic bodybiasedkeeper,” in Proc. Eur. Solid-State Circuits Conf., Sept.

2002, pp.675–678.[8] “Variable threshold voltage keeper for contention reduction in

dynamic circuits,” in Proc. IEEE Int. ASIC/SOC Conf., Sept.2002, pp.314–318.

[9] S. Borkar, .Low Power Design Challenges for the Decade,.Proceedings of the IEEE/ACM Design Automation Conference,pp. 293-296, June 2001.

[10] P. Srivastava, A. Pua, and L. Welch, .Issues in the Design of

Domino Logic Circuits, Proceedings of the IEEE Great LakesSymposium on VLSI, pp. 108-112, February 1998.

[11] G. Balamurugan and N. R. Shanbhag, .Energy-efficientDynamic Circuit Design in the Presence of Crosstalk Noise,.Proceedings of the IEEE International Symposium on LowPower Electronics and Design, pp. 24-29, August 1999.

[12]. S.Govindarajulu, Dr.T.Jayachandra Prasad “Design of HighPerformance Dynamic CMOS Circuits in Deep submicronTechnology” International Journal of Engineering Science andTechnology, Vol.2 (7), 2010, pp.2903-2917, ISSN:0975-5462

[13]. S.Govindarajulu, Dr.T.Jayachandra Prasad et.al.“Low Power, Reduced Dynamic Voltage Swing Domino LogicCircuits” Indian Journal of Computer Science and Engineering,2010 pp.74-81, ISSN:0976-5166.

[14]. S.Govindarajulu, Dr.T.Jayachandra Prasad “Energy efficientReduced Swing Domino Logic Circuits in 65 nm Technology”International Journal of Engineering Science and Technology,Vol.2 (6), 2010, pp.2248-2257, ISSN:0975-5462.

[15]. S.Govindarajulu, Dr.T.Jayachandra Prasad et.al. “Design of High Performance Arithmetic and Logic Circuits in DSMTechnology”International Journal of Engineering andTechnology, Vol.2 (4), 2010, pp.285-291, ISSN:0975-4024.

[16]. S.Govindarajulu, Dr.T.Jayachandra Prasad et.al. “HighPerformance VLSI Design Using Body Biasing in DominoLogic Circuits” International Journal of Computer Science andEngineering, Vol.2, No.5, 2010 pp.1741-1745, ISSN:0975-

3397.[17]. S.Govindarajulu, Dr.T.Jayachandra Prasad et.al. “Design of

Low Power, High Speed, Dual Threshold Voltage CMOSDomino Logic Circuits with PVT Variations” International

Journal of Electronic and Engineering Research, Vol.2,No.5, 2010 pp.619- 629, ISSN:0975-6450.

AUTHORS BIODATA:

1Salendra.Govindarajulu:- He is working as an Associate Professor in

the Dept. of Electronics & Communication Engg. at RGMCET, Nandyal,

Andhra Pradesh, India. He presented more than 25 International/National

Technical Papers. He is a Life Member of ISTE, New Delhi. He is a member

of IAENG. His interest includes Low Power VLSI CMOS design.

2Dr.T.Jayachandra Prasad:- He is working as a Principal and Professor

in the Dept. of Electronics & Communication Engg. at RGMCET, NandyalAndhra Pradesh, India. He presented more than 50 International/National

Technical Papers. He is Life Member in IE (I), CALCUTTA, Life Member in

ISTE, NEW DELHI, Life Member in NAFEN, NEW DELHI, and IEEE

Member. His interest includes Digital Signal Processing.


Vol No. 5, Issue No. 2, 319 - 331





Vol No. 5, Issue No. 2, 319 - 331

33.ijaest vol no 5 issue no 2 energy efficient domino vlsi circuits and their performance with pvt...

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