3 stm32l0 ulp peripherals

STM32L0 ULP Peripherals

OBJECTIVES

• Introduce STM32L0 Ultra-Low-Power peripherals

• Highlight key features and discuss possible applications

• With focus on energy consumption optimizing enhancements

• Test some of the peripherals in operation (exercises)

2

After this presentation you will understand the benefits of Ultra-Low-Power peripherals included in STM32L0.

ULP Peripherals Overview

M0+ CORTEXTM-M0+ CPU

32 MHzWith MPU

8KB SRAM

2 x I2C

2 x USART

SW Debug Power SupplyReg 1.8V/1.5V/1.2V

DMA7 Channels

NVIC

2 x SPI

SysTick

AR

M ®

Lite

Hi-S

peed

Bus

Mat

rix /

Arb

iter

(max

32M

Hz)

PLLRCC

RTC / WUT

20B Backup Reg.

Fla

sh I/

FF

lash

I/F

64KBFlash Memory

2KBData EEPROM

USB 2.0 FS

Glass LCD Control.(up to 8x24)

Int. RC 16 MHz

Xtal 1-24MHz

Int. RC 37 kHz

Xtal 32,768 kHz

Int. RC 65K..4.2MHz

EXTI

AES Tiny

1 x 12-bit ADC19 channels / 1Msps

Temp Sensor

4 x 16-bit Timer

1 x 12-bit DAC

2 x COMP

2 x Watchdog(ind. & window)

3

TSC

RNG

37/51 I/Os

1x LPTIM

1 x LPUART

POR/PDR/BOR/PVD

Digital peripheralsReal-Time Clock (RTC)

Calendar

Block Diagram (RTC)

Asynchronous 7-bit Prescaler

Synchronous 15-bit Prescaler

=Alarm A Event

Calendar

Alarm A

RTC_CALIB

512 Hz

HSE / 32

RTCSEL [1:0]

LSE

LSI

RTCCLK

PREDIV_A [6:0] PREDIV_S [14:0]

RTC_TAMP1

RTC_TS

Backup Registers andRTC Tamper

Control registers

TimeStamp Registers TimeStamp Event

Tamper Event

RTC_REFIN

Smooth Calibration

1 Hz

COSEL

RTC_TAMP2

ssr(binary format)

5

Alarm B Alarm B Event

RTC_OUT

=

hh:mm:ss:ssrdd/mm/year

hh:mm:ss:ssrdd/mm/year

Day/date/month/year HH:mm:ss(12/24 format)

Prescaler/2, /4, /8, /16

Wake-Up

16-bit autoreloadTimer

OSELck_spre

Out

put

Con

trol

Wake-Up Event

Calendar

TimeDate

• The initialization or the reading of the calendar value is done through 3 shadow registers, SSR, TR and DR. The RTC TR and DR registers are in BCD format.

• SSR register represents the RTC Sub seconds register

RTC Calendar

DR TR

Day : Month : Date : Year

Shadow registers

Actual registers

12h/24h

SSR

6

hh : mm : ss : ssr

Wake-Up Timer (WUT)RTCCLK (LSE, 32.768 kHz)

Wake-Up

16-bit autoreloadTimer

Prescaler/2, /4, /8, /16

WakeUpCLK

7

Wake-Up Event

Synchronous 15-bit Prescaler

To Calendar

ck_spre

Asynchronous7-bit Prescaler

VALUE <0x00, 0x7F>

DEFAULT = 0x7F

VALUE <0x0000, 0x7FFF>

DEFAULT = 0xFF

1

23

VALUE <0x (1)0000, 0x(1)FFFF>

WakeUpCLK MIN_TIME MAX_TIME Resolution

1RTCCLK /2 121 µs 4 s 61 µs resolution

RTCCLK /16 976 µs 32 s 488 µs resolution

2ck_spre = 1Hz

1 s 18.2 h 1s resolution

3 18.2 s 36.4 h 1s resolution

BACKUP domain

RTC pins alternate functions

Tamper detection ( resets all RTC user backup registers)

Time Stamp detection: the calendar is saved in the time-stamp registers

Configurable level: low/high, interrupt request generation

Wake-Up:

Reference clock input: 50 / 60Hz precise signal resynchronization

Alarm Ouput: Alarm A, Alarm B and RTC Wakeup event signals

Clock calibration Output: 1 Hz / 512 Hz when using 32.768 kHz crystal

LSE (32 kHz)

RTC + 20 Bytes DataRTC output / Wakeup

Pin 2 / Tamper 1 / Timestamp

RCC CSR

Wakeup Logic

IWDG

Wakeup Pin 1 / Tamper 2

8

LSI (37 kHz)

Reference clock input

Smooth Digital Calibration

• Consists in masking/adding N (configurable) 32kHz clock pulses, fairly well distributed in a configurable window.

• A 1Hz output is provided to measure the quartz frequency and the calibration result.

• Calibration value can be changed on the fly.

9

Calibration window Accuracy Total range

8 s ±1.91 ppm [0 ±480ppm]

16s ±0.95 ppm [0 ±480ppm]

32s ±0.48 ppm [0 ±480ppm]

RTC registers write protection

• By default and after reset, the RTC registers are write protected to

avoid possible parasitic write accesses.

• DBP bit must be set in PWR_CR to enable RTC write access

• A Key must be written in RTC_WPR register.

• To unlock write protection on all RTC registers

• 1. Write ‘0xCA’ into the RTC_WPR register

• 2. Write ‘0x53’ into the RTC_WPR register

* Except for the clear of Alarm and Wakeup timer i nterrupt flags

Writing a wrong key reactivates the write protectio n.

1010

Tamper detection• 2 tamper pins and events

• Configurable active level for each event

• Configurable use of I/Os pull-up resistors

• Configurable pre-charging pulse to support different capacitance values

• 1, 2, 4 or 8 cycles

• Configurable filter:• Sampling rate

(128Hz, 64Hz, 32Hz, 16Hz, 8Hz, 4Hz, 2Hz, 1Hz)

• Number of consecutive identical events before issuing an interrupt to wake-up the MCU

(1, 2, 4, 8)

11

STM32Tamper switch

RTC_TAMPx

Capacitor is optional (filtering can be done by software)

Biasing is done using the I/O’s Pull-up resistor

• Reset of backup registers when tamper event detected

• Tamper event can generate a timestamp event

Digital peripheralsLPTIM

12

Low-Power Timer Block diagram 13

1 2 3

1 2 3

3-bit Prescaler

16-bit ARR

+ 16-bit Counter

16-bit Compare

Encoder

Registers

APB bus

GlitchFilter

GlitchFilter

GlitchFilter

MUX trigger

CLKMUX

APB clock

LSELSI

HSI16

Up/Down

s/wtrigger

up to 8 ext trigger

Input 2

Input 1

Output

LPTIM Glitch Filters 14

GlitchFilter

2 consecutive samples



CLK

INPUT

FilteredOUTPUT

Filtered glitches

2, 4 or 8 consecutive samples configuration

LPTIM as Waveform Generator

• 3 configurable waveforms• PWM waveform

• One Pulse waveform

• Set Once waveform

15

PWM

One Pulse

Set Once

POL = 0

LPTIMx_CMP

LPTIMx_ARR

LPTIMx_CNT

LPTIM as Encoder Interface

• Encoder mode• Same operation as Encoder mode on General Purpose Timers

• Only available when LPTIM runs in Continuous mode

16

CLK

INPUT1

INPUT2

COUNTER

1 2 3

LPTIM as External Pulse Counter 17

1 2

3-bit Prescaler

16-bit ARR

+ 16-bit Counter

16-bit Compare

GlitchFilter

CLKMUX

APB clockLSELSI

HSI16

Input 1

Output

1 2 3

3-bit Prescaler

16-bit ARR

+ 16-bit Counter

16-bit Compare

GlitchFilter

CLKMUX

APB clockLSELSI

HSI16

Input 1

Output

must be ‘000’

Sampling

Fully asynchronous operation

Digital peripheralsUSART

18

USART – Block Diagram 19

Tx

Rx

SCLK

nRTS/DE

nCTS

Transmit Data Register

Receive Data Register

Transmit.Receiver

IrDA SIR Encoder / Decoder

HW Flow Control

DMA Requests

IRQ Requests

Wakeupfrom STOP

DMA Control

Interrupt Control / Status

BaudRate

Generator

SCLK Control

Node Address

Wakeup Unit

ReceiveControl

TransmitControl

USART peripheral

Clocks

PCLKSYSCLKHSILSE

USART Features List 20

Frame • 7, 8, 9 DATA bits• 0.5, 1, 1.5, 2 STOP bits• Even, odd, none PARITY• Oversampling /8 and /16 (default)

Modes • Asynchronous LIN SmartCard (T=0, T=1) IrDA Basic MODBUS Multiprocessor communication Half duplex

• Synchronous (CLK line)

Other • DMA support• HW flow control (RTS, CTS lines)• Auto baudrate detection• Programmable data order (MSB/LSB)• Swappable Tx/RX pins• Wakeup from STOP (!!! no data loss !!!)

NO data loss on wakeup

4Mbps

Wakeup from STOP (USART) 21

Typical Wakeup from STOP flowchart:

After wakeup, the WUF bit is setAfter wakeup, the WUF bit is set

Go to STOP modeGo to STOP mode

Select the Wakeup eventSelect the Wakeup event

RXNE Start bit Address Match

Set the UESM bitSet the UESM bit

Select the USART clock source Select the USART clock source HSI LSE

( ) bit

WUSTOP

TM

tDWU

⋅+=

10

There is a deviation add-on, due

to wakeup time:

M is 0 for 8 bit, 1 for 9 bit frame

tWUSTOP is the time for wakeup

from STOP mode (typ. 4.2 usec)

The first byte is received correctly

if this timing is included in the

allowed overall deviation

Conditions:

Detection range: bit time from 16 to 65535 USART clock periods.

BRR must be a value different from 0.

Only oversampling by 16 allowed

USART – Automatic Baudrate Detection

2 patterns for auto-baudrate detection:

The auto-baudrate completed Baud rate register updated

ABRF flag set

T measured

T measured

22

USART – Synchronous Mode USART supports Full duplex synchronous communication mode

Another SPI like interface Full-duplex, three-wire synchronous transfer

USART Master mode only

Synchronous clock generated on (SCLK)

Programmable clock polarity (CPOL) and phase (CPHA)

Programmable Last Bit Clock Pulse generation (LBCL)

SlaveSCK

MISO

MOSI

NSS

MasterSCLK

RX

TX

Full Duplex

USART SPI

23

USART – Single Wire Half Duplex mode

USART2

TX

USART1

TX

VDD

R =

10

KΩ

USART supports Half duplex synchronous communication mode

Only TX pin is used (RX is no longer used)

Used to follow a single wire Half duplex protocol.

Half Duplex

24

USART – Smart Card Mode USART supports Smart Card Emulation ISO 7816-3

Half-Duplex, Clock Output (SCLK)

9Bits data, 1.5 Stop Bits in transmit and receive.

T = 0, T = 1 support

Programmable Clock Prescaler to guarantee a wide range clock input

USART

SCLK

TX

C1

C2

C3

C4 C8

C7

C6

C5

25

ISO 7816-2 Electrical contact layout

USART – IrDA SIR Encoder Decoder USART supports the IrDA SIR Specification

• Half-duplex, NRZ modulation,

• Max bit rate 115200 bps

• The pulse width is 3/16 bit duration in normal mode

• Low power mode: 1.42MHz <PSC < 2.12MHz

RX

SIR Encoder

SIR Decoder

USART

TX

IrDA transceiver

USART

IrDA

26

USART – RS485, RS422 Transceiver Control

The times are expressed in oversampling time units (1/8 or 1/16 of bit time)

The polarity can be selected by DEP bit

DE pin shared with RTS pin

DEAT

time

DEDT

time

DE signal

TX signal

RX

USARTTX

RS485 transceiver

DE

+

-

27

Digital peripheralsLow -Power UART (LPUART)

28

LPUART• LPUART includes all necessary hardware support to make

asynchronous serial communications possible with minimum power consumption

• With just the LSE 32.768 kHz it is possible to run at up to 9600 baud

• For this purpose, the baudrate generation has been changed comparing to the USART peripheral

• Can be kept enabled and clocked even during STOP mo de

29

SYSCLK

HSI16

LSE

APB (PCLK)

to LPUART

LPUART baudrate generation

Where: Tx/Rx_baud... desired baudrate

fck... LPUART clock source frequency

LPUARTDIV... coded on the the BRR register(LPUARTx_BRR value can’t be lower than 0x300)

30

Desired Baud rate Actual Baud rate LPUARTx_BRR % Error

2400 Bps 2400.17 Bps 0xDA7 0.007

9600 Bps 9608.94 Bps 0x369 0.093

Tx/Rx Baud =256 × fCK

LPUARTDIV

Assuming LSE (32.768 kHz) used as clock source

USART/LPUART feature listFeatures USART1/2 LPUART1

Programmable data word length (7,8 or 9 bits) • •

Configurable stop bits (1 or 2) • •

Hardware Flow Control (Modem, RS-485 transceiver) • •

Continuous communication using DMA • •

Multi-processor communication • •

Single wire half duplex mode • •

Dual clock domain and Wake-Up from STOP mode • •

Swappable Rx/Tx pin configuration • •

Synchronous mode •

Smartcard mode •

IrDA •

LIN •

Receiver timeout •

Modbus Communication •

Autobaudrate detection •

31

Digital peripheralsI2C

32

I2C Block Diagram

PCLK

RCC_CFGR_I2CxSEL

HSI16

SYSCLK I2C_CLK

RegistersPCLK

APB bus

Digital Noise Filter

AnalogNoise Filter

SMBA

SDA

Data control

Clock control

GPIOlogic

GPIO logic

SCL

SYSCFG_CFGR1 / I2C_PBx_FM+

SYSCFG_CFGR1 / I2C_PBx_FM+

33

AnalogNoise Filter

Digital Noise Filter

Wake-Up on address match

SMBus Alert ctrl. & status

WUPEN

SMBus PEC gen./check

MASTER clkcontrol

SLAVE clk. stretching

SMBusTimeout chck

Wakeup from STOP on address match

• When I2C_CLK clock is HSI, the I2C is able to wakeup MCU from STOP when it receives its slave address. All addressing mode are supported:

• During STOP mode and no address reception: HSI is switched off

• On START detection, I2C enables HSI, used for address reception

• Wakeup from STOP is enabled by setting WUPEN in I2C1_CR1

• The HSI oscillator must be selected as the clock source for I2CCLK in

order to allow wakeup from STOP.

• Clock stretching must be enabled to ensure proper operation

(NOSTRETCH=0)

34

2 configurable addresses

Easy Master mode management • For payload <= 255 bytes : only 1 write action needed !! (apart data rd/wr)

I2Cx_CR2 is written with :

• Data transfer managed by Interrupts (TXIS / RXNE) or DMA

AUTOEND

0 : Software end mode End of transfer SW control after NBYTES data transfer : • TC flag is set. Interrupt if TCIE=1.• TC is cleared when START or STOP is set by SW

If START=1 : RESTART condition is sent

1 : Automatic end mode STOP condition sent after NBYTES data transfer

START enable (START=1)Slave address configuration (SADD)Transfer direction (RD_WRN)Number of bytes to be transferred (NBYTES = N)Autoend enable (AUTOEND=1) => peripheral will generate STOP automatically after N bytes are sent

35

Analog peripheralsPower Supply Supervisors

36

Power Supply monitoring/ Reset circuitry 37

Reset Temporization (tRSTTEMPO)

(BOR)1.8V (min)

(PVD)(1.9V min)

PDR / POR(1.5V)

100mV hysteresis

100mV hysteresis

Option BytesReload

PVD enabled by Software

VDD / VDDA

1.8V

1.7V

1.5V

2.0V

1.9V

PVD output

BOR reset(NRST)

BOR/PDR reset(NRST)

POR/PDR(NRST)

PVD interrupt(if enabled)

Analog peripheralsCOMPx

38

COMPx Block diagram

PA1

PA5VREFINT

TIM2_ETRTIM2_CH4TIM21_ETRTIM21_CH2TIM22_ETRTIM22_CH1LPTIM_ETRLPTIM_CH2

COMP1_VALUE

+

-

+

-

COMP2 polarity selection

COMP1

COMP2

WAKEUPEXTI_LINE_21

PA4 (DAC)

PA5

VREFINT¾ VREFINT½ VREFINT¼ VREFINT

PA4 (DAC)TIM2_ETRTIM2_CH4TIM21_ETRTIM21_CH2TIM22_ETRTIM22_CH1LPTIM_ETRLPTIM_CH2

COMP2_VALUE

WAKEUPEXTI_LINE_22

PA0

PA2

PB3

PA3PB4PB5PB6PB7

39

COMP1 polarity selection

GPIOx

GPIOx

COMP2 non-inverting input selection

COMP2 inverting input selection

COMP1 inverting input selection

COMP1 window mode selection

COMP features

• Parameters at a glance• Full voltage range 2V < Vdda < 3.6V

• Propagation time vs consumption (typ. 2.7 < Vdd < 3.6V, for 200 mV step with 100 mV overdrive)

• High speed mode: 120ns / 100µA• Low power mode: 1µs / 3µA

• Input offset: +/-5mV typ, +/- 20mV max

• Programmable hysteresis: 0, 8, 15, 31 mV

• Fully asynchronous operation• Comparators are still operational even in STOP mode

• No clock related propagation delay (analog peripheral)

• Functional safety (Class B)• The comparator configuration can be locked with a write-once bit

40

Analog peripheralsADC

41

TRG0

TRG2

TRG1

ADSTART

Vref+

VDDA

VSSA

ADC_IN0

ADC_IN15

AUTDLY

ADC Block Diagram

…

TRG7

AN

ALO

G M

UX

GPIOPorts

Temp Sensor

VREFINT

.

.

.

EXTRIG bit

Trigger enable and edge selection

EXTSEL[2:0] bits

Analog Watchdog

Higher Threshold

Lower Threshold

ADRDYIE EOSMPIE EOSEQIE EOCIE OVRIE AWDIE

Flags

Interrupt enable bits

Interrupt request

.

.

.

ADRDY EOSMP OVREOCEOSEQ AWD

VLCD

.

.

.

ADSTP

Start & StopControl

S & H

AUTOFF

ADEN/ADDIS

Oversampler

42

1 2 3

Input Sel. & Scan Control

AD

DR

ES

S/D

ATA

BU

S

DMA request

1.8V ~ 3.6V

Start

h/w triggers/w trigger

Samplingtime control SAR ADC

VIN

Bias & Ref

16-bit DATA

CONVERTED DATA

Clock sources (ADC)

• The ADC has a dual clock-domain architecture:• Dedicated 16MHz clock

• PCLK clock divided by 2 or divided by 4, in case of /1 the duty cycle must be 50%

ADC PERIPHERAL

ADC Prescalers: /1 or /2 or /4

PCLK

16MHz

max16MHz internal oscillator

Digital Interface

Analog Interface

Guaranteed maximum speed whatever the MCU operating frequency.Capability to use the low-power auto-off mode.(automatic ON/OFF switch of 16 MHz internal oscillator)

43

/1, /2, /4 .. /256

Total Conversion Time

• Total conversion Time = TSampling + TConversion

Resolution TConversion TSampling Total conversion time tADC at fADC = 16MHz

12 bit 12.5 Cycles 1.5 Cycles 14 Cycles 875ns




Lower resolution allows faster conversion times for applications where high data precision is not required.

44

Auto delayed conversion • Auto Delay Mode

• When AUTDLY = 1, a new conversion can start only if the previous data has been treated, once the ADC_DR register has been read or if the EOC bit has been cleared.

3 DelayDelay2Delay1ADC State

HW/SW Trigger

EOC Flag

i Channel conversion #i

This is a way to automatically adapt the speed of the ADC to the speed of the system that reads the data.

Auto-delayed mode avoids any possible overrun issue

Note : A trigger event (for the same group of conversions) occurring during this delay is ignored.

45

Startup Time

Auto-OFF mode (Power Saving) • ADC power-on and power-off can be managed by hardware and turn

OFF the 16 MHz internal oscillator in order to save power. The ADC can be powered down:

• During the ADC is waiting for a trigger event (AUTOFF= 1) The ADC is powered up at the next trigger event.

• During the delay and waiting for a trigger event (AUTDLY= 1 and AUTOFF= 1) The ADC is powered up again at the end of the delay and at the next trigger event.

i Channel conversion #i

OFF

HW/SW Trigger

Delay2Delay1

OFF ON

OFF ON ON

OFF

OFF OFF1 Delay

ON

OFF ON

ADC Waiting for Trigger

46

AUTOFF =1 AUTDLY =0

21OFF

ON

1

Delay2Delay1 1 DelayON

21 1AUTOFF =0 AUTDLY =0

AUTOFF =1 AUTDLY =1

AUTOFF =0 AUTDLY =1

Oversampling• Principle

• The ADC hardware can do averaging according to the formula:

47

1

• M and N are programmable

• N – 2 to 256• M – division is made by logical shift up to 8 bits ( division by 256)

• Benefits• Data rate reduction• SNR improvement• Basic filtering

• EOC = 1 when new averaged value is ready

• ADC can be put to AUTOFF mode between conversions

STM32L0 implementation48

• ADC does oversampling and averaging by HW• N is setup by OVFS[2:0], 2x to 256x• M by OVSS[3:0], 0 to 8 bit

0xDEDA1Raw 20-bit accumulator

019

Programmable shift

Up to 8 bits

0xDEDA16-bit result, the MSB is truncated

015

Shift by 4 bits in this example

Analog peripheralsGlass LCD Controller (LCD)

49

LCD Controller Block diagram 50

AD

DR

ES

S/D

ATA

BU

S

Analog switch array

COM DriverSEG

Driver

Pulse Generator

Voltage Generator

Contrast Controller

Registers

Registers

LCD RAM (32x16 bits)

16-bit prescaler

Divide by 16 to 31

Analog STEP-UP converter

Frequency generator

LCDCLK

Interrupt

SEG COM MUX

COM0

COM3

SEG0

SEG27

VSS

SEG29/COM5

SEG30/COM6

SEG31/COM7

SEG28/COM4

1/3 – 1/4 VLCD

2/3 – 3/4 VLCD

1/2 VLCD

VLCD

8-to

-1 M

UX

Clock MUX

ck_div

Frequency generator• The LCD Controller (LCDCLK) uses the same

clock as RTCCLK. It can be: LSE, LSI, HSE_DIV divided by 1, 2, 4 or 8.

• The LCDCLK input clock must be in the range of 32 kHz to 1MHz.

• The LCDCLK divided by 2PS[3:0] : ck_ps

• The ck_ps to be also divided by 16 to 31 to adjust the resolution rate: ck_div

• The frame frequency is obtained from the LCD frequency by dividing it by the number of active common terminals

)16(2 DIV

fff

PSLCDCLK

LCDck_div +==

51

LCDCLK / 32768

LSE/LSI/HSE_Div1/2/4/8

PCLK1 LCD_FCR

16-bits Prescaler

Clock MUX

Divide by 16 to 31

PS[3:0]

DIV[3:0]

LCDCLK

ck_ps

ck_div

The frame frequency must be selected to be within a range of around ~30 Hz to ~100 Hz

dutyff LCDFrame *=

Memory/Segment mapping52

A

B

C

D

E

F J

M NL

IH

DP

X

SEG0

SEG1

SEG2

SEG3

COM0 COM1 COM2 COM3

X

I

A

H

F

J

B

G

E D

L M

C DP

K N

LCD RAM

COM0

COM1

COM2

COM3

Digit 16 Segment

Example of Writing the character “A” on the Liquid crystal display first digit

0x 4 D 7 0

.

.

.

COM7

G K

031 …… 123

Common/Segment driver(1/2)

• Every common signal has identical waveforms but different phases

• The common has the maximum amplitude VLCD or VSS only in the corresponding phase of a frame cycle.

• During the other phases, the signal amplitude is 1/4 VLCD or 3/4 VLCD in case of 1/4 bias or 1/3 VLCD or 2/3 VLCD in case of 1/3 Bias and 1/2 VLCD in case of 1/2 Bias.

• The first frame generated is the odd one followed by an even one

• Five Duty ratios can be selected: Static Duty, 1/2 Duty, 1/3 Duty, 1/4 Duty or 1/8 Duty

• Three modes can be selected: 1/2 Bias, 1/3 Bias or ¼ Bias

53

Common/Segment driver(2/2)54

The segment terminals are multiplexed and each of them controls four segments

A segment is active if the corresponding segment line gets a maximum voltage opposite to the common

Common signals are phase inverted in order to reduce EMI

To activate segments[n] connected to COM0, SEGn needs to be inactive (VSS) during phase 0 of an odd frame and active (VLCD) during phase 0 of an even frame when COM0 is active

To deactivate segments[n+44] connected to COM1, SEGn needs to be active during the phase 1 of an odd frame and inactive during the phase 1 of an even frame when COM1 is active

Double Buffer Memory: LCD RAM AREA ALWAYS ACCESSIBL E

Odd Frame Even Frame

VLCD

2/3 VLCD

1/3 VLCD

VSSC

OM

0

RAM refresh

VSS

CO

M1

2/3 VLCD

1/3 VLCD

VSS

2/3 VLCD

1/3 VLCD

VSS

CO

M3

2/3 VLCD

1/3 VLCD

VSS

CO

M2

SE

Gn

VLCD

VLCD

VLCD

VLCD

2/3 VLCD

1/3 VLCD

Pixels[n] Pixels[n+44] Pixels[n+88] Pixels[n+132] Pixels[n] Pixels[n+44]Pixels[n+88] Pixels[n+132]

RAM refresh

LCD RAM LCD RAM

The contrast can be adjusted using two different methods:

Method 1 (external VLCD voltage)Contrast can be controlled by programming a dead time (up to 8 phase periods) between each couple of frames where the COM and SEG value is tied to Vss in the same time.

LCD Contrast Control 55

Method 2 (internal STEP-UP converted used)The software can adjust VLCD between 2.6 V to 3.3 V in 8 steps

Odd Frame Even Frame

VLCD

2/3 VLCD

1/3 VLCD

VSSC

OM

0

phase0 phase1 phase2 phase33 phase dead time phase0 phase1 phase2 phase3

LCD Signals Generation The LCD voltage levels can be generated :

Internally using an internal step-up converter or externally using VLCD voltage

An internal resistor divider network generates all VLCD intermediate voltages

External capacitor can be used to stabilize intermediate VLCD voltage

Signal shape and thus VRMS are improved without the use of High Drive (suitable especially for large displays with higher segment c apacity)

56

remains active in STOP modes not active in STANDBY mode

The nodes provide several intermediate voltage:• One (Bias ½), • two (Bias 1/3) • three (Bias ¼)

The RL and RH resistive networks are used to increase the current during transitions and to reduce consumption in static state.

Thank you

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3 stm32l0 ulp peripherals

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