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TRANSCRIPT
The FlexRay Protocol for Automotive Applications
Marco Sacchi FAE Technical Manager January 24, 2008
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Freescale and the Freescale logo aretrademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2006.
FlexRay IntroductionFlexRay is an open, common, scalable network architecture for automotive applications. FlexRay is meant to enable next-generation, high-bandwidth control applications, including powertrain and body systems and ultimately targeting by-wire solutions for active chassis management, braking systems and steering.
Freescale and the Freescale logo aretrademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2006.
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The FlexRay ConsortiumThe FlexRay Consortium
The FlexRay Communications System
The FlexRay Products
Freescale and the Freescale logo aretrademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2006.
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Consortium Motivation Market need for an industry wide standard scalable communications system Support distributed control systems
Funct. A Funct. B ECU ECU
Funct. C Funct. A ECU
Physical Layer Distributed system. Funct. A Funct. B ECU Funct. C Funct. D ECU Physical Layer Networked system. Funct. E Funct. F ECU
Communications system with high data rate Deterministic and fault-tolerant communication system
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Consortium GoalsFlexRay definesa communication system comprising the specification of a communications protocol and a physical layer for future generation high-speed control applications in vehicles.
FlexRay is defined
in the context of an industry consortium since 2000
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Consortium StructureConsortium organized in three membership shells
Differences are in rights and obligations
Associate Members Premium Associate Core Members
Details (and applications) via the Consortium Administrator through http://www.flexray.com
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Consortium Members (per Q4 2005)
Continental Teves AG
Premium Associate Members
Delphi Corporation Denso Corporation Fiat Auto S.p.A. Ford Motor Company Honda Motor Company Hyundai-Kia Motors Motorola Nissan Motor Company PSA Peugeot Citroen Automobiles Renault Technocentre Toyota Motor Corporation Tyco Electronics Corporation
BMW Group
Core Members
Bosch DaimlerChrysler General Motors Freescale Semiconductor Philips Volkswagen AG
Freescale and the Freescale logo aretrademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2006.
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Consortium Members (per Q4 2005)
ADAC AISIN Alpine AMI Atmel austriamicrosystems Avidyne Berata Bertrandt Calsonic Kansei EADS ELMOS EPCOS ESG Esterel Eurospace Fujitsu Fujitsu TEN Haldex Hella Hitachi Cable Hitachi Hyundai Autonet IAV Infineon
IPETRONIK IROC ISUZU Motors Mitsubishi Electric Tata Elxsi Murata TDK Electronics NEC TI Nihon ThyssenKrupp NIPPON SEIKI Tokai Rika NSK Toyota Tsushu Okaya TRW OKI Pacifica Group Techn. TUEV Nord Valeo Porsche Verifica Preh Visteon Renesas Volke Consulting Eng. Scania Wuerth Elektronik eiSos SiemensVDO Xilinx SKF Industrie Yamaha SP Swedish Nat. Testing ST Microelectronics Yazaki Yokogawa Subaru Sumitomo Sunny Giken Suzuki
3SOFT ARC Seibersdorf Berner&Matter C&S Group Cadence CANway CapeWare Cardec Cbb software CRST Dearborn DECOMSYS dSpace ETAS FTZ Gigatronik Gpel electronic Hitex IMD Intrepid Control Systems IXXAT K2L Kleinknecht Automotive Lauterbach
Micron MicroSys Mirabilis Design Mission Level Design National Instruments NSI proTime SEDES Softing SystemA Tecwings Textronix Toyota Macs TTAutomotive TZM Vector Informatik Volcano Warwick Weise
Freescale and the Freescale logo aretrademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2006.
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FlexRay Protocol Specification RoadmapFlexRay Protocol SpecificationsFlexRay Consortium founded PS V0.8 PS V0.6 PS V1.0 PS V1.9 PS V0.4.3 2001 2002 2003 MFR 4100 PS V2.0 PS V2.1A PS V2.1 2004 2005 2006 MCU Products MFR 4300
2000
Freescale Semiconductor Communication Controllers Philips Semiconductors Physical Layer Bus Driver
FPGA V4 FPGA V5
MFR 4200 FPGA V9
TJA1080
Freescale and the Freescale logo aretrademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2006.
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The FlexRay Communications SystemThe FlexRay Consortium
The FlexRay Communications System
The FlexRay Products
Freescale and the Freescale logo aretrademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2006.
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FlexRay RequirementsPhysical Layer Requirements Non fault-tolerant properties Communications Protocol Requirements Requirements
Requirements
Fault-tolerant properties
Requirements Interconnection architectures, functional properties of physical layer
Requirements Communication phases, services and functions within each communication phase
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Interconnection Architectures
Optional BG Single channel
Bus
Multiple star
@ 10MBit reduced wire-harness, experience, cost tolerates one faulty channel
Dual channel mixed topologies passive medium, most experience, cost efficient allows for high data rates, increases error containment
electrical & optical physical layerTM
Freescale and the Freescale logo aretrademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2006.
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Mixed Topology Example
Active StarNode 1
Node 2
Node 3
Node 4 Node 5
Active Star
Linear Passive Bus
Node 6
Node 7
Passive Star
Freescale and the Freescale logo aretrademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2006.
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Data Exchange in a Nutshell
Communication cycle (driven by synchronized time base) Static segment TDMA based MAC (bounded latency and small latency jitter communication, deterministic communication static bandwidth requirements) Channel A Dynamic segment flexible TDMA based MAC (ad-hoc communication, varying bandwidth requirements,)
NIT
1
2
3
4
5
6
7
8
9
3a
1a
3c
4a
1c
4b
3d
6at
Channel B
1
2
3
4
5
6
7 8
9
13
3b
5d
2a
3c
1c
3e
1d
2bt
Example of a FlexRay communication cycle showing the static and the dynamic segment.
Freescale and the Freescale logo aretrademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2006.
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Integration Property1 2 3 4 5 6 7 8 9
Channel A1 2
1a3 4 5
4a6
1c
4bt7 89 13
Channel B
1b
2a
1c
1d
2bt
1
2
3
4
5
6
7
8
9
Channel A1
3a2 3 4
3c5
4a6
4b7 8 9
3dt13
Channel B
3b
2a
3c
3e
2bt
1
2
3
4
5
6
7
8
9
Channel A1
3a2
1a3 4
3c5
4a6
1c
4b7 8 9
3dt13
Channel B
3b
1b
2a
3c
1c
3e
1d
2bt
Freescale and the Freescale logo aretrademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2006.
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Frame FormatPayload preamble indicator
Sync frame indicator
Reserved bit
Startup frame indicator
Null frame indicator
Header CRC Covered Area
Frame ID
Payload length
Header CRC
Cycle count
Data 0 Data 1 Data 2 0 ... 254 Bytes Payload Segment
Data n
CRC
CRC 24 bits
CRC
11 bits 11111
7 bits
11 bits
6 bits
Header Segment
Trailer Segment
FlexRay Frame 5 + (0 ... 254) + 3 Bytes
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Synchronization
Node A Communication Network
Node B
Means for exchanging deviations
Explicit exchange versus implicit exchange Physical reference clock versus virtual reference clock Offset correction versus rate correction
Some form of reference clock An adjustment policy
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Synchronization PrincipleExchanging Deviations
Implicit exchange of clock deviations via exchange of (sync) frames1:00 2:00 3:00
Node x
Send frame A
Receive frame B
Send frame C
2:00 (expected time of arrival) 2:05 (actual time of arrival) (0:05) (measured deviation)
Virtual reference clock
Receive frame B
No single physical reference clock exists Nodes calculate deviation in respect to virtual reference clock Virtual reference clock established using distributed fault-tolerant clock synchronization algorithm (fault-tolerant midpoint)
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Synchronization Principle (cont.)Adjustment policy - Offset correction
Periodically measure phase deviation to a reference clock Adjust clock according to measured deviation Example:
Adjustment policy - rate correction
Periodically measure frequency deviation to a reference clock Adjust clock according to measured deviation Example 1: Example 2:
Freescale and the Freescale logo aretrademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2006.
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Timing Hierarchy
communication cycle level static segment arbitration grid level static slot macrotick level macrotick microtick level microtick action point minislot dynamic segment symbol network window idle time
t
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Node Architecture
HostController Host Interface
Communication ControllerMAC
POC
PHY
PHY
Clock Sync
FSP
Coding
Decoding
Freescale and the Freescale logo aretrademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2006.
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Partitioning
To actuator
From sensor
Application
Controller host interface (CHI)
Message buffer management Control / status / config data
Control interface
Config interface
Message interface
Status interface
Controller host interface services
Transparent to protocolTimer service Filtering services (e.g. Message ID filtering) Network management service
Communications protocolFrom communication channels
To communication channels
Allows extensions
Freescale and the Freescale logo aretrademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2006.
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FlexRay Application Domains
Chassis Other Powertrain
Backbone
Driver Assistance
High-speed communication
By-wire systems
Freescale and the Freescale logo aretrademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2006.
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Automotive Networking Overview
Channels Speed Time Triggered Arbitration Devices available from Freescale today
LIN Single 20 Kbit/s No Master Yes
CAN Single