3. built-in self test (bist): periodical off-line test on the field 3.1 general structure unit under...
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3. Built-In Self Test (BIST):Periodical Off-Line Test on the Field
3.1 General Structure
UnitUnder
Test
DataCompressor
DataGenerator
Comparator
Display
Reference
BIST ControllerStart/Stop Ready
Electronic System
3. Built-In Self Test (BIST):Periodical Off-Line Test on the Field
3.2 Pattern Generator
General Structure of an “n-1” Stage Linear Feedback Shift Register (LFSR).
3. Built-In Self Test (BIST):Periodical Off-Line Test on the Field
Example of a 4-Bit LFSR as a Pattern Generator.
Pseudorandom States Generated by the LFSR.
3.2 Pattern Generator
3. Built-In Self Test (BIST):Periodical Off-Line Test on the Field
r-Bit (Internal XOR) Signature Generator. The content of the LFSR is the remainder of the division operation.
3.3 Signature Generator
Serial
3. Built-In Self Test (BIST):Periodical Off-Line Test on the Field
3.3 Signature Generator
r-Bit (Internal XOR) Signature Generator. The content of the LFSR is not the remainder of the division operation.
Serial
3. Built-In Self Test (BIST):Periodical Off-Line Test on the Field
3.3 Signature Generator
Serial
Example of a 4-Bit (External) Signature Generator.
3. Built-In Self Test (BIST):Periodical Off-Line Test on the Field
3.3 Signature Generator
r-Bit (Internal XOR)
Parallel Signature Generator.
The content of the LFSR is not the remainder of the division operation.
r-Bit (External XOR)
Parallel Signature Generator.
The content of the LFSR is the remainder of the division operation.
Parallel
3. Built-In Self Test (BIST):Periodical Off-Line Test on the Field
3.3 Signature Generator
Problem: Problem: When compacting results, there is a probability of fault maskingfault masking !
Probability of failing to detect an error in the response sequence:Probability of failing to detect an error in the response sequence:
Serial input Parallel input
Where: K: length of the sequence (# of
bits)r: length of the LFRS (# of bits)
2mL- r
– 1
2mL
– 1
2k-r
– 1
2r – 1
Where: L: length of the sequence (# of test
vectors)m: length of a vector (# of bits) r: length of the LFRS (# of bits)
3. Built-In Self Test (BIST):Periodical Off-Line Test on the Field
3.4 Example: 8-bit-Length Datapath
3. Built-In Self Test (BIST):Periodical Off-Line Test on the Field
3.4 Example: 8-bit-Length Datapath
3. Built-In Self Test (BIST):Periodical Off-Line Test on the Field
3.4 Example: 8-bit-Length Datapath
3. Built-In Self Test (BIST):Periodical Off-Line Test on the Field
3.5 Built-In Logic Block Observer (BILBO)
Example of a “BILBO” structure.
3. Built-In Self Test (BIST):Periodical Off-Line Test on the Field
3.5 Built-In Logic Block Observer (BILBO)
Modular Bus-Oriented Design with “BILBO”.
3. Built-In Self Test (BIST):Periodical Off-Line Test on the Field
3.6 Transparent BIST for Memory Test
Transparent Built-In Self Test is a test
algorithm that is periodically executed
on the fieldon the field in order to verify the
integrity of large amounts of critical
data stored on mass memory systems
3. Built-In Self Test (BIST):Periodical Off-Line Test on the Field
3.6 Transparent BIST for Memory Test
Main characteristicsMain characteristics::
a)a) Minimum area overheadMinimum area overhead: this approach is one of the
best choices found in the literature in terms of area
overhead and types of faults detected in memory
structures. E.g., authors claim an area overhead of 1.2%
due to the inclusion of Transparent BIST in a 128Kbytes
X 8bytes SRAM (this value decreases as the RAM size
increases).
3. Built-In Self Test (BIST):Periodical Off-Line Test on the Field
3.6 Transparent BIST for Memory Test
Main characteristicsMain characteristics::
b)b) High capability of fault detectionHigh capability of fault detection: by indicating the
occurrence of stuck-at faults, transition faults,coupling
faults, decoder faults and read/write logic faults.
3. Built-In Self Test (BIST):Periodical Off-Line Test on the Field
3.6 Transparent BIST for Memory Test
Main characteristicsMain characteristics::
c)c) Short “down Short “down timestimes””: that are periodically required to
check the functionality of mass memory systems used
in real-time applications. The Transparent BIST
approach presents the incomparable advantage of
preserving the contents of the RAM memory after
testing. Thus, this approach is very suitable for periodic
testing since we do not need to save the memory
contents before the test session and to restore them at
the end of this session.
3. Built-In Self Test (BIST):Periodical Off-Line Test on the Field
3.6 Transparent BIST for Memory Test
Table 1. Signature Prediction Algorithm.Table 1. Signature Prediction Algorithm.
execution time
3. Built-In Self Test (BIST):Periodical Off-Line Test on the Field
3.6 Transparent BIST for Memory Test
Note that the data read during the execution of sequences S1’ through S4’ of the signature prediction algorithm (Table 2) are sometimes inverted in order to match the data read during the execution of sequences S1 through S4 of the Transparent BIST (Table 1).
Table 2. Algorithm for Transparent BIST.Table 2. Algorithm for Transparent BIST.
execution time
S1 S2 S3 S4 R1 R1 R1 R1 R1 R1 R2 R2 R2 R2 R2 R2 ... ... ... ... ... ... ... ... Rn Rn Rn Rn Rn Rn