Experiment: -3

Name: Ashok Kumar ID: 2012UEC1377

AIM: - Write the VHDL model for full adder using Behavioral Modeling.

TOOL USED: Xilinx 14.5

VHDL CODE:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity FBADD is

Port ( a,b : in bit_vector(0 to 3);

cin: in bit;

Sum : out bit_vector(0 to 3);

carry : out bit );

end FBADD;

architecture Behavioral of FBADD is

begin

process(a,b,cin)

variable t1,t2,i,c: bit;

begin

c:=cin;

for i in 0 to 3 loop

t1:= a(i) xor b(i);

t2:= t1 xor c;

sum(i)<= t2;

c:= (a(i) and b(i)) or (b(i) and c) or (a(i) and c);

end loop;

carry <= c;

end process;

end Behavioral;

RTL SCHEMATIC: -

OUTPUT WAVEFORM: -

RESULT:-

VHDL code for full adder using behavioral modeling has been implemented and

waveform and RTL schematic are obtained.

Experiment: -4

Name: Ashok Kumar ID: 2012UEC1377

AIM: - Write the VHDL model for DEMUX using structural Modeling.

TOOL USED: Xilinx 14.5

VHDL CODE:-

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity fa_str is

Port ( a,s : in bit;

y0,y1 : out bit);

end fa_str;

architecture Behavioral of fa_str is

signal t1 : bit;

component not_2

port(in_1 : in bit;

out_1 : out bit);

end component;

component and_2

port(in_1, in_2: in bit;

out_1 : out bit);

end component;

begin

x0: not_2 port map(s, t1);

a0: and_2 port map(a, t1 ,y0);

a1: and_2 port map(a, s ,y1);

end Behavioral;

entity not_2 is

Port ( in_1 : in bit;

out_1 : out bit);

end not_2;

architecture Behavioral of not_2 is

begin

process(in_1)

begin

out_1 <= not in_1 ;

end process;

end Behavioral;

entity and_2 is

Port ( in_1, in_2 : in bit;

out_1 : out bit);

end and_2;

architecture Behavioral of and_2 is

begin

process(in_1,in_2)

begin

out_1<= in_1 and in_2;

end process;

end Behavioral;

RTL SCHEMATIC: -

OUTPUT WAVEFORM: -

RESULT:-

VHDL code for DEMUX using structural modeling has been implemented and

waveform and RTL schematic are obtained.