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System peripherals & Bus Structure Memory map of the LPC2300 device is

one contiguous 32-bit address range. However, the device itself is made up of a number of buses.

Core is connected to a high-speed bus called the Advanced High Performance Bus (AHB) Reserved for high performance

peripherals such as the Vector Interrupt Controller which enables fast interrupt handling, and USB and Ethernet controllers

ARM7 Bus structure

Remaining user peripherals are connected to a second standard bus called the Advanced Peripheral Bus (APB). The APB bridge contains a clock divider, this allows the APB bus to run at a slower speed than the ARM7 core and the AHB.

This allows the user peripherals to run at a slower clock rate than the main processor to conserve power.

LPC2300 series has an additional AHB dedicated for the Ethernet and a local bus for the SRAM and FLASH

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LPC2300 Bus structure

NXP have moved the GPIO registers onto the local bus in later variants of the LPC Series- IO2PIN - APB BUS: 4.3MHz toggle -14 cycles (legacy device) FIO2PIN - local bus: 30MHz toggle - 2 cycles

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LPC23xx.h

See user manual (UM10211) for further details

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/* General Purpose Input/Output (GPIO) */#define GPIO_BASE_ADDR 0xE0028000#define IOPIN0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x00))#define IOSET0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x04))#define IODIR0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x08))#define IOCLR0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x0C))

/* Fast I/O setup */#define FIO_BASE_ADDR 0x3FFFC000#define FIO0DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x00)) #define FIO0MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x10))#define FIO0PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x14))#define FIO0SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x18))#define FIO0CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x1C))

Memory Accelerator Module (MAM)

On-chip FLASH has an access time of 50ns (20MHz). The ARM7 CPU can run up to speeds of 80MHz. Running directly from flash would limit the execution speed to 20MHz.

Possible solutions Run from RAM which has a faster access time

limited size and expensive

Implement a cache - Complex with high gate count leads to increased die area Runtime code using the cache is no longer deterministic

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Memory Accelerator Module

The MAM is a compromise between the complexity of a full cache and the simplicity of allowing the processor to directly access the FLASH memory.

FLASH memory is 128 bits wide (four instructions) rather than 32 bits wide. This means that a single FLASH access can load four ARM instructions

Attempts to have the next ARM instruction in its local memory in time for the CPU to execute.

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System Clocks

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The output from the PLL enters a series of dividers that are used to determine the USB, CPU and peripheral clocks.

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Power Control

The LPC2300 supports a variety of power control features. There are three special modes of processor power reduction: Idle mode, Sleep mode, and Power-down mode.

The CPU clock rate may also be controlled as needed by changing clock sources, re-configuring PLL values, and/or altering the CPU clock divider value. This allows a trade-off of power versus processing speed based on application requirements.

Peripheral Power Control allows shutting down the clocks to individual on-chip peripherals that are not in use.

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Idle Mode

In Idle Mode the clock to the ARM7 CPU is halted but the peripherals keep running. A reset or interrupt from a peripheral will cause the CPU clock to be enabled and processing can resume.

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Sleep Mode

In Sleep Mode all the clocks to the CPU and peripherals are halted except the real time clock.

The external oscillator is powered down and the PLL is halted.

However to allow the LPC2300 to resume processing quickly, the FLASH is kept in Standby Mode and the on-chip RC oscillator is still running. The SRAM and registers are also preserved.

The LPC2300 can exit Sleep Mode when there is an interrupt from the RTC or an interrupt from the external interrupt lines. A reset will also cause the chip to wake up. Once the LPC2300 resumes processing you must re-enable the main oscillator and PLL in order to start processing at full speed.

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Power Down

Power Down Mode has the same effect as Sleep Mode except that the FLASH memory is also placed in Power Down Mode.

When the chip restarts there is an additional 100 usec start-up time before the FLASH memory can be accessed.

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Power Control

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Power Mode Control register (PCON)

Bit 7 6 5 4 3 2 1 0

Function PM2 R R BORD BOGD BODPDM PM1 PM0

Bit Symbol Description Resetvalue0 PM0 (IDL) Power mode control bit 0. 1 PM1 (PD) Power mode control bit 1. 2 BODPDM Brown-Out Power-down mode3 BOGD Brown-Out Global Disable. 4 BORD Brown-Out Reset Disable. 6:5 - Reserved, user software should not write ones to reserved bits. 7 PM2 Power mode control bit 2.

Power Control

PM2, PM1, PM0 Description

000 Normal operation

001 Idle mode. Causes the processor clock to be stopped, while on-chip peripherals remain active. Any enabled interrupt from a peripheral or an external interrupt source will cause the processor to resume execution.

101 Sleep mode. This mode is similar to Power-down mode (the oscillator and all on-chip clocks are stopped), but the Flash memory is left in Standby mode. This allows a more rapid wakeup than Power-down mode because the Flash reference voltage regulator start-up time is not needed.

010 Power-down mode. Causes the oscillator and all on-chip clocks to be stopped. A wakeup condition from an external interrupt can cause the oscillator to re-start, the PD bit to be cleared, and the processor to resume execution.

110 Recovered & others not used

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Power control example

To put the system into Sleep mode. PM2, PM1, PM0 = 101

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PCON Register 

                                                PM2            PM1  PM0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

 0 0  0  0   0  0 0  0  0   0  0 0   0  0  0 0   0 0   0 0   0  0 0  0   1  0 0  0   0  0  0  1

 0 0  0  0  0  0  8  1 

PCON = 0x00000081

Peripheral power control

A Power Control for Peripherals feature allows individual peripherals to be turned off if they are not needed in the application, resulting in additional power savings

Some peripherals are disable by default! Power Control for Peripherals register (PCONP)

is used to select which peripherals are enabled see LPC2368 user manual (UM10211) pages 59 -60 for details

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References

LPC23xx user manual (UM10211) http://www.keil.com/dd/docs/datashts/philips/lpc23xx_um.pdf

NXP links page -http://ics.nxp.com/products/lpc2000/lpc23xx/

Insiders guide to the LPC23xx http://www.hitex.com/index.php?id=download-insiders-guides

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