ADS1251

24-Bit, 20kHz, Low-PowerANALOG-TO-DIGITAL CONVERTER

FEATURES 24 BITS—NO MISSING CODES

19 BITS EFFECTIVE RESOLUTION UP TO20kHz DATA RATE

LOW NOISE: 1.5ppm

DIFFERENTIAL INPUTS

INL: 15ppm (max)

EXTERNAL REFERENCE (0.5V to 5V)

POWER-DOWN MODE

SYNC MODE

LOW POWER: 8mW at 20kHz5mW at 10kHz

DESCRIPTIONThe ADS1251 is a precision, wide dynamic range, delta-sigma, Analog-to-Digital (A/D) converter with 24-bit resolu-tion operating from a single +5V supply. The delta-sigmaarchitecture features wide dynamic range, and 24 bits of nomissing code performance. Effective resolution of 19 bits(1.5ppm of rms noise) is achieved at conversion rates up to20kHz.

The ADS1251 is designed for high-resolution measurementapplications in cardiac diagnostics, smart transmitters, indus-trial process control, weigh scales, chromatography, andportable instrumentation. The converter includes a flexible,2-wire synchronous serial interface for low-cost isolation.

The ADS1251 is a single-channel converter and is offered inan SO-8 package. It is pin-compatible with the faster ADS1252(41.7kHz data rate).APPLICATIONS

CARDIAC DIAGNOSTICS

DIRECT THERMOCOUPLE INTERFACES

BLOOD ANALYSIS

INFRARED PYROMETERS

LIQUID/GAS CHROMATOGRAPHY

PRECISION PROCESS CONTROL

4th-Order∆Σ

Modulator

DigitalFilter

SerialInterface

Control

+VIN

CLK

VREF

SCLK

DOUT/DRDY

+VDD

GND

–VIN

ADS1251

ADS1251

SBAS184D – MARCH 2001 – REVISED JUNE 2009

PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.

Copyright © 2001-2009, Texas Instruments Incorporated

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

www.ti.com

ADS12512SBAS184Dwww.ti.com

Analog Input: Current ............................................... ±100mA, Momentary±10mA, Continuous

Voltage .................................... GND – 0.3V to VDD + 0.3VVDD to GND ............................................................................ –0.3V to 6VVREF Voltage to GND ............................................... –0.3V to VDD + 0.3VDigital Input Voltage to GND ................................... –0.3V to VDD + 0.3VDigital Output Voltage to GND ................................. –0.3V to VDD + 0.3VOperating Temperature ...................................................... –40°C to 85°CPower Dissipation .......................................................................... 500mW

ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATICDISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. TexasInstruments recommends that all integrated circuits be handledwith appropriate precautions. Failure to observe proper han-dling and installation procedures can cause damage.

ESD damage can range from subtle performance degrada-tion to complete device failure. Precision integrated circuitsmay be more susceptible to damage because very smallparametric changes could cause the device not to meet itspublished specifications.

NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”may cause permanent damage to the device. Exposure to absolute maximumconditions for extended periods may affect device reliability.

SPECIFIEDPACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT

PRODUCT PACKAGE-LEAD DESIGNATOR RANGE MARKING NUMBER MEDIA, QUANTITY

ADS1251 SO-8 D –40°C to +85°C ADS1251U ADS1251U Rails, 100

" " " " " ADS1251U/2K5 Tape and Reel, 2500

NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com.

PACKAGE/ORDERING INFORMATION(1)

ELECTRICAL CHARACTERISTICSAll specifications at TMIN to TMAX, VDD = +5V, CLK = 8MHz, and VREF = 4.096, unless otherwise specified.

ADS1251U

PARAMETER CONDITIONS MIN TYP MAX UNITS

ANALOG INPUTFull-Scale Input Voltage +VIN – (–VIN) ±VREF VAbsolute Input Voltage +VIN or –VIN to GND –0.3 VDD VDifferential Input Impedance CLK = 3.84kHz 430 MΩ

CLK = 1MHz 1.7 MΩCLK = 8MHz 210 kΩ

Input Capacitance 6 pFInput Leakage At +25°C 5 50 pA

At TMIN to TMAX 1 nA

DYNAMIC CHARACTERISTICSData Rate 20.8 kHzBandwidth –3dB, CLK = 8MHz 4.24 kHzSerial Clock (SCLK) 8 MHzSystem Clock Input (CLK) 8 MHz

ACCURACYIntegral Nonlinearity Differential Input ±0.0002 ±0.0015 % of FSRTHD 1kHz Input; 0.1dB below FS 105 dBNoise 1.5 2.5 ppm of FSR, rmsResolution 24 BitsNo Missing Codes 24 BitsCommon-Mode Rejection 60Hz, AC 90 98 dBGain Error 0.1 1 % of FSROffset Error ±30 ±100 ppm of FSRGain Sensitivity to VREF 1:1Power-Supply Rejection Ratio 70 80 dB

PERFORMANCE OVER TEMPERATUREOffset Drift 0.07 ppm/°CGain Drift 0.4 ppm/°C

PRODUCT # OF INPUTS MAXIMUM DATA RATE COMMENTS

ADS1250 1 Differential 25.0kHz Includes PGA from 1 to 8ADS1251 1 Differential 20.8kHzADS1252 1 Differential 41.7kHzADS1253 4 Differential 20.8kHzADS1254 4 Differential 20.8kHz Includes Separate Analog and Digital Supplies

PRODUCT FAMILY

ADS1251 3SBAS184D www.ti.com

ELECTRICAL CHARACTERISTICS (Cont.)All specifications at TMIN to TMAX, VDD = +5V, CLK = 8MHz, and VREF = 4.096, unless otherwise specified.

ADS1251U

PARAMETER CONDITIONS MIN TYP MAX UNITS

VOLTAGE REFERENCEVREF 0.5 4.096 VDD VLoad Current 32 µA

DIGITAL INPUT/OUTPUTLogic Family CMOSLogic Level: VIH +4.0 +VDD + 0.3 V

VIL –0.3 +0.8 VVOH IOH = –500µA +4.5 VVOL IOL = 500µA 0.4 V

Input (SCLK, CLK) Hysteresis 0.6 VData Format Offset Binary Two’s Complement

POWER-SUPPLY REQUIREMENTSOperation +4.75 +5 +5.25 VDCQuiescent Current VDD = +5VDC 1.5 2 mAOperating Power 7.5 10 mWPower-Down Current 0.4 1 µA

TEMPERATURE RANGEOperating –40 +85 °CStorage –60 +100 °C

PIN CONFIGURATION

Top View SO

PIN DESCRIPTIONS

PIN NAME PIN DESCRIPTION

1 +VIN Analog Input: Positive Input of the Differen-tial Analog Input

2 –VIN Analog Input: Negative Input of the Differ-ential Analog Input.

3 +VDD Input: Power-Supply Voltage, +5V

4 CLK Digital Input: Device System Clock. Thesystem clock is in the form of a CMOS-compatible clock. This is a Schmitt-Triggerinput.

5 DOUT/DRDY Digital Output: Serial Data Output/DataReady. This output indicates that a newoutput word is available from the ADS1251data output register. The serial data isclocked out of the serial data output shiftregister using SCLK.

6 SCLK Digital Input: Serial Clock. The serial clockis in the form of a CMOS-compatible clock.The serial clock operates independentlyfrom the system clock, therefore, it is pos-sible to run SCLK at a higher frequencythan CLK. The normal state of SCLK isLOW. Holding SCLK HIGH will either ini-tiate a modulator reset for synchronizingmultiple converters or enter power-downmode. This is a Schmitt-Trigger input.

7 GND Input: Ground

8 VREF Analog Input: Reference Voltage Input

+VIN

ADS1251U

GND–VIN

VREF

+VDD SCLK

DOUT/DRDYCLK

1

2

3

4

8

7

6

5

ADS12514SBAS184Dwww.ti.com

TYPICAL CHARACTERISTICSAt TA = +25°C, VDD = +5V, CLK = 8MHz, and VREF = 4.096, unless otherwise specified.

RMS NOISE vs DATA RATE

Data Rate (Hz)

10010 10k1k 100k

RM

S N

oise

(pp

m o

f FS

)

2.0

1.6

1.2

0.8

0.4

0

EFFECTIVE RESOLUTION vs DATA OUTPUT RATE

Data Output Rate (Hz)

1k100 10k 100k

Effe

ctiv

e R

esol

utio

n (B

its)

20.0

19.5

19.0

18.5

18.0

2.0

1.8

1.6

1.4

1.2

1.0

RMS NOISE vs TEMPERATURE

Temperature (°C)

–40 –20 0 20 40 60 80 100

RM

S N

oise

(pp

m o

f FS

)

19.5

19.0

18.5

18.0

EFFECTIVE RESOLUTION vs TEMPERATURE

Temperature (°C)

–40 –20 0 20 40 60 80 100

Effe

ctiv

e R

esol

utio

n (B

its)

18

16

14

12

10

8

6

4

2

0

VREF Voltage (V)

0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

RM

S N

oise

(µV

)

RMS NOISE vs VREF VOLTAGE14

12

10

8

6

4

2

0

VREF Voltage (V)

0 1 2 3 4 5

RM

S N

oise

(pp

m o

f FS

)

RMS NOISE vs VREF VOLTAGE

ADS1251 5SBAS184D www.ti.com

TYPICAL CHARACTERISTICS (Cont.)At TA = +25°C, VDD = +5V, CLK = 8MHz, and VREF = 4.096, unless otherwise specified.

2.0

1.5

1.0

0.5

0

Input Voltage (V)

–5 –4 –3 –2 –1 0 1 2 3 4 5

RM

S N

oise

(pp

m o

f FS

)RMS NOISE vs INPUT VOLTAGE

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

INTEGRAL NONLINEARITY vs TEMPERATURE

Temperature (°C)

–40 –20 0 20 40 60 80 100

INL

(ppm

of F

S)

5

4

3

2

1

0

INTEGRAL NONLINEARITY vs DATA OUTPUT RATE

Data Output Rate (Hz)

100 1k 10k 100k

INL

(ppm

of F

S)

40

35

30

25

20

15

10

5

0

OFFSET vs TEMPERATURE

Temperature (°C)

–40 –20 0 20 40 60 80 100

Offs

et (

ppm

of F

S)

650

625

600

575

550

525

500

GAIN ERROR vs TEMPERATURE

Temperature (°C)

–40 –20 0 20 40 60 80 100

Gai

n E

rror

(pp

m o

f FS

)

–60

–65

–70

–75

–80

–85

–90

–95

–100

POWER-SUPPLY REJECTION RATIOvs CLK FREQUENCY

Clock Frequency (MHz)

1 2 3 4 5 6 7 8

PS

RR

(dB

)

ADS12516SBAS184Dwww.ti.com

TYPICAL CHARACTERISTICS (Cont.)At TA = +25°C, VDD = +5V, CLK = 8MHz, and VREF = 4.096, unless otherwise specified.

–60

–65

–70

–75

–80

–85

–90

–95

–100

–105

COMMON-MODE REJECTION RATIOvs CLK FREQUENCY

Clock Frequency (MHz)

1 2 3 4 5 6 7 8

CM

RR

at 6

0Hz

(dB

)

–60

–65

–70

–75

–80

–85

–90

–95

–100

–105

COMMON-MODE REJECTION RATIOvs COMMON-MODE FREQUENCY

Common-Mode Signal Frequency (Hz)

10 100 1k 10k 100k

CM

RR

(dB

)1.65

1.60

1.55

1.50

1.45

1.40

CURRENT vs TEMPERATURE

Temperature (°C)

–40 –20 0 20 40 60 80 100

Cur

rent

(m

A)

9

8

7

6

5

4

3

2

1

0

POWER DISSIPATION vs CLK FREQUENCY

Clock Frequency (MHz)

0 1 2 3 4 5 76 8

Pow

er D

issi

patio

n (m

W)

35

30

25

20

15

10

5

0

VREF CURRENT vs CLK FREQUENCY

Clock Frequency (MHz)

0.1 1 10

VR

EF C

urre

nt (

µA)

0

–20

–40

–60

–80

–100

–120

–140

–160

TYPICAL FFT(1kHz input at 0.1dB less than full-scale)

Frequency (kHz)

0 1 2 3 4 5 6 7 8 9 10 11

Rel

ativ

e M

agni

tude

(dB

)

ADS1251 7SBAS184D www.ti.com

THEORY OF OPERATIONThe ADS1251 is a precision, high-dynamic range, 24-bit,delta-sigma, A/D converter capable of achieving veryhigh-resolution digital results at high data rates. The analoginput signal is sampled at a rate determined by the frequencyof the system clock (CLK). The sampled analog input ismodulated by the delta-sigma A/D modulator, which is fol-lowed by a digital filter. A Sinc5 digital low-pass filter processesthe output of the delta-sigma modulator and writes the resultinto the data-output register. The DOUT/DRDY pin is pulledLOW, indicating that new data are available to be read by theexternal microcontroller/microprocessor. As shown in the blockdiagram on the front page, the main functional blocks of theADS1251 are the 4th-order delta-sigma modulator, a digitalfilter, control logic, and a serial interface. Each of thesefunctional blocks is described in the following sections.

ANALOG INPUT

The ADS1251 contains a fully differential analog input. Inorder to provide low system noise, common-mode rejectionof 98dB, and excellent power-supply rejection, the designtopology is based on a fully differential switched-capacitorarchitecture. The bipolar input voltage range is from –4.096to +4.096V, when the reference input voltage equals +4.096V.The bipolar range is with respect to –VIN, and not with respectto GND.

The differential input impedance of the analog input changeswith the ADS1251 system clock frequency (CLK). The rela-tionship is:

Impedance (Ω) = (8MHz/CLK) • 210,000

See application note Understanding the ADS1251, ADS1253,and ADS1254 Input Circuitry (SBAA086), available for down-load from TI’s web site www.ti.com.

With regard to the analog-input signal, the overall analogperformance of the device is affected by three items. First,the input impedance can affect accuracy. If the sourceimpedance of the input signal is significant, or if there ispassive filtering prior to the ADS1251, a significant portion ofthe signal can be lost across this external impedance. Themagnitude of the effect is dependent on the desired systemperformance.

Second, the current into or out of the analog inputs must belimited. Under no conditions should the current into or out ofthe analog inputs exceed 10mA.

Third, to prevent aliasing of the input signal, the bandwidth ofthe analog-input signal must be band-limited; the bandwidthis a function of the system clock frequency. With a system

clock frequency of 8MHz, the data output rate is 20.8kHz witha –3dB frequency of 4.24kHz. The –3dB frequency scaleswith the system clock frequency.

To ensure the best linearity of the ADS1251, and to maxi-mize the elimination of even-harmonic noise errors, a fullydifferential signal is recommended.

For more information about the ADS1251 input structure,refer to application note SBAA086 found at www.ti.com.

BIPOLAR INPUT

Each of the differential inputs of the ADS1251 must staybetween –0.3V and VDD. With a reference voltage at lessthan half of VDD, one input can be tied to the referencevoltage, and the other input can range from 0V to2 • VREF. By using a three op amp circuit featuring a singleamplifier and four external resistors, the ADS1251 can beconfigured to accept bipolar inputs referenced to ground. Theconventional ±2.5V, ±5V, and ±10V input ranges can beinterfaced to the ADS1251 using the resistor values shown inFigure 1.

FIGURE 1. Level-Shift Circuit for Bipolar Input Ranges.

10kΩ

20kΩ

R1

OPA4350

OPA4350

OPA4350

+IN

–IN VREF

ADS1251

R2

BipolarInput

REF2.5V

BIPOLAR INPUT R1 R2

±10V 2.5kΩ 5kΩ±5V 5kΩ 10kΩ

±2.5V 10kΩ 20kΩ

ADS12518SBAS184Dwww.ti.com

DELTA-SIGMA MODULATOR

The ADS1251 operates from a nominal system clock fre-quency of 8MHz. The modulator frequency is fixed in relationto the system clock frequency. The system clock frequencyis divided by 6 to derive the modulator frequency (fMOD).Therefore, with a system clock frequency of 8MHz, themodulator frequency is 1.333MHz. Furthermore, theoversampling ratio of the modulator is fixed in relation to themodulator frequency. The oversampling ratio of the modula-tor is 64, and with the modulator frequency running at1.333MHz, the data rate is 20.8kHz. Using a slower systemclock frequency will result in a lower data output rate, asshown in Table I.

REFERENCE INPUT

The reference input takes an average current of 32µA with a8MHz system clock. This current will be proportional to thesystem clock. A buffered reference is recommended for theADS1251. The recommended reference circuit is shown inFigure 2.

Reference voltages higher than 4.096V will increase the full-scale range, while the absolute internal circuit noise of theconverter remains the same. This will decrease the noise interms of ppm of full-scale, which increases the effectiveresolution (see typical characteristic RMS Noise vs VREF

Voltage).

DIGITAL FILTER

The digital filter of the ADS1251, referred to as a Sinc5 filter,computes the digital result based on the most recent outputsfrom the delta-sigma modulator. At the most basic level, thedigital filter can be thought of as averaging the modulatorresults in a weighted form and presenting this average as thedigital output. The digital output rate, or data rate, scalesdirectly with the system clock frequency. This allows the dataoutput rate to be changed over a very wide range (five ordersof magnitude) by changing the system clock frequency.However, it is important to note that the –3dB point of thefilter is 0.2035 times the data output rate, so the data outputrate should allow for sufficient margin to prevent attenuationof the signal of interest.

As the conversion result is essentially an average, thedata-output rate determines the location of the resultingnotches in the digital filter (see Figure 3). Note that the firstnotch is located at the data output rate frequency, andsubsequent notches are located at integer multiples of thedata output rate; this allows for rejection of not only thefundamental frequency, but also harmonic frequencies. Inthis manner, the data output rate can be used to set specificnotch frequencies in the digital filter response.

For example, if the rejection of power-line frequencies isdesired, then the data output rate can simply be set to thepower-line frequency. For 50Hz rejection, the system clock

TABLE I. CLK Rate versus Data Output Rate.

CLK (MHz) DATA OUTPUT RATE (Hz)

8(1) 20,8337.372800(1) 19,2006.144000(1) 16,0006.000000(1) 15,6254.915200(1) 12,8003.686400(1) 96003.072000(1) 80002.457600(1) 64001.843200(1) 48000.921600 24000.460800 12000.384000 10000.192000 5000.038400 1000.023040 600.019200 500.011520 300.009600 250.007680 200.006400 16.670.005760 150.004800 12.500.003840 10

NOTE: (1) Standard Clock Oscillator.

FIGURE 2. Recommended External Voltage Reference Circuit for Best Low-Noise Operation with the ADS1251.

0.10µF

+5V

10kΩ

10µF 4

3

2

7

6

+0.10µF

0.1µF10µF+

0.1µF

OPA350

0.1µF

+5V

3

1

2

To VREFPin 8 ofthe ADS1251REF3040

ADS1251 9SBAS184D www.ti.com

frequency must be 19.200kHz, and this sets the data outputrate to 50Hz (see Table I and Figure 4). For 60Hz rejection, thesystem CLK frequency must be 23.040kHz, and this sets thedata output rate to 60Hz (see Table I and Figure 5). If both50Hz and 60Hz rejection is required, then the system CLKmust be 3.840kHz; this sets the data output rate to 10Hz andrejects both 50Hz and 60Hz (see Table I and Figure 6).

There is an additional benefit in using a lower data outputrate. It provides better rejection of signals in the frequencyband of interest. For example, with a 50Hz data output rate,a significant signal at 75Hz may alias back into the passbandat 25Hz. This is due to the fact that rejection at 75Hz mayonly be 66dB in the stopband—frequencies higher than thefirst notch frequency (see Figure 4). However, setting thedata output rate to 10Hz provides 135dB rejection at 75Hz(see Figure 6). A similar benefit is gained at frequencies nearthe data output rate (see Figures 7, 8, 9, and 10). Forexample, with a 50Hz data output rate, rejection at 55Hz mayonly be 105dB (see Figure 7). With a 10Hz data output rate,however, rejection at 55Hz will be 122dB (see Figure 8). If aslower data output rate does not meet the system require-ments, then the analog front-end can be designed to providethe needed attenuation to prevent aliasing. Additionally, thedata output rate may be increased and additional digitalfiltering may be done in the processor or controller.

Application note SBAA103, A Spreadsheet to Calculate theFrequency Response of the ADS1250-54, available for down-load from TI’s web site at www.ti.com, provides a simple toolfor calculating the ADS1250 frequency response for any CLKfrequency.

The digital filter is described by the following transfer function:

H f

ff

ff

or

H zz

z

MOD

MOD

( )

sin• •

• sin•

( )–

• –

–

–

=

= ( )

π

π

64

64

1

64 1

5

64

1

5

The digital filter requires five conversions to fully settle. Themodulator has an oversampling ratio of 64; therefore, itrequires 5 • 64, or 320 modulator results (or clocks) to fullysettle. As the modulator clock is derived from the systemCLK (modulator clock = CLK ÷ 6), the number of systemclocks required for the digital filter to fully settle is5 • 64 • 6, or 1920 CLKs. This means that any significant stepchange at the analog input requires five full conversions tosettle. However, if the step change at the analog input occursasynchronously to the DOUT/DRDY pulse, six conversionsare required to ensure full settling.

CONTROL LOGIC

The control logic is used for communications and control ofthe ADS1251.

Power-Up Sequence

Prior to power-up, all digital and analog input pins must beLOW. At the time of power-up, these signal inputs can bebiased to a voltage other than 0V; however, they shouldnever exceed +VDD.

Once the ADS1251 powers up, the DOUT/DRDY line willpulse LOW on the first conversion for which the data is validfrom the analog input signal.

DOUT/DRDY

The DOUT/DRDY output signal alternates between twomodes of operation. The first mode of operation is the DataReady mode (DRDY) to indicate that new data have beenloaded into the data output register and are ready to be read.The second mode of operation is the Data Output (DOUT)mode and is used to serially shift data out of the Data OutputRegister (DOR). See Figure 11 for the time domain partition-ing of the DRDY and DOUT function.

See Figure 12 for the basic timing of DOUT/DRDY. Duringthe time defined by t2, t3, and t4, the DOUT/DRDY pinfunctions in DRDY mode. The state of the DOUT/DRDY pin

ADS125110SBAS184Dwww.ti.com

FIGURE 3. Normalized Digital Filter Response. FIGURE 4. Digital Filter Response (50Hz).

FIGURE 5. Digital Filter Response (60Hz). FIGURE 6. Digital Filter Response (10Hz Multiples).

FIGURE 7. Expanded Digital Filter Response (50Hz with a50Hz data output rate).

FIGURE 8. Expanded Digital Filter Response (50Hz with a10Hz data output rate).

NORMALIZED DIGITAL FILTER RESPONSE0

–20

–40

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–80

–100

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–180

–2001 2 3 4 5 6 7 8 9 100

Frequency (Hz)

Gai

n (d

B)

DIGITAL FILTER RESPONSE0

–20

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–20050 100 150 200 250 3000

Frequency (Hz)

Gai

n (d

B)

DIGITAL FILTER RESPONSE0

–20

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–20050 100 150 200 250 3000

Frequency (Hz)

Gai

n (d

B)

DIGITAL FILTER RESPONSE0

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–20010 20 30 40 50 60 70 80 90 1000

Frequency (Hz)

Gai

n (d

B)

DIGITAL FILTER RESPONSE0

–20

–40

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–80

–100

–120

–140

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–180

–20046 47 48 49 50 51 52 53 54 5545

Frequency (Hz)

Gai

n (d

B)

DIGITAL FILTER RESPONSE0

–20

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–20046 47 48 49 50 51 52 53 54 5545

Frequency (Hz)

Gai

n (d

B)

ADS1251 11SBAS184D www.ti.com

is HIGH prior to the internal transfer of new data to the DOR.The result of the A/D conversion is written to the DOR fromthe Most Significant Bit (MSB) to the Least Significant Bit(LSB) in the time defined by t1 (see Figures 11 and 12). TheDOUT/DRDY line then pulses LOW for the time defined byt2, and then drives the line HIGH for the time defined by t3 toindicate that new data are available to be read. At this point,the function of the DOUT/DRDY pin changes to DOUTmode. Data are shifted out on the pin after t7. If the MSB ishigh (because of a negative result) the DOUT/DRDY signalwill stay HIGH after the end of time t3. The device communi-cating with the ADS1251 can provide SCLKs to the ADS1251after the time defined by t6. The normal mode of reading datafrom the ADS1251 is for the device reading the ADS1251 tolatch the data on the rising edge of SCLK (because data areshifted out of the ADS1251 on the falling edge of SCLK). Inorder to retrieve valid data, the entire DOR must be readbefore the DOUT/DRDY pin reverts back to DRDY mode.

If SCLKs are not provided to the ADS1251 during the DOUTmode, the MSB of the DOR is present on the DOUT/DRDYline until the beginning of the time defined by t4. If anincomplete read of the ADS1251 takes place while in DOUTmode (that is, less than 24 SCLKs were provided), the stateof the last bit read is present on the DOUT/DRDY line untilthe beginning of the time defined by t4. If more than 24SCLKs are provided during DOUT mode, the DOUT/DRDYline stays LOW until the time defined by t4.

The internal data pointer for shifting data out on DOUT/DRDYis reset on the falling edge of the time defined by t1 and t4.This ensures that the first bit of data shifted out of theADS1251 after DRDY mode is always the MSB of new data.

SYNCHRONIZING MULTIPLE CONVERTERS

The normal state of SCLK is LOW; however, by holdingSCLK HIGH, multiple ADS1251s can be synchronized. Thisis accomplished by holding SCLK HIGH for at least four, butless than 20, consecutive DOUT/DRDY cycles (see Figure13). After the ADS1251 circuitry detects that SCLK has beenheld HIGH for four consecutive DOUT/DRDY cycles, theDOUT/DRDY pin pulses LOW for one CLK cycle and then isheld HIGH, and the modulator is held in a reset state. Themodulator will be released from reset and synchronizationoccurs on the falling edge of SCLK. With multiple converters,the falling edge transition of SCLK must occur simulta-neously on all devices. It is important to note that prior tosynchronization, the DOUT/DRDY pulse of multipleADS1251s in the system could have a difference in timing upto one DRDY period. Therefore, to ensure synchronization,the SCLK must be held HIGH for at least five DRDY cycles.The first DOUT/DRDY pulse after the falling edge of SCLKoccurs at t14. The first DOUT/DRDY pulse indicates validdata.

FIGURE 9. Expanded Digital Filter Response (60Hz with a60Hz data output rate).

FIGURE 10. Expanded Digital Filter Response (60Hz with a10Hz data output rate).

DIGITAL FILTER RESPONSE0

–20

–40

–60

–80

–100

–120

–140

–160

–180

–20056 57 58 59 60 61 62 63 64 6555

Frequency (Hz)

Gai

n (d

B)

DIGITAL FILTER RESPONSE0

–20

–40

–60

–80

–100

–120

–140

–160

–180

–20056 57 58 59 60 61 62 63 64 6555

Frequency (Hz)

Gai

n (d

B)

ADS125112SBAS184Dwww.ti.com

POWER-DOWN MODE

The normal state of SCLK is LOW; however, by holdingSCLK HIGH, the ADS1251 will enter power-down mode. Thisis accomplished by holding SCLK HIGH for at least 20consecutive DOUT/DRDY periods (see Figure 14). After theADS1251 circuitry detects that SCLK has been held HIGH forfour consecutive DOUT/DRDY cycles, the DOUT/DRDY pinpulses LOW for one CLK cycle and then is held HIGH, andthe modulator is held in a reset state. If SCLK is held HIGHfor an additional 16 DOUT/DRDY periods, the ADS1251enters power-down mode. The part will be released frompower-down mode on the falling edge of SCLK. It is impor-tant to note that the DOUT/DRDY pin is held HIGH after fourDOUT/DRDY cycles, but power-down mode is not enteredfor an additional 16 DOUT/DRDY periods. The firstDOUT/DRDY pulse after the falling edge of SCLK occurs att16 and indicates valid data. Subsequent DOUT/DRDY pulseswill occur normally.

SERIAL INTERFACE

The ADS1251 includes a simple serial interface which can beconnected to microcontrollers and digital signal processors ina variety of ways. Communications with the ADS1251 cancommence on the first detection of the DOUT/DRDY pulseafter power up.

It is important to note that the data from the ADS1251 is a24-bit result transmitted MSB-first in Offset Binary TwosComplement format, as shown in Table III.

The data must be clocked out before the ADS1251 entersDRDY mode to ensure reception of valid data, as describedin the DOUT/DRDY section of this data sheet.

TABLE III. ADS1251 Data Format (Offset Binary TwosComplement).

DIFFERENTIAL VOLTAGE INPUT DIGITAL OUTPUT (HEX)

+Full-Scale 7FFFFFH

Zero 000000H

–Full-Scale 800000H

SYMBOL DESCRIPTION MIN TYP MAX UNITS

tDRDY Conversion Cycle 384 • CLK nsDRDY Mode DRDY Mode 36 • CLK nsDOUT Mode DOUT Mode 348 • CLK ns

t1 DOR Write Time 6 • CLK nst2 DOUT/DRDY LOW Time 6 • CLK nst3 DOUT/DRDY HIGH Time (Prior to Data Out) 6 • CLK nst4 DOUT/DRDY HIGH Time (Prior to Data Ready) 24 • CLK nst5 Rising Edge of CLK to Falling Edge of DOUT/DRDY 30 nst6 End of DRDY Mode to Rising Edge of First SCLK 30 nst7 End of DRDY Mode to Data Valid (Propagation Delay) 30 nst8 Falling Edge of SCLK to Data Valid (Hold Time) 5 nst9 Falling Edge of SCLK to Next Data Out Valid (Propagation Delay) 30 nst10 SCLK Setup Time for Synchronization or Power Down 30 nst11 DOUT/DRDY Pulse for Synchronization or Power Down 3 • CLK nst12 Rising Edge of SCLK Until Start of Synchronization 1537 • CLK 7679 • CLK nst13 Synchronization Time 0.5 • CLK 6143.5 • CLK nst14 Falling Edge of CLK (After SCLK Goes LOW) Until Start of DRDY Mode 2042.5 • CLK nst15 Rising Edge of SCLK Until Start of Power Down 7681 • CLK nst16 Falling Edge of CLK (After SCLK Goes LOW) Until Start of DRDY Mode 2318.5 • CLK nst17 Falling Edge of Last DOUT/DRDY to Start of Power Down 6144.5 • CLK ns

TABLE II. Digital Timing.

FIGURE 11. DOUT/DRDY Partitioning.

DATA

DRDY Mode DOUT ModeDOUT Mode

DATA DATA

t4t2 t3

t1

DRDY Mode

DOUT/DRDY

ADS1251 13SBAS184D www.ti.com

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ADS125114SBAS184Dwww.ti.com

ISOLATION

The serial interface of the ADS1251 provides for simpleisolation methods. The CLK signal can be local to theADS1251, which then only requires two signals (SCLK andDOUT/DRDY) to be used for isolated data acquisition.

LAYOUTPOWER SUPPLY

The power supply must be well-regulated and low-noise. Fordesigns requiring very high resolution from the ADS1251,power-supply rejection will be a concern. Avoid runningdigital lines under the device as they may couple noise ontothe die. High-frequency noise can capacitively couple intothe analog portion of the device and will alias back into thepassband of the digital filter, affecting the conversion result.This clock noise will cause an offset error.

GROUNDING

The analog and digital sections of the system design shouldbe carefully and cleanly partitioned. Each section shouldhave its own ground plane with no overlap between them.GND should be connected to the analog ground plane, aswell as all other analog grounds. Do not join the analog anddigital ground planes on the board, but instead connect thetwo with a moderate signal trace. For multiple converters,connect the two ground planes at one location as central toall of the converters as possible. In some cases, experimen-tation may be required to find the best point to connect thetwo planes together. The printed circuit board can be de-signed to provide different analog/digital ground connectionsvia short jumpers. The initial prototype can be used toestablish which connection works best.

DECOUPLING

Good decoupling practices should be used for the ADS1251and for all components in the design. All decoupling capaci-tors, and specifically the 0.1µF ceramic capacitors, should beplaced as close as possible to the pin being decoupled. A1µF to 10µF capacitor, in parallel with a 0.1µF ceramiccapacitor, should be used to decouple VDD to GND.

SYSTEM CONSIDERATIONSThe recommendations for power supplies and grounding willchange depending on the requirements and specific designof the overall system. Achieving 24 bits of noise performanceis a great deal more difficult than achieving 12 bits of noiseperformance. In general, a system can be broken up into fourdifferent stages:

• Analog Processing

• Analog Portion of the ADS1251

• Digital Portion of the ADS1251

• Digital Processing

For the simplest system consisting of minimal analog signalprocessing (basic filtering and gain), a microcontroller, andone clock source, one can achieve high resolution by power-ing all components from a common power supply. In addi-tion, all components could share a common ground plane.Thus, there would be no distinctions between analog powerand ground, and digital power and ground. The layoutshould still include a power plane, a ground plane, andcareful decoupling. In a more extreme case, the design couldinclude:

• Multiple ADS1251s

• Extensive Analog Signal Processing

• One or More Microcontrollers, Digital Signal Processors,or Microprocessors

• Many Different Clock Sources

• Interconnections to Various Other Systems

High resolution will be very difficult to achieve for this design.The approach would be to break the system into as manydifferent parts as possible. For example, each ADS1251 mayhave its own analog processing front end.

DEFINITION OF TERMS

An attempt has been made to use consistent terminology inthis data sheet. In that regard, the definition of each term isprovided here:

Analog-Input Differential Voltage—for an analog signalthat is fully differential, the voltage range can be compared tothat of an instrumentation amplifier. For example, if bothanalog inputs of the ADS1251 are at 2.048V, the differentialvoltage is 0V. If one analog input is at 0V and the other

ADS1251 15SBAS184D www.ti.com

analog input is at 4.096V, then the differential voltage mag-nitude is 4.096V. This is the case regardless of which inputis at 0V and which is at 4.096V. The digital-output result,however, is quite different. The analog-input differential volt-age is given by the following equation:

+VIN – (–VIN)

A positive digital output is produced whenever the analog-input differential voltage is positive, whereas a negativedigital output is produced whenever the differential is nega-tive. For example, a positive full-scale output is producedwhen the converter is configured with a 4.096V reference,and the analog-input differential is 4.096V. The negative full-scale output is produced when the differential voltage is–4.096V. In each case, the actual input voltages must remainwithin the –0.3V to +VDD range.

Actual Analog-Input Voltage—the voltage at any one ana-log input relative to GND.

Full-Scale Range (FSR)—as with most A/D converters, thefull-scale range of the ADS1251 is defined as the input whichproduces the positive full-scale digital output minus the inputwhich produces the negative full-scale digital output. Forexample, when the converter is configured with a 4.096Vreference, the differential full-scale range is:

[4.096V (positive full-scale) – (–4.096V) (negative full-scale)] = 8.192V

Least Significant Bit (LSB) Weight—this is the theoreticalamount of voltage that the differential voltage at the analoginput would have to change in order to observe a change inthe output data of one least significant bit. It is computed asfollows:

LSBWeightFull ScaleRange V

NREF

N= − =2 1

2

2 1–

•

–

where N is the number of bits in the digital output.

Conversion Cycle—as used here, a conversion cycle refersto the time period between DOUT/DRDY pulses.

Effective Resolution (ER)—of the ADS1251, in a particularconfiguration, can be expressed in two different units:bits rms (referenced to output) and µVrms (referenced toinput). Computed directly from the converter’s output data,each is a statistical calculation based on a given number ofresults. Noise occurs randomly; the rms value represents astatistical measure, which is one standard deviation. The ERin bits can be computed as follows:

ER in bits rms =

20 log2• •

VVrms noise

REF

6 02.

The 2 • VREF figure in each calculation represents the full-scale range of the ADS1251. This means that both units areabsolute expressions of resolution—the performance in dif-ferent configurations can be directly compared, regardless ofthe units.

fMOD—frequency of the modulator and the frequency theinput is sampled.

fCLK Frequency

MOD =6

fDATA—Data output rate.

ff CLK Frequency

DATAMOD= =64 384

Noise Reduction—for random noise, the ER can be im-proved with averaging. The result is the reduction in noise bythe factor √N, where N is the number of averages, as shownin Table IV. This can be used to achieve true 24-bit perfor-mance at a lower data rate. To achieve 24 bits of resolution,more than 24 bits must be accumulated. A 36-bit accumulatoris required to achieve an ER of 24 bits. The following usesVREF = 4.096V, with the ADS1251 outputting data at 20kHz, a4096 point average will take 204.8ms. The benefits of averag-ing will be degraded if the input signal drifts during that 200ms.

N NOISE ER ER(Number REDUCTION IN IN

of Averages) FACTOR µVrms BITS rms

1 1 16µV 19.262 1.414 11.3µV 19.754 2 8µV 20.268 2.82 5.66µV 20.7616 4 4µV 21.2632 5.66 2.83µV 21.7664 8 2µV 22.26128 11.3 1.41µV 22.76256 16 1µV 23.26512 22.6 0.71µV 23.761024 32 0.5µV 24.262048 45.25 0.35µV 24.764096 64 0.25µV 25.26

TABLE IV. Averaging for Noise Reduction.

ADS125116SBAS184Dwww.ti.com

DATE REVISION PAGE SECTION DESCRIPTION

6/09 D 2 Product Family Table Changed ADS1251 maximum data rate from 26.8kHz to 20.8kHz.

9/07 C 12 Table II Changed t11 from 1 • CLK to 3 • CLK.

.

Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

PACKAGE OPTION ADDENDUM

www.ti.com 8-Nov-2014

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead/Ball Finish(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

ADS1251U ACTIVE SOIC D 8 75 Green (RoHS& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS1251U

ADS1251U/2K5 ACTIVE SOIC D 8 2500 Green (RoHS& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR ADS1251U

ADS1251U/2K5G4 ACTIVE SOIC D 8 2500 Green (RoHS& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR ADS1251U

ADS1251UG4 ACTIVE SOIC D 8 75 Green (RoHS& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS1251U

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availabilityinformation and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finishvalue exceeds the maximum column width.

PACKAGE OPTION ADDENDUM

www.ti.com 8-Nov-2014

Addendum-Page 2

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

ADS1251U/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 24-Jul-2013

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

ADS1251U/2K5 SOIC D 8 2500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 24-Jul-2013

Pack Materials-Page 2

IMPORTANT NOTICE

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