2128 ieee transactions on circuits and systems—i: …

2128 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 54, NO. 10, OCTOBER 2007

A 8-GHz SiGe HBT VCO Design on a Low ResistiveSilicon Substrate Using GSML

Jongsoo Lee, Young-Gi Kim, Member, IEEE, Eun-Jin Lee, Chang-Woo Kim, Member, IEEE, andPatrick Roblin, Member, IEEE

Abstract—A practical layout method called ground shield mi-crostrip lines (GSML) is investigated for the reliable design of highfrequency interconnection lines on a low resistive silicon substrate.GSML facilitates the prediction of parasitic networks at the ex-pense of introducing negligible loss. The microwave performanceof a GSML line structure is compared to that of a conventionalmetal line on the same standard silicon substrate (20 cm). Then,the GSML structure is applied to an 8-GHz SiGe heterojunctionbipolar transistor (HBT) voltage-controlled oscillator (VCO) cir-cuit. The GSML method replaces the post layout simulation andreduces iteration time, increasing design efficiency. A fully inte-grated differential tuning SiGe HBT 8-GHz VCO is designed andtested. The measured phase noise for the VCO is 106 2 dBc/Hzat 1-MHz offset with an output power of 6 7 dBm.

Index Terms—Ground shield microstrip line (GSML), hetero-junction bipolar transistor (HBT), microstrip line, radio frequencyintegrated circuit (RFIC), voltage-controlled oscillator (VCO).

I. INTRODUCTION

THE RF and analog integrated circuit market for wirelessbroadband applications has been rapidly expanding during

the last few years. To be successful in the wireless market, chipsolutions need to be small, low cost and feature low powerconsumption. Well developed, low-cost, reliable and timeproven silicon processes have become attractive and can noweffectively compete with other expensive processes such asGaAs processes. With the advances in state-of-the-art siliconprocesses, silicon-based circuits have now reached applicationsin which III–V devices had previously prevailed. Silicon-basedcircuits have now become a strong candidate that can meetthe requirements for successful chip set solutions for newdeveloping high-frequency broadband applications.

Recently new emerging wireless broadband applications suchas ultra-wide-band (UWB) [1] and WiMAX [2] have been in-troduced. These new developing wireless broadband applica-tions operate at very high frequencies. As operating frequencies

Manuscript received November 13, 2006; revised February 15, 2007. Thiswork was supported in part by the Basic Research Program of the Korea Science& Engineering Foundation under Grant R01-2003-000-10455-0 and in part bya Texas Instruments Fellowship. This paper was recommended by AssociateEditor A. Apsel.

J. Lee and P. Roblin are with the Electrical and Computer Engineering, TheOhio State University, Columbus, OH 43210 USA (e-mail: [email protected]).

Y,-G, Kim is with the Department of Data Communications, Anyang Univer-sity, Anyang-Si 430-714, Korea (e-mail: [email protected]).

E.-Jin Lee was with the Department of Data Communications, Anyang Uni-versity, Anyang-Si 430-714, Korea. He is now with the College of Electrical En-gineering and Computer Science, Kook Min University, Seoul 136-702, Korea.

C.-W. Kim is with the College of Electric and Information Engineering,Kyung Hee University, Yongin-Si 449-701, Korea (e-mail: [email protected]).

Digital Object Identifier 10.1109/TCSI.2007.904595

are pushed up, the low resistivity silicon substrate becomes amajor obstacle for silicon-based radio frequency integrated cir-cuits (RFICs). The low-resistivity of silicon substrate leads tolarge signal losses in the substrate and cross talk through thesubstrate.

Obviously, high resistive substrates are preferable for highfrequency applications. However due to its complicated fabrica-tion processes, high-resistive silicon wafers are quite expensivefor standard commercial chip applications, and are not attractiveas a chip solution material.

Typical transmission-line loss on standard Si substrate (i.e.,15 to 20 cm) is much higher than that on GaAs substrate,which is a huge obstacle for many microwave applications. Dueto the complicated parasitic networks caused by low resistivityof silicon substrate, precise prediction of the high frequencytransmission characteristics for conventional interconnectionlines based on standard silicon substrate is hardly possible inthe design of RFIC at high frequencies [3].

To overcome the drawback of the low resistive silicon sub-strate and take advantage of cheap silicon wafer prices and well-developed silicon process technology, much research has beencarried out and new novel methodologies have been suggested.These novel methodologies are based on two basic principles.One approach is to imitate a high resistivity substrate, and theother is to provide an ideal ground plane [4].

This work proposes a practical layout method called groundshield microstrip lines (GSML) which allow for the precise pre-diction of parasitic networks of high frequency interconnectionlines on the low resistive silicon substrate at the expense of in-troducing trivial loss. GSML can be directly used in the designprocedure of RFICs in standard CMOS or bipolar processes. Wewill first investigate the microwave performance of a GSML linestructure and compare it to a conventional metal line counter-part on the same standard silicon substrate (20 cm). Then,the use of the GSML technique will be demonstrated in the de-sign of an 8-GHz SiGe heterojunction bipolar transistor (HBT)voltage-controlled oscillator (VCO) circuit.

The outline of this paper is as follows. In Section II, previousworks are reviewed. Section III is dedicated to the GSML struc-ture. The design of an 8-GHz SiGe HBT VCO is presented inSection IV. Measurement results of the 8-GHz SiGe HBT VCOare reported in Section V. Finally, a summary of achievement isgiven in Section VI.

II. SPECIAL RF TECHNOLOGY REVIEW

There are several different mechanisms which cause energylosses at high operating frequencies. One is related to the metalloss, i.e., metal series resistance, and the others are associated

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LEE et al.: A 8-GHZ SIGE HBT VCO DESIGN ON A LOW RESISTIVE SILICON SUBSTRATE USING GSML 2129

with the substrate loss via capacitive coupling and magneticcoupling to the substrate [5]. Metal loss comes from the skin ef-fect and other magnetic effects at high frequencies, which leadsto nonuniform current distribution in the metal lines and an in-crease in the effective resistance. Capacitances between metallines and substrate provide paths where signals in metal linespass through the substrate, causing signal losses and cross talksbetween nearby building blocks. In the case of heavily dopedsubstrate, the magnetic field induced by the current flowing inthe metal lines results in eddy currents in the substrate, andimage currents in the substrate which flow in opposite directionto the original currents, leading to energy loss.

To overcome the drawback of the low resistive siliconsubstrate, a number of special RF technologies have been sug-gested. Yue described in his paper [4] a pattern ground shield inwhich the resistivity of the silicon substrate goes to either zeroor infinity. This observation will provide an important clue toresolution of the above issues.

Etching of the silicon substrate [6] or high resistivity sub-strate [7] have been used such that the resistivity of the sub-strate approaches infinity. The substrate crosstalk suppressioncapability of silicon-on-insulator substrate with buried thick un-doped tungsten silicide ground planes has been reported [8].Those methods have however the drawback that they are notcompatible with standard CMOS processes.

Since the introduction of a patterned ground shield (PGS) [4]by Yue, this method has been used extensively in RF circuit de-signs. Patterned ground shield is made of plates that must bebroken regularly in the direction perpendicular to the currentdirection in metal lines so as to prevent an image current fromoccurring on the ground shield, reducing energy losses in metallines and, in addition, reducing coupling noise from substrate tometal lines. Its advantage is that it can be implemented in stan-dard silicon process. This method was successfully applied toon-chip interconnection lines to reduce the loss up to 7 GHz [9].The disadvantage of PGS method is that the number of plateswhich are used for a patterned ground shield is very large. Ac-cordingly, the extraction of the parasitics associated with thislayout process is greatly complicated by the large number ofplates used.

The complexity of integrated circuits for high frequencybroadband applications is increasing rapidly. The number ofinterconnections between building blocks is increasing and thelevel of interaction is becoming much more complicated. Tobe successful in RFIC design, it is very important to take all ofparasitic effects into account to verify whether designed circuitswork appropriately. The parasitic effects become much morecritical and serious as operating frequencies are pushed up.RFIC designers normally rely on the post layout simulation tocheck if parasitic networks have an impact on the performanceof designed circuits and verify if the designed circuits meet allrequirements described in the application specifications. In gen-eral, the design time spent on extraction of layout and post layoutsimulation depends on the number of circuit blocks and asso-ciated wiring, and the fact that parasitic networks dramaticallyincrease with the number of building block considered. Highlycomplex layout structures such as patterned ground shields underon-chip inductors and interconnection lines, and guard rings

Fig. 1. Actual signal line structures. (a) Proposed GSML. (b) Bare line.

around on-chip inductors lead to an unacceptable number ofparasitic networks, causing a huge waste of time and resources.In spite of their advantages, these RF special techniques make itvery difficult or sometimes impossible to do reliable post layoutsimulation in such complicated circuits. In this paper, we proposea very practical methodology to remove the issue of post layoutsimulation in circuits with complicated layout structures.

III. GSML METHOD

We propose the use of GSML based on the thin film mi-crostrip (TFMS) lines [10] for high precise and reliable predic-tion of parasitic effects of interconnection lines at high frequen-cies on low resistive silicon wafers. GSML can be used for thedesign and fabrication of RFICs in standard CMOS or bipolarprocesses.

The main advantage of GSML is that the parasitic effectscoming from interconnection lines can be considered in thestage of schematic simulation. This method can replace thepost layout simulation process to some degree, reducing circuitdesign time and increasing efficiency in RF circuit designs byreducing iterations between schematic and layout simulations.

Fig. 1 shows the proposed GSML transmission line structure.The GSML line structure consists of signal transmission linesand a ground shield metal plane. A top thick metal layer is usedfor the signal transmission lines and metal 1 layer is used for theshield metal plane. To provide a ground plane and separate thetop metal line from the lossy silicon substrate, metal 1 layer isgrounded. In addition, separation between signal line and lossysubstrate mitigates the effect of the low resistive silicon sub-strate.


Fig. 2. Equivalent circuit for a lossy transmission line.

Microstrip loss and prediction of the loss in general are topicsof continued interest [11]. The advantage of GSML is that theentire chip area except the active devices and pads provides aground plane to the signal line. The ground shield plain blocksthe signal path through the low resistive substrate and simplifiesthe modeling of the parasitic networks relative to the ground byproviding a solid ground plane.

By using a GSML structure, prediction of high frequency par-asitic loss and cross talk problems in low resistive silicon sub-strate can be improved. The high predictability of parasitic lossin the GSML structure arises from the more accurate micro-stripline methods which can be directly applied to the RFIC de-sign. If these effects are well predicted, the circuit design andlayout can be optimized to minimize parasitic loss. Microstripline modeling allows us to more precisely predict the perfor-mance of high frequency RF building blocks.

To route interconnects in the design, a few additional metallayers other than the top metal layer were used. However, thenumber of these additional layers was kept to a minimum andtheir length was kept very short, such that their associated par-asitic effects are insignificant.

A. Lossy Transmission Lines

In physical transmission lines, the propagation of the voltageand current waves is attenuated. The attenuation constant is ajoint function of the microstrip geometry, the electrical prop-erties of the dielectric substrate and the conductors, and of fre-quency. The losses can be expressed as loss per unit length alongthe microstrip line using an attenuation factor. There are twotypes of losses in a microstrip line: the dielectric loss and theohmic skin loss in the conductors [12].

Fig. 2 shows a basic equivalent circuit for a lossy transmissionline. R and G represent a series resistance and shunt conductanceof transmission line per unit length. The conductor loss is rep-resented by the series resistance R, while the dielectric loss isrepresented by the shunt conductance G. The propagation con-stant and characteristic impedance of a lossy transmission lineis given as

(1)

(2)

which are complex, indicating power loss during propagationand a phase shift between voltage and current waves.

For large loss in the dielectric, the propagation of modes suchas the slow-wave mode or skin-effect mode can take place. Con-sider two examples in Fig. 3. Depending on the conductivity of

Fig. 3. Two examples of a microstrip over a lossy silicon substrate.

Fig. 4. Comparison of the propagation constant � versus frequency for a TEMmodel neglecting the dielectric loss and a Momentum simulation and the Tuncermodel.

the silicon layer and the wave frequency, the silicon layer canbehave like a shunt resistance, a capacitance or a ground plane.

When the loss in the dielectric region is important, an exactsolution must be obtained for the propagation constant andattenuation factor . Starting from (1) and using the followingdefinitions:

(3)

(4)

(5)

(6)

(7)

One can verify that is given by

(8)

A plot of versus frequency is given by Fig. 4.The dispersion obtained for (A Momentum simulation

and the Tuncer model [13]) clearly departs from the conven-tional linear loss-less TEM case. Assuming a TEM mode, thephase and group velocity are obtained from the propagationconstant .

and (9)


Fig. 5. Various modes of propagation for a 20-�m line on a lossy substrate.

Fig. 6. Skin effect of transmission line.

The larger slope observed at low frequency in Fig. 4 is indeedassociated with low phase and group velocities. This orig-inates from the penetration of the magnetic field in the lossy sil-icon layer whereas an electric field remains mostly confined inthe SiO layer. As a result, both C and L are large, and the phasevelocity becomes very large. For high enough frequencies, apropagation mode switches to either a dielectric quasi-TEMmode at high silicon resistivity or a skin effect mode at lowsilicon resistivity when the skin depth becomes comparable orsmaller than the silicon layer thickness. The different modes areindicated in Fig. 5 for a 20- m width line. Clearly, accuratelymodeling lines in lossy substrate is difficult.

B. Loss in Transmission Line

1) Conductor Loss: Conductor loss at high frequencies in-creases with the square root of the frequency and is dominatedby skin effect as illustrated in Fig. 6. Due to the skin effect, RFcurrents are forced to flow near the surface of the conductor. Theskin depth of a conductor is defined as the distance in the con-ductor for which the current density drops by 37% of its valueat the surface [14] and is given by

(10)

Fig. 7. Skin depth versus frequency in an aluminium metal line.

where is the skin depth (m), the conductor magnetic perme-ability ( : free space), the bulk conduc-tivity (S/m), and the frequency (Hz).

As frequency increases, the skin depth becomes thinner andthinner, and the effective resistance of the metal line increases.Fig. 7 shows the variation of the skin depth versus frequency.It is evident that a 2.5- m thick metal layer is efficient up to5 GHz, which is the normal thickness for top metal layers inrecent processes. Above 5 GHz, the skin effect in a 2.5- mmetal layer becomes serious. To accurately model interconnec-tion losses between devices as well as I/O pads, skin effect has tobe taken into account in the design stage, especially, at frequen-cies above 5 GHz. The GSML method provides a good method-ology for making it possible by utilizing the microstrip modelsused in MMIC design.

2) Dielectric Loss: Another source of loss in transmissionline is dielectric loss. In this work, a ground plane is placed be-tween thick metal signal lines and a lossy silicon substrate. Dueto the thin dielectric layer placed between the metal layer andthe ground shield, transmission lines show relatively high inser-tion losses. Fortunately, compared to conductor losses, dielec-tric losses are relatively small, and not a major source of loss.

To verify the performance of the GSML, several 10- m widthsignal lines are designed and fabricated as shown in Fig. 8.Signal lines with and without a ground shield are implemented.In the test structure, open and short patterns are also included toassist with the de-embedding process.

The loss characteristics of the signal lines are predicted usingthe ADS Momentum simulator and compared with measuredvalues. The results given in Fig. 9 show that the GSML improvesthe return loss characteristics. This comes from the fact that theinserted ground shield plane provides a sound ground point. In-sertion losses in Fig. 10 show that the insertion loss of the GSMLis larger than that of a conventional line up to 4.5 GHz, while theinsertion loss of a GSML is smaller than that of a conventionalline above 4.5 GHz. In practice the return loss has an impact onthe insertion loss of signal lines. This fact makes insertion losscomparisons relevant only to 50- source and loads.


Fig. 8. Photo of GSML test structure.

Fig. 9. Return loss characteristics of 10 �m width signal lines in Fig. 8.

Fig. 10. Insertion loss characteristics of 10 �m width signal lines in Fig. 8.

The ultimate figure-of-merit for comparing GSML to a con-ventional line under optimal matching condition is provided bythe maximum available gain, given in

with

(11)

Fig. 11. Gmax characteristics of 10 �m width signal lines in Fig. 8.

The result is shown in Fig. 11. It shows that the signal losswith GSML increases slightly faster than in the unshielded line.This increase is due to the thinner dielectric. However, the signalloss remains quite small for the ideal matching condition re-quired by and is an acceptable tradeoff.

Patterned ground shields are preferred over solid groundshield under the inductor because they suppress the eddy orimage current induced by magnetic coupling. In the case of amicrostrip line the image current is welcomed as it providesa well defined return path for the current. At the same timethe inductive series impedance added by the microstrip is keptsmall due to the strong capacitive coupling induced by the verythin dielectric. The loss associated with the eddy current effectalong the microstrip is then the skin effect loss in the groundplane which for the GSML considered is kept quite small asindicated by in Fig. 11.

Indeed the GSML structure provides advantages such aslower R , suppression of cross talk, reliable prediction of allparasitics at the expense of trivial potential losses coming fromthe thinner dielectric. Further the optimization of the line widthcan be done at the circuit level using microstrip design method.

IV. CIRCUIT DESIGN

The SiGe HBTs used in the design feature a typical cutofffrequency of 45 GHz and a typical maximum oscillation fre-quency of of 60 GHz. The designed circuit is fabricatedusing a 0.35- m SiGe process.

The VCO core is made up of a cross-coupled differential pairwith a parallel resonator connected between the collector nodes.In most of the frequency tuning circuits in the differential VCOsreported by other research groups, the oscillation frequency de-creases as the tuning voltage goes up, or negative tuning volt-ages are used [15]–[17]. Similarly, the differential VCO pre-sented in this paper has the frequency tuning circuit such thatthe oscillation frequency decreases as the tuning voltage goesup.

The P-ports of the varactor diodes are biased by the tuningvoltage via choke resistors. Inductors have a low dc voltagedrop, reduce noise and improve linearity. However, they occupya large chip area. Therefore, resistors are used for the choke toreduce the chip area due to the comparatively large size of thespiral inductor in the MMIC chip. However, the choke resistorscontribute to increase phase noise and decrease the tuning range


Fig. 12. Simplified schematic of differential VCO with buffer amplifier circuit.

Fig. 13. Layout of differential VCO with buffer amplifier circuit. The built-ininductors used in the VCO circuit have a patterned ground shield.

of the oscillation frequency. The coupled differential oscillatorcircuit is connected to a buffer amplifier circuit which adapts anemitter follower buffer circuit topology as shown in Fig. 12.

Traditionally, error-free layouts pass through post layout sim-ulation process to verify whether the performances of the designfulfill its requirements. If the requirements are not satisfied, op-timization of the circuit is required. This process is repeatedover and over until all requirements are satisfied. In the postlayout process, the extraction of parasitic components is a time-consuming process. This problem is aggravated when using ad-vanced state-of-art layout techniques which require more com-plicated layouts.

In the new proposed method, the optimization process ispossible at the schematic design stage because compared todevices and passive components, the interconnection lines arelarge enough not to be affected by the change of parameters ofdevices and passive components. The increase of the numberof components introduced by the GSML structure is trivialcompared to the number of parasitic components introduced bythe extraction process. Therefore, simulation at the schematicstage greatly benefits from the GSML methodology.

The layout of the differential VCO is shown in Fig. 13. Asmentioned in Section III, the GSML method is applied to thelayout. To be successful in the design of RFIC circuits, para-sitic effects coming from interconnection lines have to be takeninto account. In this work, the microstrip line method is appliedusing the GSML methodology. Fig. 14 shows the schematicof the differential VCO and buffer amplifier using microstrip

Fig. 14. Schematic of differential VCO with buffer amplifier circuit with trans-mission lines.

Fig. 15. Simulation result of a differential VCO with a buffer amplifier circuitwith transmission lines.

lines. All interconnection lines shown in Fig. 13 have been con-verted to microstrip lines in Fig. 14. Using this reliable infor-mation on interconnection lines, the VCO circuit is optimizedat the schematic design level, removing the need for multiplepost layout simulation iterations.

To investigate the effect of GSML in the VCO performances,two VCOs were simulated; one with GSML, and the otherwithout GSML. Fig. 15 shows the simulation results of theGSML VCO. The simulated output power of the VCO andthe second harmonic suppression are dBm at 7.9 GHzand dBc, respectively. Fig. 16 and 17 show simulatedcharacteristics of VCOs with and without GSML structure.The operating frequency of the GSML based VCO varied from7.32 to 8.18 GHz with a tuning voltage varying from 0 to2.8 V. This shows a negative frequency tuning of 860 MHz.The phase noise of the VCO was dBc/Hz at 1-MHzoffset. Table I summarizes the performances of VCOs with andwithout GSML, and Table II provides a measurement summaryof an 8-GHz VCO. The frequency tuning range is one of themost important requirements in VCO design. The start andstop frequencies of the 2 VCOs deviate by 1.02 and 1.14,


Fig. 16. Simulated output power, oscillation frequency, and second harmonicsuppression characteristics of VCO versus Frequency tuning voltage. (a) VCOwith GSML. (b) VCO with elimination of GSML.

Fig. 17. Simulated phase noise versus frequency tuning voltage.

respectively. These deviations measure how the oscillationfrequency of the VCO ideally set by the LC resonator is in

TABLE ISIMULATION RESULTS SUMMARY OF VCOS

TABLE IIMEASUREMENT SUMMARY OF 8-GHZ VCO

Fig. 18. Photograph of microbuffered VCO chip.

practice perturbed by the interconnect parasitic components.The accurate quantification of the parasitics in the GSML VCOwill allow to achieve closer agreement between simulation andmeasurement results. Note also that the output power and phasenoise exhibit improved performance when using GSML.

V. MEASUREMENT RESULTS

The VCO chip occupies an area of 0.57 mm by 0.89 mm in-cluding all wire bonding pads as shown in Fig. 18. The practicalchip occupation will be reduced to 0.40 mm by 0.62 mm if it isintegrated as a component in a monolithic RF transceiver cir-cuit. After grinding to 235- m thickness, the processed chipswere wire-bonded to the circuit board and tested with a HP8563E spectrum analyzer.

The oscillator shows dBm output power at 8.35 GHzas shown in Fig. 19. The second harmonic suppression is

dBc as shown in Fig. 20. The even order harmonics


Fig. 19. VCO output spectrum.

Fig. 20. VCO harmonic spectrum performance.

will be even more reduced when the VCO is connected as adifferential LO supply circuit to the balanced mixer, due tothe even harmonic cancellation in the differential VCO circuittopology. The VCO achieves a phase noise of dBc/Hzat 1-MHz offset as shown in Fig. 21. A 3-V battery was usedas dc bias source for phase noise measurements to reduce theDC-FM noise contribution normally produced by standardpower supply [18]. The VCO operating frequency was variedfrom 7.35 to 8.55 GHz with a tuning voltage variation from0 V to 2.8 V as shown in Fig. 22. This is a negative frequencytuning of 800 MHz. The dc current consumption is 12 mA at3-V voltage supply.

VI. CONCLUSION

The accurate and reliable GSML layout methodology wasused in the design of a VCO. The ground shield layer is con-formed to the circuit such that the interconnection lines are

Fig. 21. VCO phase noise at 1-MHz offset from 8.347-GHz carrier.

Fig. 22. Output power, oscillation frequency, and 2 harmonic suppressioncharacteristics of VCO in terms of frequency tuning voltage.

shielded from the low resistive silicon substrate. This layoutmethodology has the advantage of greatly simplifying the esti-mation of the parasitic networks for the interconnection lines atthe expense of introducing trivial amount of loss. This structurealso reduces cross-talk and noise from the low resistive siliconsubstrate.

In this work, the GSML method replaced the post layout sim-ulation and reduced iteration times, increasing efficiency in thedesign and optimization of the circuit.

A fully integrated differential tuning SiGe HBT 8-GHz VCOwas designed and tested. It has negative tuning frequency rangeof more than 10% with a positive tuning voltage change of 2.8 V.The measured phase noise for the VCO was dBc/Hz at1-MHz offset with an output power of dBm. The measuredoscillation frequency and output power were close to those pre-dicted by the simulation using GSML.

The VCO chip size, dc power consumption, output power,and the phase noise are comparable to other monolithic oscil-lators and are believed to deliver optimal results for monolithicoscillators intended for 8-GHz RF transceivers.

This work demonstrated that GSML is an effective and usefullayout method which leads to reliable design even for sensi-tive autonomous circuits such as oscillators. GSML provides analternative RFIC layout methodology which simplifies designprocedures by eliminating the post layout simulation procedurewhich is believed not to be reliable at high radio-frequencies.


ACKNOWLEDGMENT

The authors would like to thank to IC Design EducationCenter for providing computer-aided design tools. The firstauthor would like to thank Mr. Wetterskog of Texas Instrumentsfor organizing the TI graduate student fellowship.

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Jongsoo Lee was born in Dangjin, Korea, in 1974. Hereceived the B.S degree in physics from Chung-AngUniversity, Seoul, Korea, in 1999, and the M.S de-gree in electrical engineering from The Ohio StateUniversity, Columbus, in 2003, where he is currentlyworking toward the Ph.D. degree

From 2000 to 2006, he received Texas Instrumentsfellowship. As part of the requirement of his M.S.thesis, he developed inductor structures for a high-Qfactor and designed a CMOS mixer. His recent workis focused on the design of a WCDMA transmitter

and development of linearization scheme for a WCDMA transmitter. He is alsoinvolved with 900-MHz RFID transceiver development and ubiquitous 8-GHzwireless transceiver development. His research interest is RF and analog inte-grated circuit design.

Young-Gi Kim (M’06) was born in Seoul, Korea. Hereceived the B.S. and M.S. degrees in electronics en-gineering from Hanyang University, Seoul, Korea, in1983 and 1984, respectively, and the Ph.D. degreefrom the University of Texas at Arlington in 1993.

From 1986 to 1997, he was with Korea TelecomResearch Laboratory, where he was engaged withlong-distance optical fiber communication anddeveloped Monolithic Microwave Integrated Cir-cuits for wireless application. In 1996, he movedto Anyang University, Anyang, Korea, where he is

currently a Professor in the Department of Data Communication Engineering.His research interests are included radio frequency integrated circuits anddevices.

Eun-Jin Lee was born in Jin-Hea, Korea, in 1980.He received the B.S. and M.S degrees in informa-tion comunication and engineering from the AnyangUniversity, Anyang, Korea, in 2005 and 2007, respec-tively. He is working toward the Ph.D. degree in theCollege of Electrical Engineering and Computer Sci-ence, Kook Min University, Seoul, Korea.

His research interests include CMOS RF circuitsfor wireless communication system and RFID.

Chang-Woo Kim (M’93) was born in Seoul, Korea,in March, 1961. He received the B.S. and M.S.degrees in electronic engineering from the HanyangUniversity, Seoul, in 1984 and 1986, respectively,and the Ph.D. degree in elecronic engineering fromthe Shizuoka University, Hamamatsu, Japan, in1992.

From 1992 to 1996, he was with the Microelec-tronics Laboratories, NEC Corporation, Tsukuba,Japan, where he worked on the high-frequency andhigh-power heterojunction devices and ICs used for

mobile and satellite communication applications. Since 1996, he has been withthe Department of Radio Communication Egineering, Kyung Hee University,Gyeonggi-do, Korea, where he is a professor. From 2004 to 2005, he wasa visiting professor of the Radio Communication Laboratory, University ofCincinnati, OH, USA. His research interests include microwave/mm-wavesoild-state device modeling, MCIC and MMIC design, and RF characterization.

Dr. Kim is a member of IEEK, KIEE, KEES, and IEICE.

Patrick Roblin (M’85) was born in Paris, France, inSeptember 1958. He received the maitrise de physicsdegree from the Louis Pasteur University, Strasbourg,France, in 1980, and the M.S. and D.Sc. degrees inelectrical engineering from Washington University,St. Louis, MO, in 1982 and 1984, respectively.

In 1984, he joined the Department of ElectricalEngineering, at The Ohio State University (OSU),Columbus, OH, as an Assistant Professor and iscurrently a Professor. His present research interestsinclude the measurement, modeling, design and

linearization of nonlinear RF devices, circuits and systems such as oscillators,mixers, and power-amplifiers. He is the author of textbook on High-SpeedHeterostructure Devices published by Cambridge University Press. He hasdeveloped at OSU two educational RF/microwave laboratories and associatedcurriculum for training both undergraduate and graduate students. He is thefounder of the nonlinear RF research lab.

2128 ieee transactions on circuits and systems—i: …

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