2008 a new model of sub threshold swing for sub-100 nm mosfets

8/3/2019 2008 a New Model of Sub Threshold Swing for Sub-100 Nm MOSFETs

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A new model of subthreshold swing for sub-100 nm MOSFETs

Lin-An Yang *, Chun-Li Yu, Yue Hao

School of Microelectronics, Xidian University, Xian 710071, China

Received 8 April 2007; received in revised form 16 May 2007Available online 10 August 2007

Abstract

A novel subthreshold swing model that linearly depends on the drain bias voltage (Vds) and negative-exponentially depends on theeffective channel length (Leff) is proposed for LDD MOSFETs on 90 nm CMOS technology. It simplifies the description of the effectivegate overdrive voltage (Vgte) and yields a single-equation IVcompact model to present the transition of the drain current (Ids) betweensubthreshold and strong inversion. The simulation shows an excellent prediction to the characteristics of sub-100 nm MOSFETs espe-cially in the subthreshold region that is very important in reliability analysis of short channel devices. Compared with the existing thresh-old voltage-based compact models, the modeling is low in calculation consumptions therefore suitable for the circuit simulation. 2007 Elsevier Ltd. All rights reserved.

1. Introduction

While MOS devices scaling down to the ultra-deep sub-

micron regime, the supply voltage decreases to the level oflower than 1 V in practice. In this case, an accurate sub-threshold current model of MOSFETs finds more valuableapplication in reliability analysis of devices. Among theexisting threshold voltage-based compact models for shortchannel devices, the BSIM series still dominate the regimeof the devices technology before 65 nm node because ofgood accuracy and easy understanding [13], despite somedrift-diffusion surface potential-based models have foundrapid developments for nanometer MOS devices. Normally,the modeling of IV characteristics include a diffusioncurrent-based subthreshold current model, a drift-current-

based strong inversion current model and a smooth transi-tion model between the two regions, all of which require alarge number of fitted and extracted parameters to maintainthe modeling accuracy. When the gate oxide thicknessdecreases to 12 nm regime in sub-100 nm MOSFETs, thereappear some enhanced effects, such as gate and drain leak-age induced by gate tunneling, reverse short channel effectinduced by high substrate doping, parasitic resistance

caused by shallow source/drain junction, etc., all of whichnot only significantly degrade the subthreshold characteris-tics of devices, but also increase the complexity of device

modeling. In BSIM4 model [3], for example, a complicatedmodel of effective gate overdrive voltage (Vgte) is employedto smooth the current discontinuity between strong inver-sion and subthreshold regions in order to form a unifiedIVmodel. Although possessing a good accuracy, this kindof device model is of great inconvenience for circuit simula-tion since too many fitting parameters are required. Thusthis work put the emphasis on developing a concise modelof effective gate overdrive voltage (Vgte), wherein a novelsubthreshold swing model with fewer fitting parameters isproposed, aimed at obtaining an empirically based IVmodel with single-equation for both the subthreshold

region and the strong inversion region, needless anothersubthreshold current model as that in BSIM4 model. TheLDD MOSFETs with the mask gate lengths ranging from90 nm to 0.50 lm and the gate oxide thickness of 1.24 nmfabricated on 90 nm CMOS technology are investigated toverify the modeling of ultra-deep submicron devices.

2. Modeling of ultra-deep submicron MOSFETs

In the theory of inversion charge of MOSFETs, thestrong inversion and the weak inversion are two important

0026-2714/$ - see front matter 2007 Elsevier Ltd. All rights reserved.

doi:10.1016/j.microrel.2007.06.007

* Corresponding author. Tel.: +86 29 88201759; fax: +86 29 88201641.E-mail address: [email protected] (L.-A. Yang).

www.elsevier.com/locate/microrel

Available online at www.sciencedirect.com

Microelectronics Reliability 48 (2008) 342347
mailto:[email protected]:[email protected]


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regions for modeling. First of all, we summarize the mod-eling in strong inversion where the gate voltage Vgs is largerthan the threshold voltage Vth. In this region, a universaldrain current characteristic derived from the inversioncharge for short channel MOSFET has been modeled by [4]

Ids

WCoxleff

Leff 1 VdsxLeffEc

Vgs Vth 0:5aVdsx

Vdsx 1 ldEc

Leff ldEc Vdsx

; 1

where Vdsx is defined as the effective drain voltage replacingthe saturation voltage Vdsat to smooth the drain currenttransition from linear to saturation regions [4]. The otherparameters such as the effective channel length Leff, velocitysaturation region length ld, critical saturation electric fieldEc, and effective mobility leff are determined by parameterextraction. W and Cox are the gate width and gate oxidecapacitance. This widely used IV model can present the

drain current characteristics in whole the linear and the sat-uration regions, i.e., the low and high Vds regions. Theshortcoming of this kind of Vth-based model is that it isalways sensitive to the accuracy of parameter extractions.

With a drastic decrease of supply voltage for deep-sub-micron devices, the performance of devices in weak inver-sion, i.e., in subthreshold region, becomes more and moreimportant. For modeling the drain current in subthresholdregion where Vgs < Vth, an effective gate overdrive voltageVgte is developed to replace the term (Vgs Vth) in (1).For example, BSIM3 and BSIM4 give a kind of Vgte model,shown as [2,3]

Vgte nVt ln 1 exp

mVgseVthnVt

h in om nCoxe

ffiffiffiffiffiffiffiffiffiffiffiffiffiffi2Us

qNDEPesi

qexp

1mVgseVthV0off

nVt

h i ; 2where Vt = kBT/q is the thermal voltage, and the offsetvoltage V0off, modifying coefficient m

*, effective gate voltageVgse, etc., are obtained by extraction, most of which requirea large number of fitting parameters to maintain the mod-eling accuracy [3]. Among these parameters, the subthresh-old swing n is an important parameter for describing thedrain current characteristics in subthreshold region andtransition region, which is modeled in BSIM4 by

n 1 NFACTOR CdepCoxe

Cdsc Term CITCoxe

; 3

where

Cdsc Term CDSC CDSCD Vds CDSCB Vbseff

0:5

cosh DVT1Lefflt

1

: 3a

Obviously, the definition of n is of some complexity, andthe yielding Vgte model requires too many fitting coeffi-cients, which is inconvenient for circuit simulation. Besides,another subthreshold drain current different from (1) is still

required, which is modeled by [3]

Ids lW

L

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiqesiNDEP

2/sV2t

s1 exp

Vds

Vt

expVgs Vth V

0off

nVt

: 4

Thereby (2) accompanied with (3) is used to match the

smooth transition between (1) and (4). The modeling accu-racy has been widely accepted in suitable device regime.

3. Concise Vgte model with a novel definition of subthreshold

swing

To circumvent the complexity of above mentionedmodel, a more concise Vgte model is proposed in this workas

Vgte g ln1 eVgsVth=g: 5

With this model, Eq. (1) can be directly used to describe the

subthreshold characteristics, needless adding another sub-threshold drain current model such as (4). Clearly theimplement is much easier than those in existing models[25]. Note that g is a key parameter to govern the accuracyof the drain current transition between subthreshold andstrong inversion in this Vgte model. Generally speaking, gis related with nVt similar to that in (2). For long channelMOSFET, the subthreshold swing n is often regarded asa constant, so is nVt. Some previous models for short chan-nel devices also employ the constant n for simplicity. Infact, g closely depends on the bias voltages due to thatthe surface potential /s is related to the bias voltage instead

of a constant in short channel device. Thus this work givesa concise definition to the parameter g as

g nVt; 6

where a new subthreshold swing n is modeled by taking thedrain bias and the channel length into account, and omit-ting the influence of substrate bias by forcing Vsb = 0,shown as follows

n n0 fLeff; Vds: 7

This n model consists of two terms: n0 is defined as the sub-threshold swing of long channel device and is regarded as aconstant; f(Leff, Vds) is a function related with effectivechannel length and drain voltage, and is determined byparameters extraction. In the long channel device, the con-tribution of f (Leff, Vds) is very weak because of bias-inde-pendent surface potential, thus g approximately equalsthe constant n0Vt. With shortening of the channel, theinfluence of f (Leff, Vds) on the subthreshold swing in-creases. To unveil this tendency, the LDD NMOSFETswith different mask gate lengths are used for parameterextraction by using Eqs. (1), (5), (6) and (7). The extractionresults in Fig. 1 gives an approximately linear dependencebetween n and Vds, and further, the influence of Vdsincreases with shrinkage of the channel length. Conse-

quently, the y-axis intercepts and the slopes of these n

L.-A. Yang et al. / Microelectronics Reliability 48 (2008) 342347 343


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versus Vds straight lines can be calculated. The results andthe fitting curves are drawn in the inset of Fig. 1. It clearlyshows a negative-exponential dependence of the interceptand slope on the effective channel length Leff, where the Leffextraction is discussed later. With the curves the functionf(Leff, Vds) can be easily determined by optimization, there-fore the model (7) can be written in details by

n n0 a1 eLeff=l0 a2 Vds; 8

where a1 and a2 are the fitting coefficients, l0 is definedas the critical length. This yields the intercept of n0 +a1 a2exp(Leff/l0) and the slope of a1exp(Leff/l0). By leastsquare optimizing both negative-exponential curves simul-taneously, the parameters can be obtained as: n0 = 2.75(normally, the empirical value of n0 is between 1 and 3for long channel devices), a1 = 3.36, a2 = 2.29, andl0 = 0.033 with the same dimension as Leff. Mathematically,the term exp(Leff/l0) in (8) tends to zero when Leff is large,but can not be omitted when Leff< 5l0. That means theinfluence of Vds on n must be taken into account whenLeff< 0.165 lm, i.e., the mask gate length Lmask is approx-imately lower than 0.2 lm. Note that Leff= Lmask DL,and the extracted channel length reduction DL of0.0252 lm from the referenced devices will be discussedlater. Thus for ultra-deep submicron device, the increaseofn with Vds will slow down Vgte changing from Vgt to zero(see Eq. (5)), certainly enlarge the subthreshold current dueto the current continuity. The result is consistent with thetendency in other existing models that the subthresholdcurrent is empirically proportional to 1 exp(Vds/Vt)[3,6]. Instead of the gate overdrive voltage (Vgs Vth) bythe new Vgte model (5), the IV model (1) is suitable fornot only the strong inversion but also the subthresholdregion. Thus the improved IV model with a simple Vgte

expression does not require another diffusion current

model in subthreshold region. Especially, the new sub-threshold swing n model requires only four fitting coeffi-cients, which are much lower than that in (3), thereforesignificantly reduces the calculations for circuit simulation.In some literatures such as [7], a single-equation IVmodelis also developed which shows accurate and practical

results in subthreshold region. But the modeling of Vgte isstill complicated and requires more fitting coefficients com-pared with the new model. Further, literature [7]employsthe longer channel MOSFETs on 0.25 lm CMOS technol-ogy, in which case the model can not present the clearinfluence of Vds and Leff.

4. Parameter extraction for IV modeling

The ultra-thin gate oxide (tox = 1.24 nm) LDD NMOS-FETs with W/Lmask = 6/0.09, 0.13, 0.16, 0.22, 0.28, 0.35and 0.5 lm fabricated on 90 nm CMOS technology arereferenced in this work. First of all, we employ themeasurement-based threshold voltages model, as is givenby [4]

Vth Vth0Vds50 mV rVds

Vth0Vds50 mV e0eSir0 r1 Vsb

pCoxLmeff

Vds; 9

where Vth0Vds50 mV is the extraction from IdsVgs charac-teristic at Vds = 50 mV by transconductance change (TC)extraction technique which is found well for ultra-thin gateoxide MOSFETs among existing Vth extraction techniquesbecause it can reduces the impact of parasitic resistance

and mobility variation [8]. Different devices with the gatelengths ranging from 0.09 lm to 0.5 lm are employed forVth extraction, where different drain biases are suppliedto present the reverse short channel effect (RSCE) inducedby the heavy doping of channel which is widely used in ul-tra-deep submicron device. Given in Fig. 2 are the ex-tracted Vth at 50 mV and 1.5 V drain biases and zero

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6

3

4

5

6

7

8

Symbol: extractionCurve: fitting

Intercept

Effective Gate Length, L (m)

Slope

Lmask

=0.09m

Lmask

=0.13m

Lmask

=0.16m

Lmask

=0.22m

Lmask

=0.28m

Lmask

=0.35m

SubthresholdSwing,n

Drain Voltage, Vds

(V)

Fig. 1. Plots ofn against Vds extracted from LDD NMOSFETs with themask gate lengths ranging from 90 nm to 0.35 lm. The inset is the plots ofy-axis intercepts and the slopes of n versus Vds straight lines, where the

solid lines are the curves fitted by negative-exponential function.

0.0 0.1 0.2 0.3 0.5 0.6

0.2

0.3

0.4

0.5

0.6

0.7

0.8

(V =0)

V =0.05V

V =1.5V

ThresholdVoltage,

V

(V)

Gate Mask Length, L (m)

0.4

Fig. 2. Extracted threshold voltage Vth by TC method at drain bias

voltages of 50 mV and 1.5 V, respectively. The substrate bias is zero.

344 L.-A. Yang et al. / Microelectronics Reliability 48 (2008) 342347


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substrate bias, where the plot of Vth versus Lmask clearlypresents the RSCE tendency. After several drain and sub-strate biases, the measured IdsVgs data are used to deter-mine the fitting parameters r0, r1 and m in (9) byoptimization and the results are listed in Table 1. Com-pared with the existing Vth models based on experiments[3,9], Eq. (9) is more convenient to present the effect ofdrain induced barrier lowering (DIBL). More importantly,the motivation of our using the measured Vth instead ofcalculation-based Vth model is to maintain the accuracyof Vth-based model (1) for simulating IV characteristicsof LDD NMOSFETs.

Secondly, the drain/source parasitic series resistance

Rds, the channel length reduction DL, the effective mobilityleff, etc., are imperative for device modeling. Practically,the constant Rds, DL, and low electric field l0 are desiredfor compact model. But the significant gate leakage, drasticmobility degradation and Vth shift always impact themeaningful parameter extractions in ultra-deep submicrondevices. Based on the widely used L-array method, thiswork employs Vth optimization technique to extract aboveparameters [10]. With this technique, the extraction errorcaused by significant gate leakage and Vth shift is greatlyreduced, and the fluctuation of extracted results by differ-ent existing methods also shrinks. The constant Rds, DL,

and l can be easily obtained in high gate bias region whichis reasonable in compact model for circuit simulation. Theresults from the referenced devices by this extractionmethod are listed in Table 1. To other important parame-ters, the extracted Vdsat by means of G-function methodcan be used to optimize the parameters Ec, a, d0 and Awhich are required in Vdsat and Vdsx expressions. Theresults are also given in Table 1.

5. Simulation results and discussion

With above proposed models and parameter extrac-tions, Fig. 3 gives the simulated and measured drain cur-rent and drain conductance characteristics of device withmask gate length of 90 nm. The drastic channel lengthmodulation (CLM) effect and drain induced barrier lower-ing (DIBL) effect are well modeled by excellent agreementbetween simulation and measurement in linear and satura-tion regions. Further more, Fig. 4 presents the measuredand simulated IdsVgs and gmVgs characteristics at differ-ent drain biases, showing a good continuity of the firstorder of drain current model in reversion region. Fig. 5shows the comparison between the simulated and mea-sured drain current of 90 nm device in the low gate biasregion. The significant degradation of subthreshold charac-

teristics with the increasing Vds is accurately predicted,

which implies that the improved IVmodel is valid in sub-threshold region for sub-100 nm devices. The serious deg-radation of subthreshold current at high Vds is due to theultra-thin gate oxide in the referenced device which isreflected on the high value of a1 in (8). It can be predictedthat a1 will decrease with the improvement of gate oxidetechnology. To verify the model in longer channel devices,the LDD NMOSFETs with the gate lengths ranging from0.13 lm to 0.35 lm are investigated. Fig. 6 gives the outputdrain currents in linear and saturation regions at the gatebiases of 0.6 V and 1.2 V. A good agreement between sim-ulation and measurement demonstrates that the new model

is suitable for the wide range of gate length. Fig. 7 gives

Table 1Extracted parameters for modeling of IV characteristics

Rds(x) DL (lm) l0 (cm2/Vs) Ec (V/cm) a d0 A m r0 r1

25.32 0.0252 158.3 2.55 104 1.06 0.2 10 1.5 1.8 0.3

0.0 0.3 0.6 0.9 1.2 1.5

0

5

10

15

20

0.3 V

0.6 V

0.9 V

1.2 V

Vgs

=1.5 V

DrainConductance,gds

(mS)

Drain Voltage, Vds

(V)

DrainCurrent,Id

s(mA)

Symbol: measurement

Solid Line: simulation

W/Lmask

=6/0.09 m

-1

0

1

2

3

4

5

6

7

Fig. 3. Measured and simulated output drain current and drain conduc-tance of LDD NMOSFET with 90 nm mask gate length.

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4

0

1

2

3

4

5

6

7

8

Symbol: measurement

Solid line: simulation

W/Lmask

= 6/0.09m Vds=0.05V

Vds

=0.55V

Vds

=1.05V

Vds

=1.50V

DrainCurre

nt,Id

s(mA)

Gate Voltage, Vgs

(V)

0

2

4

6

8

10

Transconducta

nce,g

m(

mS)

Fig. 4. Measured and simulated IdsVgs and gmVgs characteristics ofLDD NMOSFETs with mask gate length of 90 nm at different drainbiases.



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the variation of drain current with the channel length insubthreshold and transition regions at low drain bias(Vds = 50 mV) and Fig. 8 at high drain bias (Vds = 1.5 V)respectively. It is observed that the subthreshold character-istics significantly degrade when the gate length shrinks tosub-100 nm regime, and a serious degradation occurs withincreasing Vds. In summary, the excellent agreementsbetween simulations and measurements indicate that theproposed IV model is valid not only in strong inversionbut also in subthreshold region for devices from deep toultra-deep submicron regime. Thus the new subthreshold

model is valuable in reliability prediction of devices andits simplicity is desirable for circuit simulation.

6. Conclusions

This work proposes an improved model of effective gateoverdrive voltage Vgte with a novel definition of the sub-threshold swing n. This leads to a simple subthreshold cur-rent model that includes a linear-dependence of n on thedrain bias voltage and an negativel-exponential depen-dence of n on effective channel length, both of which areexperimentally proved by extraction from ultra-thin gateoxide LDD MOSFETs with the gate lengths ranging from90 nm to 0.35 lm on 90 nm CMOS technology. With thisconcise model, the degradation of subthreshold character-istics in sub-100 nm devices is well predicted, which isimportant in reliability analysis of ultra-deep submicrondevices and circuits. The comparison between simulationsand measurements shows that the improved IV model issuitable for devices from deep to ultra-deep submicronregimes. Furthermore, this model avoids the complicatedVgte modeling and another subthreshold current modelemployed in some existing models, thus reduces the calcu-lations of the single-equation IVcompact model for wholethe bias voltage region which is valuable for circuit

simulations.

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

1x10

1x10

10

10

10

10

10

Symbol: measurementSolid line: simulation

W/Lmask

= 6/0.09m

V =0.05V

V =0.55V

V =1.05V

V =1.50V

DrainCurrent,

Ids

(mA)

Gate Voltage, Vgs

(V)

Fig. 5. Measured and simulated subthreshold currents of 90 nm LDDNMOSFETs at different drain biases.

0.0 0.4 0.8 1.2 1.6

0

1

2

3

4

(Vgs

=0.6 V)

Symbol : measurement

Solid line : simulation

(Vgs

=1.2 V)

Lmask

=0.13m

0.16m

0.22m

0.28m

0.35m

DrainCurrent,Id

s

(mA)

Drain Voltage, Vds

(V)

0.2 0.6 1.0 1.4

Fig. 6. Measured and simulated output drain current of LDD NMOS-FETs with mask gate lengths ranging from 0.13 lm to 0.35 lm.

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.710

10

10

10

1x10

1x10

10

10

10

10

10

Lmask

=0.09m

0.13m

0.16m

0.22m

0.28m

0.35m

Symbol: measurement


Gate Voltage, Vgs

(V)

DrainCurrent,Id

s

(mA)

(V =50mV)

Fig. 7. Measured and simulated Ids Vgs characteristics of LDD NMOS-

FETs with mask gate lengths from 0.09 lm to 0.35 lm at Vds = 50 mV.

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.710

10

10

10

1x10

1x10

10

10

10

10

10

Symbol: measurement


Lmask

=0.09m

0.13m

0.16m

0.22m

0.28m

0.35m

(V =1.5V)

DrainCurrent,

Ids

(mA)

Gate Voltage, Vgs

(V)

Fig. 8. Measured and simulated IdsVgs characteristics of LDD NMOS-FETs at Vds = 1.5 V.

346 L.-A. Yang et al. / Microelectronics Reliability 48 (2008) 342347


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Acknowledgements

The project is supported by the National Natural Sci-ence Foundation of China (Grant No. 60376024). TheLDD MOSFETs on 90 nm CMOS technology were fabri-cated at Semiconductor Manufacturing International Cor-

poration, Shanghai.

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[3] Liu WD et al. BSIM4v1 MOSFET Model Manual. Berkeley: Uni-versity of California; 2000.

[4] Arora N. MOSFET Models for VLSI Circuit Simulation Theory andPractice. Springer-Verlag; 1993.

[5] Cheng Y et al. A unified MOSFET Channel charge model for devicemodeling in circuit simulation. IEEE Trans. CAD Integrat. CircuitsSyst. 1998;17(8):6414.

[6] Chen MJ, Ho JS. A three-parameters-only MOSFET subthresholdcurrent CAD model considering back-gate bias and process variation.IEEE Trans. CAD Integrat. Circuits Syst. 1997;16(4):34352.

[7] Lim KY, Zhou X. MOSFET subthreshold compact modeling witheffective gate overdrive. IEEE Trans. Electron. Devices 2002;49(1):1969.

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2008 a new model of sub threshold swing for sub-100 nm mosfets

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