On Clock Network Design for Sub-threshold Circuitry1
Outline
Clock Topology Discussion for Sub-threshold
Summary
Questions
2
Outline
Clock Topology Discussion for Sub-threshold
Summary
Questions
3
Pdyn=α0-1CeffVDD2f
Transistor devices not “on”…
Sub-VT characterized by weak drive and long delay
And great savings in dynamic power/energy
Wide application space
Slew and skew affect timing constraints
CAUSES TIMING VIOLATIONS
REG
Setup constraint
Hold constraint
Designer has control over tslew,max, Cmax, δmax
module example(…)
Clock Topology Discussion for Sub-threshold
Summary
Questions
7
Setbacks of sub-threshold impose difficulty for quality clock network
Exponential dependency on VT variation
vs
Wire delay no longer a factor
Wire load still relevant
Both skew and slew
Monte Carlo simulation of delay exhibiting non-Gaussian distribution
Delay(s)
Short circuit power(not a focus in super-threshold)
Low drive strength=less control(10’s ns vs. 1 ps)
Scaling won’t work
Can re-design directly in sub-threshold, but undermines low power
Example of register
Scaled Clock Tree
Clock Topology Discussion for Sub-threshold
Summary
Questions
10
Tighter nodal capacitance constraint CMAX will corral slew
Slew recovery through buffer is stronger function of CMAX than input slew
Therefore, use higher CMAX near clock source, smaller CMAX at registers
Relationship between slew, CMAX , and power
Output slew vs. load cap and input slew
Resulting clock tree shape
Clock Topology Discussion for Sub-threshold
Summary
Questions
12
Solution: circuit in sub-threshold, clock network not
Capacitive Boosting:
No level converter overhead
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Shortcomings:
Greater area
Complexities with timing and clock gating(1/2 cycle startup)
Doesn’t save power at lower frequencies for set VDD
Doesn’t necessarily address process variations
Advantages:
Drastic improvement in slew (2.6x at 0.4V, 1 pF load)
Better overall clock network energy due to fewer # of buffers
Drastic improvement in skew
Improvement in slew[4]
Improvement in skew[4]
Clock Topology Discussion for Sub-threshold
Summary
Questions
15
Conventional tree scrutinized
vs
Energy overhead incurred under same nominal skew constraint for non-buffered trees[3]
Skew and slew improvement with non-buffered trees[3]
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Measurements show improvement in skew, skew variation, and slew variation without much overhead
4 orders of magnitude less skew
28% less slew variation
Drawback: design not suitable across all circuit sizes
Drawback: design not suitable across all constraints
Skew and slew improvement with non-buffered trees[3]
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Outline
Clock Topology Discussion for Sub-threshold
Summary
Questions
18
Summary
Slew Aware Clock Tree Design for Sub-threshold:
Good for slew control by design
Universal for all clock network topologies
Always saves something in power
Does not address variations
A Clock Buffer Design for Sub-threshold:
Fantastic performance with regards to slew and skew
Given range of supply voltage that it addresses process variations
Ridiculous increase in power/energy for single buffer
Thus restricted to certain frequencies and design sizes
Clock Network Design for Sub-threshold
Method address slew, skew, process variations
Power/energy overhead fluctuates with design characteristics
What does it all mean?
Imminently, no universal solution
We should carefully observe the characteristics of our design, and design accordingly
Example: Combine papers [3] and [4]?
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References
[1] B. H. Calhoun., A. Wang, N. Verma, A. P. Chandrakasan, "Sub-threshold Design: The Challenges of Minimizing Circuit Energy," International Symposium on Low Power Electronics and Design (ISLPED), pp. 366-368, October 2006.
[2] J. R. Tolbert, X. Zhao, S. K. Lim, S. Mukhopadhyay, “ Slew-Aware Clock Tree Design for Reliable Subthreshold Circuits”, ISLPED, August 2009.
[3] Jonggab Kil, et al, “A High-Speed Variation-Tolerant Interconnect Technique for Sub-threshold Circuits Using Capacitive Boosting,” ISLPED, 2006, pp. 67-72.
[4] Mingoo Seok, D. Blaauw, D. Sylvester, "Clock Network Design for Ultra-Low Power Applications,"International Symposium on Low Power Electronics and Design, Aug, 2010.
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Questions?
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