2007 level converter

7/31/2019 2007 Level Converter

1/4

A Robust, Input Voltage Adaptive and Low EnergyConsumption Level Converter for Sub-threshold Logic *

Hui Shao and Chi-Ying TsuiDepartment of Electronic and Computer Engineering

The Hong Kong University of Science and TechnologyHong Kong SAR., P. R. China

{shaohui and eetsui}@ee.ust.hk

Abstract A new level converter (LC) is proposed for logicvoltage shifting between sub-threshold voltage to normal highvoltage. By employing 2 PMOS diodes, the LC shows goodoperation robustness with sub-threshold logic input. Theswitching delay of the proposed LC can adapt with the inputlogic voltage which is more suitable for power aware systems.With a simpler circuit structure, the energy consumption of theLC is smaller than that of the existing sub-threshold LC.Simulation results demonstrate the performance improvementand energy reduction of the proposed LC. Test chip wasfabricated using 0.18 m CMOS process. Measurement resultsshow that our proposed LC can operate correctly with an inputat as low as 127mV and an output voltage at 1.8V.

I NTRODUCTION The ultra low power consumption requirement has pushed

the operation of the digital core circuit into the sub-thresholdregion [1-2] for applications that featuring limited energysources and low performance. However, the supply voltage of the I/O interface cannot be scaled down at the same time andthere is a large voltage difference between the core and the I/Ointerface. In multiple V dd logic applications, some logic gates

can be operated in sub-threshold region and there is also alarge voltage difference between the gates that are driven bydifferent voltage domains. For some high performanceapplications, e.g. UWB baseband processor [3], sub-thresholdlogic operation has also been proposed and similar voltagedifference problem exists at the digital/analogue interface. Tosolve these problems, level converter (LC) is required toconvert the voltage of the logic signals across different voltagedomains.

Fig. 1(a) shows the conventional LC circuit [4]. The cross-coupled PMOS transistors improve the switching speed andoutput swing by using the positive feedback. When a 1 isapplied to IN L, INB L becomes 0 and node OUTB H is pulleddown which turns on MP2 and OUT H goes to V DDH . WhenINL changes to 0, INB L rises to V DDL and turns on MN2which pulls OUT H down to 0. However, if sub-threshold logicsignal is used for the input to the LC, due to the low voltagevalue of logic 1 at INB L, the on current through MN2 is veryweak comparing with the on current of MP2. Node OUT H cannot be pulled down and the conventional LC will not functionwell. Fig. 1(b) shows the conventional clock-level shiftedsensing amplifying flip-flop (CSSAFF) circuit which

Figure 1. (a) Conventional LC (b) Conventional CSSAFF

combines the function of LC and D-flip-flop and the same problem exists when the input logic voltage is too low.

Several methods have been tried to reduce the LCminimum acceptable voltage. In [5-6], a signal voltagedoubler (SVD) is employed to double the input logic voltageof the LC in order to increase the pull down ability of MN1and MN2. However, due to the limitation of the SVDstructure, the minimum acceptable input voltage cannot bereduced to sub-threshold value.

In [7], an LC is specially designed for the sub-thresholdinput where two reduced swing inverters (RSI) are employedto drive MP1 and MP2. The structure is shown in Fig. 2. Withthe 2 PMOS diodes in the RSI, the turn on voltage of thecross-coupled PMOS (MP1 and MP2) is limited to|VGS |=2|V PD | where |V PD | is the voltage drop of the PMOSdiode. The pull up ability of MP1 and MP2 is thus reduced.When transistor MN1 or MN2 is turned on with sub-thresholdlogic input, due to the weakening of the PMOS pull upstrength, the small NMOS sink current can still pull the nodeOUT H down to 0 correctly.

Figure 2. (a) Sub-threshold LC in [7] (b) RSI circuit for the LC in [7]

* This work was supported in part by the Hong Kong Research GrantsCouncil under Grant CERG 620305.

1-4244-1125-4/07/$25.00 2007 IEEE. 312Authorized licensed use limited to: UNIVERSIDADE FEDERAL DE MINAS GERAIS. Downloaded on May 11,2010 at 11:25:28 UTC from IEEE Xplore. Restrictions apply.


2/4

However, when the LC input logic voltage increases, e.g.the core of a power aware system is configured to use a higher supply voltage during run-time [8], the pull up time of the LCoutput becomes significant for the deign in [7], since the pullup ability of MP1 and MP2 is limited by the RSI with thevalue |V GS|=2|V PD | which is non-scalable. While the operation

speed of most digital core circuit can scale with the supplyvoltage, the non-scalability of the LC conversion speed may

pose a problem to the system when being operated at higher voltage. In order to avoid this problem, the LC design should

be able to accept both sub-threshold logic and strong inversionlogic inputs and its performance should be adaptive with theinput logic voltage values.

Moreover, for the LC in [7], additional inverters are usedto drive the RSI. This will limit the minimum acceptable inputlogic voltage. When IN L switches to 1, MN1 is tuned on. Inorder to activate the LC positive feedback loop, the appliedlogic 1 voltage should be large enough so that the sink current through MN1 can pull its drain (OUTB H) voltage

lower than the switching threshold voltage of the addedinverter and flip the inverter output. Furthermore, theadditional inverters and RSI consume a significant amount of energy which is not preferable for low power applications.

In this paper, we propose a robust, low energyconsumption LC that can accept the sub-threshold logic input,and can adapt its performance with the input logic voltagevalues. By always keeping the PMOS pull up ability at aminimum value at the steady state and the initial period of theconversion, the sub-threshold turn on current of the NMOStransistor can easily pull its drain voltage down and flip theLC output, which results in robust operation for the LC.During the process of level conversion, the pull up ability of the PMOS adapts with the input logic voltage and the LC

performance can thus be scalable. Moreover, the LC energyconsumption during the conversion is very low since there isno additional circuit inside the proposed LC. The samestructure can be applied to conventional CSSAFF. To verifythe robustness of the operation and the performanceimprovement across a large input voltage range, the proposedLC was designed and fabricated.

PROPOSED SUB-THRESHOLD LEVEL CONVERTER To make sure the LC work correctly for sub-threshold

logic input, we need to limit the pull up ability of the cross-coupled PMOS transistors. Here we propose a new LCarchitecture by employing 2 additional PMOS diodes. The

proposed architecture is shown in Fig. 3(a).As shown in Fig. 3, 2 additional PMOS diodes (MP3 andMP4) are connected in series with the 2 original cross-coupled

Figure 3. (a) Proposed sub-threshold LC (b) Operating analysis of the LC

PMOS transistors (MP1 and MP2). When the LC is at steadystate, the |V GS | of the PMOS diodes is very small which equalsto the diode voltage drop |V PD|. At the same time, the original

pull-up PMOS transistors are either turned on or turned off,depending on the input value. When the input logic switches,e.g. IN L switches from 0 to 1 as shown in Fig. 3(b), the

|VGS | of the PMOS diode MP3 will not change so quickly andit maintains at its initial value of |V PD |, which limits the pull upstrength of the left branch. On the other hand, the input sub-threshold logic 1 weakly turns on the transistor MN1. Due tothe weak pull up ability of the diode MP3, the small sink current of MN1 will pull down the voltage of node A at theinitial level conversion period. Meanwhile, the voltage drop atnode A turns on the transistor MP2 in the right branch andactivates the positive feedback. In this way, the circuit canoperates correctly for the sub-threshold logic input.

For the cross-coupled LC designs, the input voltage should be able to activate the LC internal positive feedback in order to make the LC flip its output correctly. When the sub-

threshold logic 1 is inputted to the NMOS gate, e.g. IN L of MN1, the transistor is turned on and its sink current would pull the NMOS drain voltage down. At the same time, the|VDS | of the pull up PMOS is increased and so is its pull upcurrent. Since both the PMOS of LC in [7] and the PMOSdiode of our proposed design work in the sub-thresholdregion, the pull up current is small. The NMOS sink currentthus further decreases the NMOS drain voltage. Meanwhile,the NMOS current will decrease and PMOS current willincrease due to the change of their own |V DS | until the twocurrents are equal. If the voltage drop at the NMOS drain islarge enough, the positive feedback will be activated.Comparing our proposed design with the LC design in [7], theinitial |V GS | of our pull up PMOS diode is |V PD | which is onlyhalf of the value of the LC in [7]. The pull up current of our design is then smaller and the voltage drop at the NMOS drainis larger for the same input voltage. Moreover, for the LC in[7], due to the additional inverter before the RSI, the voltage atthe NMOS drain has to drop lower than inverters switchingthreshold in order to flip the inverter output and activate the

positive feedback. Thus the required voltage drop at the NMOS drain is larger and the minimum acceptable inputvoltage of the LC is higher. For our LC design, we can trigger the positive feedback with a smaller input voltage due to thelarger voltage drop at the NMOS drain and also the drainvoltage is used directly to drive the positive feedback withoutany logic inserted in between.

In power aware systems, supply voltage is varied to matchwith the workload of the system. Therefore the circuit performance has to be adaptive with the operating supplyvoltage. When the core supply voltage V DDL increases, theoperating speed should be higher. At the same time, the delayof the level conversion should also track with the input logicvoltage change automatically. For the cross-coupled LC, thelevel conversion time mainly depends on the speed of the

positive feedback which is determined by the NMOS oncurrent in one branch and the PMOS on current in the other

branch. For the design in [7] and the proposed design, the NMOS on current varies with its |V GS | which is equal to V DDL .For the LC in [7], the PMOS on current is limited by the RSIoutput low voltage which equal to 2|V PD | and is not scalable

313Authorized licensed use limited to: UNIVERSIDADE FEDERAL DE MINAS GERAIS. Downloaded on May 11,2010 at 11:25:28 UTC from IEEE Xplore. Restrictions apply.


3/4

with the supply voltage V DDL . Therefore when the core voltageincreases, the PMOS current does not track with it and theswitching speed is also not adaptive to the change of V DDL .For our design, when a logic 1 is applied to IN L as shown inFig. 3(b), the rate of the voltage drop at node A and hencethe on current of MP2 are both determined by the MN1 sink

current which is adaptive with the input logic voltage. Thespeed of the voltage increase at node OUT H also depends onthe input logic voltage. At the same time, the |V GS | of the twoPMOS diodes and their pull up or pull down ability increase.The speed of the increase depends on the speed of the voltagechange at nodes OUT H and A. Therefore, higher input logicvoltage results in a quicker increase in the |V GS | of the PMOSdiodes and a faster switching time at the LC output. Thus the

proposed LC conversion speed can track with the input logicvoltage values automatically.

In order to increase the noise margin and reduce the static power loss of the logics driven by the LC output, rail to railswing should be provided at the LC output. For the proposed

design, due to the voltage drop of the PMOS diode MP4,when the LC outputs a logic 0, the voltage at the node OUT H is one |V PD | higher than ground which is not preferable. Tosolve this problem, we add 2 NMOS transistors MN3 andMN4, which are controlled by the input of the LC, to fullydischarge the output of the LC to ground. This is shown in Fig.3(a). By doing so, full rail swing can be achieved at the outputof the proposed LC.

When sub-threshold logic is used, it is usually targeted for applications that require very low energy consumption. For this situation, the energy consumption of the LC has also to beminimized. When sub-threshold logic input is used for the LC,the slew rate of the LC output is very long since the NMOS oncurrent is weak and the positive feedback loop is slow. If theLC output is driving static CMOS gates which are powered byVDDH , the energy consumption due to the short circuit currentof the CMOS gates will be high. To reduce the energyconsumption of the LC, the fanout of the LC output should beminimized. For the design in [7], two additional inverters

powered by V DDH are connected to the output to drive the RSI.This increases the energy consumption of the LC. For the

proposed design, we do not have extra logic gate inside the LCdriven by the LC output. Thus the energy overhead is muchsmaller.

The proposed LC architecture can be applied to CSSAFFfor sub-threshold operation, and this is shown in Fig. 4. Byadding 2 PMOS diodes to limit the LC pull up ability and 2

NMOS transistors to fully swing the converted output signal,the sub-threshold clock signal CLK L can be level-convertedto a high voltage to pre-charge the sense amplifier. Duringevaluation, the amplifier outputs the converted high voltagesignal from the sub-threshold data input to set/reset the RSlatch. In order to speed up the evaluation time, the convertedCLK H signal is used to clock the sense amplifier bycontrolling the NMOS gate which is shown in blue circle.

EXPERIMENTAL R ESULTS To demonstrate the performance improvement and the

robustness of the proposed LC, we designed and implementedthe proposed LC using TSMC0.18m CMOS technology. For comparison, we also implemented the conventional LC and

Figure 4. Proposed sub-threshold CSSAFF

the LC in [7]. The same transistor sizing was used for the threedesigns for fair comparison. HPSICE simulations were carriedout to check the performance and energy consumption.

The first experiment was executed to compare the outputdelay of the 3 different LC designs. The input voltage isranged from 0.2V to 1.2V while V DDH is 1.8V. The simulationresults for the typical corner are shown in Fig. 5. From Fig. 5,we can see that the conventional LC does not work when theinput voltage is less than the threshold voltage. For the designin [7], it cannot work correctly when the input voltage is lessthan 0.35V while the lowest input voltage is 0.2 for the

proposed design. We can also see that for low voltage logicinput, our proposed LC has a similar delay as the LC in [7].When the input logic voltage increases, our proposed designcan adapt its performance. The delay is approaching that of theconventional LC when the input logic voltage is higher thanthe threshold voltage. For the design in [7], the performancedoes not track well with the input voltage when it is higher than the threshold voltage. Comparing with the design in [7],the proposed LC reduces the switching delay by 65.3% whenthe input logic voltage is 1.2V.

0.2 0.4 0.6 0.8 1 1.210

-10

10-9

10-8

10-7

10-6

10-5

VDDL (VDDH=1.8V) (V)

L C o u

t p u

t d e

l a y

( s )

Conventional LCLC in [7]Proposed LC

65.3%

Figure 5. LC output delay vs. V DDL

We also compared the energy consumption of the threedifferent LC designs. An inverter was connected to the LCoutput as the load and its energy consumption was included inthe simulation. The simulation results are shown in Fig. 6.From Fig. 6, we can see at high input logic voltages, theenergy consumption of the three designs are similar since theenergy consumed by the LC branches and the inverters driven

by LC output are all very small. With the decrease of the inputlogic voltage, the energy consumption of the logic gates thatare driven by the LC output becomes large due to the largeslew rate of the LC output. Comparing the proposed designwith the design in [7], the energy overhead is smaller since the



4/4

fanout of the LC output is fewer. When the input voltage is0.35V, the proposed design has a 96.5% reduction in energyconsumption when comparing with the design in [7].

0.2 0.4 0.6 0.8 1 1.210

-14

10-13

10-12

10-11

10-10

10-9

VDDL (VDDH=1.8V) (V)

L C e n e r g y c o n s u m p

t i o n p e r s w

i t c h i n g

( J ) Conventional LC

LC in [7]Proposed LC

96.5%

Figure 6. LC energy consumption vs. V DDL

The proposed LC also has a higher immunity against the

power supply bouncing because of its smaller pull up abilityand directly driving the positive feedback without any logic being inserted between. Fig. 7 shows the plot of the minimumacceptable input logic voltage at typical corner against theground bounce. We can see that given a certain ground

bounce, the minimum acceptable input logic voltage of the proposed design is about 0.2V higher than that of the design in[7].

0 0.25 0.5 0.75 1 1.25 1.5

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

Delta VSSH (VDDH= 1.8V) (V)

M i n i m u m

o p e r a

t i n

g V D D L ( V )

LC in [7]Proposed LC

Figure 7. LC minimum acceptable logic voltage vs. ground bouncing

Simulations of the proposed LC at different operationcorners were also conducted and in the worst case, the designcan operate correctly at 0.25V at the FS and SS corner.

The circuits for the conventional CSSAFF and the proposed sub-threshold CSSAFF were also implemented.Simulation in the typical corner shows that the proposeddesign can operate for an input logic voltage as low as 0.2Vwhile the conventional design becomes malfunction at 0.8V.In the worst case FS and SS corner, our design can operatecorrectly at 0.25V.

A tested chip was fabricated where a sub-threshold CRC-5logic block for RFID applications was implemented for testing. The proposed LC was used to convert the CRC-5output signal from a sub-threshold voltage value to 1.8V. Thedie photo is shown in Fig. 8. Figure 9 shows the measuredwaveforms of the output of the LC. It shows that the CRC-5logic can operate correctly with a supply voltage of 127mV.

The proposed LC then correctly shifts the 127mV logic signalto 1.8V.

CONCLUSIONS An LC design has been proposed for the sub-threshold

logic input. With the inserted two PMOS diodes, the LC can

robustly operate for very low input voltage. At the same timethe LC switching speed can track with the input logic voltage.Without any additional logic driven by the LC output insidethe design, the energy consumption of the LC is minimized.The performance improvement and the robustness of theoperation across a wide range of input logic voltage valueswere demonstrated through simulation. Test chip wasfabricated to show the correctness of the LC operation and it isshown that the LC and the sub-threshold logic both work correctly for the V DDL voltage of as low as 127mV.

R EFERENCES [1] A. Wang and A. P. Chandrakasan, A 180-mV subthreshold FFT

processor using a minimum energy design methodology, JSSC,2005.,vol.40, pp. 310-319

[2] B. H. Calhoun, A. Wang and A. P. Chandrakasan, Modeling andsizing for minimum energy operation in sub-threshold circuits,JSSC2005., Vol. 40 pp.1778-1786

[3] V. Sze, R. Blazquez, M. Bhardwaj and A. Chandrakasan, An energyefficient sub-threshold baseband processor architecture for pulsed ultra-wideband communications, ICASSP, 2006, pp. 908-911

[4] K. Usami and M. Horowitz, Clustered Votlage scaling Technique for low power design, ISLD, 1995, pp.3-8.

[5] Y. Kanno, H. Mizuno, K. Tanaka, and T. Watanabe, Level converterswith high immunity to power supply bouncing for high-speed sub-1-VLSIs, Symposium on VLSI Circuits, 2000. pp.202-203

[6] W.T.Wang, M. D. Ker, M. C. Chiang and C. H. Chen, Level shiftersfor high-speed 1V to 3.3V interfaces in a 0.13um Cu-interconnection/low-k CMOS Technology Intl. symposium on VLSItechnology, systems and applications, 2001, pp.307-310

[7] I. J. Chang, J. J. Kims, K. Roy, Robust level converter design for sub-threshold logic, ISLPED, 2006, pp. 14-19.

[8] R. Ge, X. Feng and K. W. Cameron, Performance-constraineddistributed DVS scheduling for scientific applications on power-awareclusters, SuperComputing 2005, pp.34-44.

Figure 8. Die micro-photograph of the test chip

Figure 9. Measured waveforms at the LC output of the test chip


2007 level converter

Documents