18 advanced database systems - cmu 15-721

Parallel Join Algorithms (Sorting)

@Andy_Pavlo // 15-721 // Spring 2019

ADVANCEDDATABASE SYSTEMS

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ctu

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https://twitter.com/andy_pavlo

https://15721.courses.cs.cmu.edu/spring2019/

http://db.cs.cmu.edu/

CMU 15-721 (Spring 2019)

PROJECT #2

This Week→ Status Meetings

Monday April 8th

→ Code Review Submission→ Update Presentation→ Design Document

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http://15721.courses.cs.cmu.edu/

CMU 15-721 (Spring 2019)

PARALLEL JOIN ALGORITHMS

Perform a join between two relations on multiple threads simultaneously to speed up operation.

Two main approaches:→ Hash Join→ Sort-Merge Join

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CMU 15-721 (Spring 2019)

SIMD Background

Parallel Sort-Merge Join

Evaluation

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CMU 15-721 (Spring 2019)

S INGLE INSTRUCTION, MULTIPLE DATA

A class of CPU instructions that allow the processor to perform the same operation on multiple data points simultaneously.

All major ISAs have microarchitecture support SIMD operations.→ x86: MMX, SSE, SSE2, SSE3, SSE4, AVX→ PowerPC: Altivec→ ARM: NEON

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CMU 15-721 (Spring 2019)

Z

SIMD EXAMPLE

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X + Y = Z 87654321

X

SISD

+for (i=0; i<n; i++) {Z[i] = X[i] + Y[i];

}

11111111

Y

x1

x2

⋮xn

y1

y2

⋮yn

x1+y1

x2+y2

⋮xn+yn

+ =



CMU 15-721 (Spring 2019)

Z

SIMD EXAMPLE

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X + Y = Z 87654321

X

SISD

+for (i=0; i<n; i++) {Z[i] = X[i] + Y[i];

}

911111111

Y

x1

x2

⋮xn

y1

y2

⋮yn

x1+y1

x2+y2

⋮xn+yn

+ =



CMU 15-721 (Spring 2019)

Z

SIMD EXAMPLE

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X + Y = Z 87654321

X

SISD

+for (i=0; i<n; i++) {Z[i] = X[i] + Y[i];

}

9 8 7 6 5 4 3 211111111

Y

x1

x2

⋮xn

y1

y2

⋮yn

x1+y1

x2+y2

⋮xn+yn

+ =



CMU 15-721 (Spring 2019)

Z

SIMD EXAMPLE

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X + Y = Z 87654321

X

for (i=0; i<n; i++) {Z[i] = X[i] + Y[i];

}

9 8 7 611111111

Y

SIMD

+

8 7 6 5

1 1 1 1

128-bit SIMD Register

128-bit SIMD Register128-bit SIMD Register

x1

x2

⋮xn

y1

y2

⋮yn

x1+y1

x2+y2

⋮xn+yn

+ =



CMU 15-721 (Spring 2019)

Z

SIMD EXAMPLE

6

X + Y = Z 87654321

X

for (i=0; i<n; i++) {Z[i] = X[i] + Y[i];

}

9 8 7 6 5 4 3 211111111

Y

SIMD

+4 3 2 1

1 1 1 1

x1

x2

⋮xn

y1

y2

⋮yn

x1+y1

x2+y2

⋮xn+yn

+ =



CMU 15-721 (Spring 2019)

SIMD TRADE-OFFS

Advantages:→ Significant performance gains and resource utilization if

an algorithm can be vectorized.

Disadvantages:→ Implementing an algorithm using SIMD is still mostly a

manual process.→ SIMD may have restrictions on data alignment.→ Gathering data into SIMD registers and scattering it to

the correct locations is tricky and/or inefficient.

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CMU 15-721 (Spring 2019)

SORT-MERGE JOIN (R⨝S)

Phase #1: Sort→ Sort the tuples of R and S based on the join key.

Phase #2: Merge→ Scan the sorted relations and compare tuples.→ The outer relation R only needs to be scanned once.

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CMU 15-721 (Spring 2019)


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Relation R Relation S

SORT! SORT!



CMU 15-721 (Spring 2019)


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Relation R Relation S

⨝SORT! SORT!

MERGE!



CMU 15-721 (Spring 2019)

PARALLEL SORT-MERGE JOINS

Sorting is always the most expensive part.

Use hardware correctly to speed up the join algorithm as much as possible.→ Utilize as many CPU cores as possible.→ Be mindful of NUMA boundaries.→ Use SIMD instructions where applicable.

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MULTI-CORE, MAIN-MEMORY JOINS: SORT VS. HASH REVISITEDVLDB 2013



https://15721.courses.cs.cmu.edu/spring2019/papers/18-sortmergejoins/p85-balkesen.pdf


CMU 15-721 (Spring 2019)

PARALLEL SORT-MERGE JOIN (R⨝S)

Phase #1: Partitioning (optional)→ Partition R and assign them to workers / cores.

Phase #2: Sort→ Sort the tuples of R and S based on the join key.

Phase #3: Merge→ Scan the sorted relations and compare tuples.→ The outer relation R only needs to be scanned once.

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CMU 15-721 (Spring 2019)

PARTITIONING PHASE

Approach #1: Implicit Partitioning→ The data was partitioned on the join key when it was

loaded into the database.→ No extra pass over the data is needed.

Approach #2: Explicit Partitioning→ Divide only the outer relation and redistribute among the

different CPU cores.→ Can use the same radix partitioning approach we talked

about last time.

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CMU 15-721 (Spring 2019)

SORT PHASE

Create runs of sorted chunks of tuples for both input relations.

It used to be that Quicksort was good enough.

But NUMA and parallel architectures require us to be more careful…

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CMU 15-721 (Spring 2019)

CACHE-CONSCIOUS SORTING

Level #1: In-Register Sorting→ Sort runs that fit into CPU registers.

Level #2: In-Cache Sorting→ Merge Level #1 output into runs that fit into CPU caches.→ Repeat until sorted runs are ½ cache size.

Level #3: Out-of-Cache Sorting→ Used when the runs of Level #2 exceed the size of caches.

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SORT VS. HASH REVISITED: FAST JOIN IMPLEMENTATION ON MODERN MULTI-CORE CPUSVLDB 2009



https://15721.courses.cs.cmu.edu/spring2019/papers/18-sortmergejoins/kim-vldb2009.pdf

https://15721.courses.cs.cmu.edu/spring2019/papers/18-sortmergejoins/kim-vldb2009.pdf

CMU 15-721 (Spring 2019)

CACHE-CONSCIOUS SORTING

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Level #1

Level #2

Level #3

SORTED

UNSORTED



CMU 15-721 (Spring 2019)

LEVEL #1 SORTING NETWORKS

Abstract model for sorting keys.→ Fixed wiring “paths” for lists with the same # of elements.→ Efficient to execute on modern CPUs because of limited

data dependencies and no branches.

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Input Output



CMU 15-721 (Spring 2019)




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CMU 15-721 (Spring 2019)




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wires = [9,5,3,6]

wires[0] = min(wires[0], wires[1])wires[1] = max(wires[0], wires[1])wires[2] = min(wires[2], wires[3])wires[3] = max(wires[2], wires[3])


wires[1] = min(wires[1], wires[2])wires[2] = max(wires[1], wires[2])



CMU 15-721 (Spring 2019)




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wires = [9,5,3,6]



wires[1] = min(wires[1], wires[2])wires[2] = max(wires[1], wires[2])

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CMU 15-721 (Spring 2019)


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12 21 4 13

9 8 6 7

1 14 3 0

5 11 15 10

Instructions:→ 4 LOAD



CMU 15-721 (Spring 2019)


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12 21 4 13

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1 14 3 0

5 11 15 10

Sort Across Registers




CMU 15-721 (Spring 2019)


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1 8 3 0

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12 21 15 13



Instructions:→ 10 MIN/MAX



CMU 15-721 (Spring 2019)


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12 21 4 13

9 8 6 7

1 14 3 0

5 11 15 10

1 8 3 0

5 11 4 7

9 14 6 10

12 21 15 13

1 5 9 12

8 11 14 21

3 4 6 15

0 7 10 13


Transpose Registers


Instructions:→ 10 MIN/MAX

Instructions:→ 8 SHUFFLE→ 4 STORE



CMU 15-721 (Spring 2019)

LEVEL #2 BITONIC MERGE NETWORK

Like a Sorting Network but it can merge two locally-sorted lists into a globally-sorted list.

Can expand network to merge progressively larger lists (½ cache size).

Intel’s Measurements→ 2.25–3.5x speed-up over SISD implementation.

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EFFICIENT IMPLEMENTATION OF SORTING ON MULTI-COREVLDB 2008



http://www.vldb.org/pvldb/1/1454171.pdf

http://www.vldb.org/pvldb/1/1454171.pdf

CMU 15-721 (Spring 2019)

LEVEL #2 BITONIC MERGE NETWORK

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Input Output

b4

b3

b2

b1

Sorted Run

Reverse Sorted Run

a1

a2

a3

a4

S

H

U

F

F

L

E

S

H

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E

Sorted Run

min/max min/max min/max



CMU 15-721 (Spring 2019)

LEVEL #3 MULTI-WAY MERGING

Use the Bitonic Merge Networks but split the process up into tasks.→ Still one worker thread per core.→ Link together tasks with a cache-sized FIFO queue.

A task blocks when either its input queue is empty or its output queue is full.

Requires more CPU instructions, but brings bandwidth and compute into balance.

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CMU 15-721 (Spring 2019)

Sorted Runs

LEVEL #3 MULTI-WAY MERGING

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MERGE

MERGE

MERGE

MERGE

MERGE

MERGE

MERGE

Cache-Sized Queue



CMU 15-721 (Spring 2019)

MERGE PHASE

Iterate through the outer table and inner table in lockstep and compare join keys.

May need to backtrack if there are duplicates.

Can be done in parallel at the different cores without synchronization if there are separate output buffers.

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CMU 15-721 (Spring 2019)

SORT-MERGE JOIN VARIANTS

Multi-Way Sort-Merge (M-WAY)

Multi-Pass Sort-Merge (M-PASS)

Massively Parallel Sort-Merge (MPSM)

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CMU 15-721 (Spring 2019)

MULTI-WAY SORT-MERGE

Outer Table→ Each core sorts in parallel on local data (levels #1/#2).→ Redistribute sorted runs across cores using the multi-

way merge (level #3).

Inner Table→ Same as outer table.

Merge phase is between matching pairs of chunks of outer/inner tables at each core.

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CMU 15-721 (Spring 2019)


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Local-NUMA Partitioning



CMU 15-721 (Spring 2019)


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Local-NUMA Partitioning Sort



CMU 15-721 (Spring 2019)


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Multi-Way Merge



CMU 15-721 (Spring 2019)


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SORT!

SORT!

SORT!

SORT!


Multi-Way Merge

Same steps asOuter Table



CMU 15-721 (Spring 2019)


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SORT!

SORT!

SORT!

SORT!

⨝

⨝

⨝

⨝


Multi-Way Merge

Local Merge Join

Same steps asOuter Table



CMU 15-721 (Spring 2019)

MULTI-PASS SORT-MERGE

Outer Table→ Same level #1/#2 sorting as Multi-Way.→ But instead of redistributing, it uses a multi-pass naïve

merge on sorted runs.

Inner Table→ Same as outer table.

Merge phase is between matching pairs of chunks of outer table and inner table.

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CMU 15-721 (Spring 2019)


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CMU 15-721 (Spring 2019)


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Local-NUMA PartitioningSort



CMU 15-721 (Spring 2019)


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Global Merge Join

⨝

Local-NUMA PartitioningSort



CMU 15-721 (Spring 2019)

MASSIVELY PARALLEL SORT-MERGE

Outer Table→ Range-partition outer table and redistribute to cores.→ Each core sorts in parallel on their partitions.

Inner Table→ Not redistributed like outer table.→ Each core sorts its local data.

Merge phase is between entire sorted run of outer table and a segment of inner table.

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MASSIVELY PARALLEL SORT-MERGE JOINS IN MAIN MEMORY MULTI-CORE DATABASE SYSTEMSVLDB 2012



https://15721.courses.cs.cmu.edu/spring2019/papers/18-sortmergejoins/p1064-albutiu.pdf

https://15721.courses.cs.cmu.edu/spring2019/papers/18-sortmergejoins/p1064-albutiu.pdf

CMU 15-721 (Spring 2019)


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Cross-NUMA Partitioning



CMU 15-721 (Spring 2019)


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Cross-NUMA Partitioning Sort

Globally Sorted



CMU 15-721 (Spring 2019)


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SORT!

SORT!

SORT!

SORT!




CMU 15-721 (Spring 2019)


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SORT!

SORT!

SORT!

SORT!


Cross-Partition Merge Join



CMU 15-721 (Spring 2019)


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SORT!

SORT!

SORT!

SORT!

⨝


Cross-Partition Merge Join



CMU 15-721 (Spring 2019)

Rule #1: No random writes to non-local memory→ Chunk the data, redistribute, and then each core

sorts/works on local data.

Rule #2: Only perform sequential reads on non-local memory→ This allows the hardware prefetcher to hide remote

access latency.

Rule #3: No core should ever wait for another→ Avoid fine-grained latching or sync barriers.

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Source: Martina-Cezara Albutiu



http://15721.courses.cs.cmu.edu/spring2016/papers/p1064-albutiu.pdf

CMU 15-721 (Spring 2019)

EVALUATION

Compare the different join algorithms using a synthetic data set.→ Sort-Merge: M-WAY, M-PASS, MPSM→ Hash: Radix Partitioning

Hardware:→ 4 Socket Intel Xeon E4640 @ 2.4GHz→ 8 Cores with 2 Threads Per Core→ 512 GB of DRAM

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CMU 15-721 (Spring 2019)

RAW SORTING PERFORMANCE

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1 2 4 8 16 32 64 128 256Thr

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put (

M T

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Number of Tuples (in 220)

C++ STL Sort SIMD Sort

Source: Cagri Balkesen

Single-threaded sorting performance

2.5–3x Faster



https://www.inf.ethz.ch/personal/cagri.balkesen/

CMU 15-721 (Spring 2019)

COMPARISON OF SORT-MERGE JOINS

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Partition Sort S-Merge M-Join Throughput

13.6


Workload: 1.6B⋈ 128M (8-byte tuples)

7.6

22.9




CMU 15-721 (Spring 2019)

Hyper-Threading

M-WAY JOIN VS. MPSM JOIN

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Multi-Way Massively Parallel

108 M/sec

315 M/sec


Workload: 1.6B⋈ 128M (8-byte tuples)

130 M/sec

54 M/sec

259 M/sec

90 M/sec




CMU 15-721 (Spring 2019)

SORT-MERGE JOIN VS. HASH JOIN

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SORT HASH SORT HASH SORT HASH SORT HASH

128M⨝128M 1.6B⨝1.6B 128M⨝512M 1.6B⨝6.4B

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Partition Sort S-Merge M-Join Build+Probe


Workload: Different Table Sizes (8-byte tuples)




CMU 15-721 (Spring 2019)

SORT-MERGE JOIN VS. HASH JOIN

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Millions of Tuples

Multi-Way Sort-Merge Join Radix Hash Join


Varying the size of the input relations




CMU 15-721 (Spring 2019)

PARTING THOUGHTS

Both join approaches are equally important.

Every serious OLAP DBMS supports both.

We did not consider the impact of queries where the output needs to be sorted.

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CMU 15-721 (Spring 2019)

NEXT CL ASS

Query Compilation→ Or "Why is DSL Project is Awesome"

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18 advanced database systems - cmu 15-721

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