16_pll johns & martin slides

8/13/2019 16_pll Johns & Martin Slides

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University of Toronto 1 of 26 D. Johns, K. Martin, 1997

Phase-Locked Loops

David Johns, Ken MartinUniversity of Toronto


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Common PLL Applications Clock multiplier

- input is a fixed frequency clock - output is a higher frequency clock signal that is amultiple of input clock frequency

Frequency synthesizer- input is a fixed frequency clock - output is a clock signal with arbitrary frequency

Clock and data recovery- input is a data signal (from a serial link)- output is digital data as well as clock signal- phase detector is different than other applications

FM demodulation- input is a radio signal- output is demodulated signal


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Example Waveforms

(3)

(4)

Above shows an example of (slightly less)

0 2 4 6 8 10 12 14 16 18 201

0.8

0.6

0.4

0.2

0

0.2

0.4

0.6

0.8

1

V pd

VoscVin

V in E in t ( )sin=

V osc

E osc

t d

90 +( )sin E osc

t d

( )cos= =

d 90


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PLL Basics Can show

(5)

The lowpass filter removes second term and for small...

(6)

where we define

(7)

V pd K M E in E osc

2------------------- d( )sin 2 t d ( )sin+[ ]=

d

V cntl K lp K M E in E osc

2------------------- d K lp K pd d =

K pd K M E in E osc

2-------------------=


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PLL Basics Oscillator frequency given by

(8)

is the free running freq of oscillator is the VCO gain constant

Feedback forces to equal

However, if does not equal , and loop filter does NOT have infinite gain at dc, then phase difference whenin lock given by:

(9)

osc K osc V cntl fr +=

fr K osc

osc in

in fr

d V cntl

K lp K pd ------------------ in fr

K lp K pd K osc------------------------------= =


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PLL Linear Model

(10)

(11)

in s( )

osc s( ) 1 s

KlpHlp s( )

Kpd

Kosc

Vcntl

V cntl s( ) K pd K lp H lp s( ) in s( ) osc s( ) [ ]=

osc

s( ) K osc V cntl s( )

s------------------------------=


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PLL Equations Combining above 2 equations ...

(12)

This is a highpass response from input phase to controlvoltage

Can also be written as

(13)

This is a lowpass response from input phase to output phase

V cntl s( )

in s( )-------------------

sK pd K lp H lp s( )

s K pd K lp K osc H lp s( )+------------------------------------------------------=

osc s( )

in s( )-----------------

K pd K lp K osc H lp s( )

s K pd K lp K osc H lp s( )+-----------------------------------------------------=


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Charge Pump PLL

Sequential

phase detector

Vin

Vosc

Pu

Pd

IchS1

S2 C1

R C2

Low-pass filter Charge-pump phase comparator

Ich

Vlp

(de-glitching cap)


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Sequential Phase Detector

If leads , (pulse up) goes high for lead time

If leads , (pulse down) goes high for lead time.

Vin

Vosc

Pu

Pd

2

in

Time

V in V osc P u

V osc V in P d


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Charge Pump PLL Equations Average current flowing into lowpass filter is ...

(14)

Lowpass filter is (ignoring )...

(15)

which results in

(16)

avg

in2

----------- Ich=

C 2

lp s( )V lp s( )

Iavg

s( )----------------- R 1

sC 1

---------+1 sRC 1+

sC 1

----------------------= = =

osc s( )

in s( )-----------------

1 sRC 1+( )

1 sRC 1 s 2C 1

K pd K osc---------------------+ +

--------------------------------------------------=


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Charge Pump PLL Equations The phase transfer curve is second-order (ignores de-

glitching cap ) so and can be found as

(17)

(18)

C 2 0 Q

01

pll --------

I ch K osc2 C 1

------------------= =

Q 1 RC 1 0----------------- 1

R--- 2

C 1 Ich K osc--------------------------= =


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Charge Pump Example Let and .

. Desired loop time constant of100 cycles, or . Find loop filter components.

SOLUTION

(19)

(20)

Let and

(21)

Kosc 2 50 M rad V = Ich 10 A=

fr 2 50 M rad s =

2 s

01

2 s----------- 500 krad s = =

C 11

02

------Ich2------ K osc 2 nF= =

C 2 C 1 10 2.5 pF= = Q 0.4=

R 1Q---- 2

C 1Ich K osc-------------------------- 31.4 k = =


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Phase Frequency Detector

Can be used for sequential phase detector but also works

when large frequency differences between osc freq andinput freq

Pd

FF2

FF4

Vosc

Pd-dsbl

Reset

FF3

FF1

Pu-dsbl

Vin

Pu

Set 1 Set 2

Set 4Set 3


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Phase Frequency Detector

Above example is for osc freq much lower than input freq

Note that is high much longer than

Vin

Vosc

Pu

Pd

Pu-dsbl

Pd-dsbl

P u P d


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Oscillators

Two main classes of oscillators

Most common are LC osc and Ring osc (Crystal osc isgood but difficult to tune away from center freq)

Oscillators

Tuned oscillators Nonlinear oscillators

RC

osc.

SC

osc.

LC

osc.

Crystal

osc.

Relaxation

osc.

Ring

osc.


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Ring Oscillators

(22)

where is delay of each inverter

Vout

Vout (quadrature)

osc 1T --- 12n inv---------------= =

inv


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Fully Differential Delay Stage

IBVcntl

Vout Vout

+

Vin+ Vin

IB

V biasl

Q1 Q2

Q3 Q4

2IBVcntl


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V2I Conversion

+

IVcntl

R------------=

Vcntl

V bias

R

Control circuitryFirst inverter of ring oscillator

I

To other

oscillators

I

Q7

Q9

Q3

Q2

Q4

Q1

Q5 Q6Q8

2I


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Alternative Biasing

Vcntl

Vref

Vref

Bias stage Delay stage

To other stages

From other stages

Q2Q1

Q4

Q3

R 3 R 4 R 1R 2

I b I b


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Computer Simulation of PLLs Simulation times can be very long due to large variations

in time-constants

Make use of bilinear transform to simulate analog signals

in discrete timesteps. Loop Filter example

Impedance looking into loop filter is ... ( )

(23)

So voltage to charge relationship is ...

(24)

G 1 R =

Z lp s( ) 1 sC 1--------- 1 sC 2 G+

--------------------+=

V lp s( )Q lp s( )---------------- G s C 1 C 2+( )+

GC 1 sC 1C 2+--------------------------------------=


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Discrete-time loop filter Use bilinear transform

(25)

giving

(26)

which can be written as

s 2T --- 1 z

1 1 z 1 +-----------------

M z ( )V lp z ( )

Q lp z ( )---------------

2 1 z 1 ( ) C 1 C 2+( ) GT 1 z 1 +( )+

2C 1

C 2

1 z 1 ( ) C 1

GT 1 z 1 +( )+--------------------------------------------------------------------------------------= =


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(27)

where

(28)

(29)

(30)

(31)

P z ( )

V lp z ( )

Q lp z ( )-------------------

m1 m2 z 1 +

1 z 1 k 2 ( ) z 2 1 k ( )+ +-----------------------------------------------------------------= =

11 z 1 ---------------- m1 m2 z

1 +

1 z 1 kz 1 + ---------------------------------

=

k 2GC 1T

D------------------=

m12 C 1 C 2+( ) GT +

D------------------------------------------=

m22 C 1 C 2+( ) GT +

D----------------------------------------------=

D 2C 1C 2 GC 1T +=


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Discrete-time Loop Filter

Can use Matlab, Simulink, C, etc to simulate

z 1

k

X2(z)

m2

m1

Vlp(z)

z 1

X1(z)

Q(z)


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A Fractional-N Frequency Synthesizer

Use oversampling within a PLL f xt M -----

phasedetect

loopfilter VCO

N

M crystal

osc

f xt

Nf xt PM ----------

N k-1 k k+1, ,{ }= A digital controlled oscillator

P

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