Faculty of Engineering Sciences Department of Electrical and Computer Engineering

Advanced Micro-Computers Laboratory

16 bit Calculator with Altera FPGA, LCD & Keyboard:By Noam Avital Yaniv Tsabari Gil Botton Advanced micro lab instructor: Mr. Alex Reizenson

2

nd

Semester 2004

Table of contents:

Chapter 1 The Combined System1.1 Projects overview 1.2 Project's blocks diagram

Chapter 2 The Keypad2.1. Introduction 2.2. Module ports 2.2.1. Module inputs 2.2.2 Module outputs 2.3. Lower hierarchy modules 2.4. Interrupt request (IRQ) 2.5. Enables

Chapter 3 THE ALUThe ALU - Introduction 3.1 ALU module 3.2

Chapter 4 The LCD DisplayThe LCD 4.1 LCD module 4.2

Initializing the LCD 4.2.1 4.2.2 Data from Keyboard to the LCD 4.2.3 Data from ALU to the LCD

Chapter 1 The Combined System1.1 Projects overviewWe designed calculator for 16 bits integers that can calculate adding, subtraction, dividing and multiply. The calculator is billet from 3 main modules: 1) PAD pad interface for user to enter calculator numbers and mathematical operations. 2) ALU the core of the calculator. Calculates mathematical operations that user feed him from PAD module and send result to LCD module. 3) LCD interface to display calculator actions and results.

All the modules are programmed on ALTERA flex10k card in VERILOG. The picture below shows the different parts of the project.

LCD

ALTERA Flex10k

1.2 Project's blocks diagram

PAD

Z

padQ

4

4 8

LCDout

PAD Module

NOT_IRQ

16

Num5

op

update_result

ALU Module

ALUout

LCD Module

32 reset 8

DB

RS

E

R_W

Chapter 2 The Keypad2.1. IntroductionIn this project we use the 4x4 keypad. the keypad was designed to get the numbers and operations from the user, encoding them for the LCD display, and accumulating them into the final number that the user want to operate with (in a case of more than one digit). Except of that, the keypad module is responsible for creating the interrupt request for the other modules (ALU, LCD) while a key is pressed.

Under the integration plan we made, the Keypad module had to submit a steady LCD decoded number or operation as it pressed, and a steady data of the number coded in binary form, stored in a register for the ALU use. For acknowledgment of the ALU that a number is ready for use, there is an OP (operation) register that his outputs represent the chosen operation of the user. Those OP outputs activate the ALU.

2.2. Module portsThe keypad module is the primary module at the process of calculating. This module contains outputs to the two other modules (ALU, LCD) and inputs from the keypad and internal clock produced from the ALTERA device. 2.2.1. Module inputs clk internal clock produced by the ALTERA device at frequency of 27.125 MHz. padQ [3:0] these are the outputs of the keypad that goes into the module and show us in which row a button is pressed. reset initial the system by a button on the ALTERA device. 2.2.2 Module outputs Zshifter [3:0] this module is a lower hirarchy of the pad_encoder module. It is a shift register that produce a zero that is shifted cyclic on 4 bits. LCDout [7:0] the coded outputs of the pad_encoder is driven directly to the LCD and ready for display. OP [5:0] these outputs are an interrupt signal for the ALU. These signals are produced when an operation was requested by the user. OP[0] multiply OP[1] divide OP[2] add OP[3] subtract OP[4] result OP[5] reset A [15:0] number after accumulating into the final number, ready for the ALU

Operation. IRQ an interrupt that is produced when a key is pressed on the keypad. used by the LCD module.

Pad modules diagram:

2.3. Lower hierarchy modulesPad encoder responsible for the decision which key was pressed and encoding it to the LCD, OP and Accumulator. A combination of '0' at one of the padQ inputs and '0' under the key pressed produces a signal for each key. ZERO shifter 4 bit shift register. Implemented by a state machine. OP produces interrupts for the ALU. Each signal represent an operation. Accumulator accumulate the numbers pressed into the final number for the ALU usage.

2.4. Interrupt request (IRQ)

The interrupt is produced as long as a key is pressed. The difficulty was that the padQ signal is going to '0' for one clock period, every 4 clock cycles. The pressing period is much longer than a clock period and thats causes hundreds of seemingly pressings. The solution implemented by using a counter that counts 4 clock periods, and than checks if the key is still pressed. Floating diagram: For each clockif reset was pressed

no if all padQ inputs are '0' and IRQ = '0'

yes if IRQ = '0' and conter = '000'

no

yes

if IRQ = '1'

IRQ = '1' incline counter

no

yes if conter =4 and one of the padQ inputs is '0'

remain at the same state

no

yes

if counter = 4 and all padQ inputs are '1'no yes

counter = 1

incline counter

initial counter and initial counter

2.5. EnablesThis logical description is the positive edge detector on the IRQ signal. It produces different Enables to the different modules. The Accumulator is enabled by 'dly1' and OP is enabled by 'dly2'.

Accumulator En(1)

OP En(2)

IRQ

reg1

reg2

dly1

dly2

clk

clk

clk

clk

Chapter 3 THE ALUThe ALU - Introduction 3.1In the project we use ALU module in order to calculate summing, subtraction, dividing and multiply on integers. Each input number is 16 bits long and the result is 32 bits long. The result is also integer.

Pin no. 1 - 16 17 18 19 20 21 22 23 24 25 - 56

Signal Input 16 bits integer input from PAD module. equal 1 bit signal from PAD module. ADD 1 bit signal from PAD module. MUL 1 bit signal from PAD module. SUB 1 bit signal from PAD module. DIV 1 bit signal from PAD module. CLK 1 bit clock signal from. Reset 1 bit hardware reset. IRQ 1 bit signal, when high signals to LCD module that Result is ready. Result 32 bits holding result of ALU.

ALU module

3.2

The ALU module has two, 16 bits, registers to hold input numbers from PAD module. When one of the signals ADD, MUL, SUB or DIV is detected high, the first input number .is stored and the action request is stored in one bit register When equal request is detected high, the second input number is stored and after one clock delay the result is stored in result register. One clock cycle after result is stored IRQ signal is posted high for two clock cycles to notify LCD module that the result is .ready to display

Chapter 4 The LCD DisplayThe LCD 4.1In the project we use LCD 2X16 PC1602ARS-PSO, the LCD have two rows and 16 characters in each row. In the next table there is a configuration of the LCD: Pin no. 1 2 3 4 Signal VDD (+5V) VSS (GND) VO - input - intensity of the LCD. Optimum value - 0.5 volt input. RS - address input. Usually connected to AD0. RS= 0 - command reg. RS=1 - data reg. 5 6 7 8 9 10 11 12 13 14 R/W - read write input signal. Read active high. E - chip select high active. DB0 - least significant bit data DB1 - data DB2 - data DB3 - data DB4 - data DB5 - data DB6 - data DB7 - most significant bit data

The first row located in the address 80h-8Fh. The second row is in the address C0h-CFh. Move to specific address by writing the address into command register (RS = 0). In the LCD are two registers: command reg. (RS = 0) and data register (RS = 1).

LCD module

4.2

The LCD module builds from three parts: Initializing, Data from Keyboard and Data from ALU. The all three parts are in the same module and selected by Reset or IRQ .request

4.2.1 Initializing the LCD:The LCD display setting, which are being set at Reset pressed: 8 bit 2 lines 5*7 dots per digit Cursor off blink on Entry mode Increment cursor without display shift .As well, clearing the screen and go back to home position :The Sequence of Initializing 1) Insert 38h into command register four times with interval delay of 4.1 msec at least. 2) Insert following data instructions into command register with interval delay of 1.64 msec minimum: 08h - sets off all display and the cursor. 01h - clear all display. 06h - sets right cursor move direction without shift the display. 0fh - sets on all display, the cursor and blink of cursor positions character. 02h - return the cursor to the home position. All delays in the sequence control by the chip select pin (E), that high active for at list 2 sec and low active for the delay time. In the Sequence of Initializing we are writing to control register there for the address input pin is low active (RS = 0). The Sequence of Initializing is write in a state machine to make the delays of the chip select and change the data to the control register.

4.2.2 Data from Keyboard to the LCD:The data from the keyboard module is decoded when it arrives to the LCD module and the IRQ key is low active when a key is pressed. The LCD module check if Enter was pressed, if he was pressed it write to the LCD "=" and write to the control register to go to second row (C0h). If the enter was pressed the next time that another key will pressed the LCD will restart and will write the key that pressed.

4.2.3 Data from ALU to the LCD:The data from the ALU module is not decoded it arrives in binary number and needed to convert it to BCD numbers, when it arrives to the LCD module and the IRQ ALU is high active when the ALU module finish his calculation. After the Conversion to BCD the digit the digit is writing to the LCD in delay of 200 sec. The Binary to BCD Converter: We can calculate up to 16 bit numbers there for the result can be up to 32bit numbers, Then we use 32 bit Binary to BCD converter. We use Shift and Add-3 Algorithm: 1. Shift the binary number left one bit. 2. If 8 shifts have taken place, the BCD number is in the Hundreds, Tens, and Units column. 3. If the binary value in any of the BCD columns is 5 or greater, add 3 to that value in that BCD column. 4. Go to 1.

Example: Convert hex E to BCD

Pins assignmentPin Name Pin Number clk. 91 reset ..29 Z[0].................................................................................................................................. 83 Z[1].. 84 Z[2].. 86 Z[3]...87 padQ[3]....88 padQ[2]... 94 padQ[1]... 95 padQ[0]... 97 DB[0].. 219 DB[1] . 220 DB[2] . 221 DB[3].. 222 DB[4] ..223 DB[5].. 225 DB[6] ..226 DB[7]...227 E ..228 RS 229 R_W .230

The project contains 8 verilog files with the hierarchy shown below: CalcNew.v LCD.v newALU.v PAD.v Accumulator.v Pad_encoder.v Z_shifter.v OP_interupt.v