1.2 - digital logic

S02 - Digital Logic

Required: PM: Ch 2, pgs 5-25Code: Chs 10-16Wiki: Finite State Machine

Recommended: Transistors and FaucetsGates, Tables, ExpressionsCombinational LogicSequential Logic

http://en.wikipedia.org/wiki/Finite-state_machine



http://drstienecker.com/tech-332/3-logic-circuits-boolean-algebra-and-truth-tables/

http://drstienecker.com/tech-332/3-logic-circuits-boolean-algebra-and-truth-tables/

http://www.play-hookey.com/digital/combinational/

http://www.play-hookey.com/digital/combinational/

http://www.play-hookey.com/digital/sequential/

http://www.play-hookey.com/digital/sequential/

BYU CS 224 S02 - Digital Logic 2

CS 224Chapter Lab Homework

S00: IntroductionUnit 1: Digital Logic

S01: Data TypesS02: Digital Logic

L01: Data TypesL02: FSM

HW01HW02

Unit 2: ISAS03: ISAS04: MicroarchitectureS05: Stacks / InterruptsS06: Assembly

L03: BlinkyL04: MicroarchL05b: Traffic LightL06a: Morse Code

HW03HW04HW05HW06

Unit 3: CS07: C LanguageS08: PointersS09: StructsS10: ThreadsS11: I/O

L07b: Morse IIL08a: LifeL09b: SnakeL10a: Threads

HW07HW08HW09HW10

Learning Outcomes…

Learning OutcomesAfter completing this section, students will be able to: Use transistors to create an invertor, OR, and/or

AND gate. Convert a logical equation to a truth table or

digital gates. Convert a truth table to digital gates or a logical

equation. Convert digital gates to a logical equation or a

truth table Use combinational logic to create any logical

device (logical completeness). Create computer memory using sequential logic. Use a finite state machine in a practical

application.


Topics Logical and Arithmetic Operations Digital Logic Devices

The Transistor Devices: Inverter, NAND,

NOR, Drivers Gates, Truth Tables, and Equations

Equations De Morgan’s Law Translations Boolean Algebra

Combinational Logic devices Decodes, Multiplexors,

Adders, PLAs Logical Completeness

Sequential Logic Latches Memory

Finite State Machine Turing Machine

S02 - Digital Logic 4BYU CS 224

Problem Solving w/ComputersSolving Problems

Wordprocessing…Games…Surfing the web…

101011011…

Devices

Logic/Circuit Design:gates and low-level circuits to implement components

Logical and Arithmetic Operations


Logical Operations

NOT – Logical complement OR, NOR – Logical disjunction AND, NAND – Logical conjunction XOR – Exclusive OR, A OR B, but not both

Logical Operations

A B NOT A A OR B A NOR B A AND B A NAND B A XOR B

0011

0101

1100

0111

1000

0001

1110

0110

1010 10101010OR 0111 AND 0111 XOR0111

1111 00101101

Bitwise:

Exercise 2.11. What are the results of the following 4-bit logical

operations?NOT 10112

10012 OR 10112

10012 NOR 10112

10012 AND 10112

10012 NAND 10112

10012 XOR 10112

2. What are the results of the following 4-bit arithmetic operations (2’s complement)?

NEG 10112

10012 ADD 10112

10012 SUB 10112BYU CS 224 S02 - Digital Logic 7

Logical/Arithmetic Operations

The Transistor


Semiconductors A semiconductor is a material which has electrical

conductivity properties of a metal (such as copper) and that of an insulator (such as glass).

Semiconductors are the foundation of modern solid state electronics.

The Transistor


History of the Transistor Around 1945, Bell Labs scientists discovered that silicon

was comprised of two distinct regions differentiated by the way in which they favored current flow.

The area that favored positive current flow they named "p" and the area that favored negative current flow they named "n".

The transistor effect describes the change from a condition of conductivity (switched “on”, full current flow) to a condition of insulation (switched “off”, no current flow).

The Transistor


Digital Logic Circuits Computers = large number of simple structures Intel 4004 = 2,300 transistors Intel Pentium 4 = 42 million transistors Intel Core 2 Duo = 291 million transistors Intel i7 “Bloomfield” = 731 million transistors

The Transistor

S02 - Digital Logiccurrent flow

gate

N-type Transistor

12

The MOS Transistor A transistor acts like a switch

Conducts current when "ON" No current flow when "OFF"

MOS = metal-oxide semiconductorCMOS = complementary MOS with both N and P transistors

The Transistor

Complementary

Gate(input)

FET(output)

GND (0) Open

Vcc (3.3v) Closed

Gate(input)

FET(output)

GND (0) ClosedVcc (3.3v) Open

current flow

gate

P-type Transistor

BYU CS 224 12

S02 - Digital Logic

Output

13

CMOS Gates

Pull-up Structure(P-Type)

Pull-down Structure(N-Type)

Complementary

The “C” in CMOS

Even in the digital world,"EVERYTHING IS ANALOG"!

The Transistor

1

0

Complementary pull-up / pull-down logic pull-down is " ON" when pull-up is "OFF " and vise versa.

BYU CS 224 13


The Inverter

in

1

0

out 0

1

0

1

on

off

1

1

0

0on

off

Truth-table lists outputfor all possible inputs.

Symbols are abstractions!

Digital Logic Devices

In out0 11 0

3.3v relativeto ground.

S02 - Digital Logic 15

The NOR Gate (NOT-OR)

a

b

1

0 0

NOR


on

off off

on

1

0

0

1

0 0

off

off

on

on

0

a

b

1

0 0

a b NOR0 0 10 1 01 0 01 1 0

BYU CS 224 15


The OR GateDigital Logic Devices

a b OR0 0 00 1 11 0 11 1 1

How do you build an OR gate?

a

b

1

0 0

a

bOR

1

0

OR

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The NAND Gate (NOT-AND)

on

off off

on

1

1

0

1 1

0

1

0

1

1 1

0

off

off

on

on

b

a

1 1

0

NAND


a b NAND0 0 10 1 11 0 11 1 0


The AND Gate

How do you build an AND gate?


b

a

AND ANDa

b

a b AND0 0 00 1 01 0 01 1 1

BYU CS 224 18


Drivers Why can’t complementary logic connect to a bus?


Bus

A 0 and a 1 on the bus would let the magic smoke out! Solution: Tri-state driver:

BYU CS 224 19

BusPull-up

+3.3vAll OFF 1Any ON 0

Input Output

Select

Exercise 2.2



What is the output of the following logic circuit if a=0, b=1, c=0?

Draw the corresponding symbol.

S02 - Digital Logic 21BYU CS 224

Problem Solving w/ComputersSolving Problems

DevicesProcess Engineering & Fabrication:develop and manufacture lowest-level components

Logic/Circuit Design:gates and low-level circuits to implement components

Circuits

Wordprocessing…Games…Surfing the web…

101011011…

Gates, Truth Tables, and Equations



Notation and Precedence Logical operator notation (in order of precedence):

NOT, bar, circle, ~, ¬ AND, *, , OR, +,

Examples:

sbasout

BABA

y = NOT(s) AND a AND NOT(b)

y = (~s a ~b) + (~s a b)

Equations

¬(x y) = ¬x ¬y


De Morgan’s Law

BABA

BABA

To distribute the bar, change the operation.

NOR Symbols

De Morgan’s Law

NAND SymbolsBYU CS 224 24


You Should Know How to Translate

LogicEquations

LogicGates

TruthTables

These are three different ways of representing logical information

You can convert any one of them

to any other

Translations


Equations to Gates/Truth TablesTranslations

sabbasabsbasout

out

sab

sab

sab

sab

s a b out0 0 0 00 0 1 00 1 0 10 1 1 11 0 0 01 0 1 11 1 0 01 1 1 1

Gates to Truth Tables/Equations


(NOT(A) AND B) OR (A AND NOT(B))

Translations

A B AB0 0 00 1 11 0 11 1 0

Truth Tables to Gates/Equations


C = (~A × S × B) + (A × ~S × ~B) + (A × ~S × B) + (A × S × B)

A S B C 0 0 0 00 0 1 00 1 0 00 1 1 11 0 0 11 0 1 11 1 0 01 1 1 1

Translations


Laws (basic identities) of Boolean algebra.

Law OR ANDIdentity x 0 = x x 1 = x

One/Zero x 1 = 1 x 0 = 0

Idempotent x x = x x x = x

Inverse x ¬x = 1 x ¬x = 0

Commutative x y = y x x y = y x

Associative (x y) z = x (y z) (x y) z = x (y z)

Distributive x (y z) = (x y) (x z) x (y z) = (x y) (x z)

DeMorgan’s ¬(x y) = ¬x ¬y ¬(x y) = ¬x ¬y

Manipulating Logic ExpressionsBoolean Algebra


Exercise 2.3

What is the logical equation and truth table for the following circuit?

Quiz

BYU CS 224 30


CMOSReview

NOT

in out0 11 0

NAND

b

a

a b NAND0 0 10 1 11 0 11 1 0

a

bNOR

a b NOR0 0 10 1 01 0 01 1 0

BYU CS 224 31

in sel out 0 0 - 0 1 0 1 0 - 1 1 -

SelectInput

OUT

Combinational Logic Devices


Decoders Decode the input and signify its

value by raising just one of its outputs.

2-to-4Decoder

A B

WXYZ

DECODERSymbol1 if A,B = 00

1 if A,B = 01

1 if A,B = 10

1 if A,B = 11

W

X

Y

Z

AB

Circuits

A B W X Y Z0 0 0 1 1 0 1 1

1 0 0 00 1 0 00 0 1 00 0 0 1

10

0

0

1

0

0

Connect one of its inputs to its output according to select signals

Useful for selecting one from a collection of data inputs.

Usually has 2n inputs and n select lines.

1


MultiplexorsA B

S

C

0 1

MULTIPLEXOR Symbol

A BS

C

Circuits

A B S C0 - 0 01 - 0 1- 0 1 0- 1 1 1

1 1


Adders

At each digit position add together the 2 operands and the carry-in

FullAdder

a0b0

s0

c0Full

Adder

a1b1

s1

c1Full

Adder

a2b2

s2

c2Full

Adder

a3b3

s3

c3‘0’

Just like longhand additionexcept it’s in binary...

c 0110+0101 1011

Circuits


Full Adder Module Design

a b c cyout sum0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1

cbaabccbacbacbasum

abccabcbabcacyout

Circuits


Programmable Logic Arrays Programmable Logic Array

(PLA) can be used to implement any logic function

?

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?

??

?

??

?

??

?

?

?

?

?

?

?

?

?

?

?

?

?In

puts

:

Outp

uts:

PLAs

Take truth table of any logic function

Convert into equation (any truth table can be expressed as set of “and” expressions “or”ed together)

PLA programmed by making/breaking wire connections


PLA Example

A B C Out1 Out2 Out30 0 0 0 1 10 0 1 1 0 00 1 0 0 1 00 1 1 0 0 01 0 0 1 0 01 0 1 0 1 01 1 0 0 0 01 1 1 1 0 1

Out1 = ABC + ABC + ABCOut2 = ABC + ABC + ABCOut3 = ABC + ABC

Inputs

Outputs

?

?

?

?

?

?

??

?

??

?

??

?

?

?

?

?

?

?

?

?

?

?

?

?ABC

Out1Out2Out3

PLAs


Exercise 2.4 Implement a half adder using a PLA

PLAs

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?

?

?

?

?

?

?

?

?

?

?abc ?

?

?

?

?

?

??

?

?

sum

sum = abc + abc + abc + abc = a b c

Digital Components


CMOS Gates

Representing Logical Expressions

Combinational Circuits

Review

Sequential Logic


Storage Elements Everything so far has been combinational logic

the output is strictly a function of the current inputs Computing systems need storage elements

for holding previously computed values for saving state

Two types of locks:

Sequential Logic

4 1 8 4

Combinational – Success depends only on the values, not the order in which they are set.

30

15

5

1020

25

Sequential - Success depends on the sequence of values (e.g, R-13, L-22, R-3).

BYU CS 224 42


Bi-Stability = Key to Memory When there are 2 stable states - a bi-stable circuit

RS Latch

Sequential Logic

0 11This is also a stable state –it will sit like this forever

1 00This is a stable state –it will sit like this forever

q

q

s

r

q

q

s

r

1

1

0

1

1

1

1

0

BYU CS 224 43


RS Latch – Bi-Stable CircuitSequential Logic

0

1

1

0

1

0

0

1

1

1

0

1

q

q

s

r

1 1

1 0

This is also a stable state –it will sit like this forever

q

q

s

r

This is a stable state –it will sit like this forever

1 0

1 1

1

1

0

1

1

1

1

0


Gated D Latch Output q gets value from input d only when we is

high we stands for write enable, think of it as a load signal

s

r

q

q

d

we

LATCH Symbol

WE

D QD-Latch

Symbols are abstractions!

Latch


Register

A computer register is a place to store a collection of bits

Very fast memory Numbered right to left (LSB on the right)

D-Latch

d0

q0

D-Latch

d1

q1

D-Latch

d2

q2

D-Latch

d3

q3

we

REGISTER Symbol

Register

d

q

we

Latch


Memory

A collection of addressable locations Address selects which location to read from

or write to

Memory

address

q

n

we

dm m

A memory with n address wires has 2n locations.

The number of data wires in is equal the number of data wires out.

Memory is changed when we is asserted.

q always reflects the contents stored at the addressed memory location.

Memory can be viewed as a large collection of slower registers.

Memory


Building a Memory From Latches

2-to-4Decoder

a1 a0

00

01

10

11

Register

Register

Register

Register

we

we

we

we

writeEnable d input

q output

This is a functional view.The key parts are: address decoder memory cells (registers) output selector (mux)

Memory

address

q

n

we

dm m

MEMORY Symbol

n = 2address

q0

q1

q2

q3

Memory

Exercise 2.5


Latch

D CLK S R Q Q1 0 01 10 00 10 0

Fill in the values of S, R, Q, and Q as D and CLK change.

Finite State Machine


Computing Devices Alan Turing

In 1936 he proposed a way to define the term “computable”

The Turing Machine Basic abstract symbol-manipulating devices

which can be adapted to simulate the logic of any computer algorithm.

Anything that can be computed,can be computed by a TM…

The TM is not a real machine,but an abstract machine

Turing Machine


Turing Machine DetailsTuring Machine


Turing Machine Example

Old Read Write NewState Sym Sym Move StateS1 1 0 R S2S2 1 1 R S2S2 0 0 R S3S3 0 1 L S4S3 1 1 R S3S4 1 1 L S4S4 0 0 L S5S5 1 1 L S5S5 0 1 R S1

Step State Tape 1 S1 …11000…

“Action Table”Start State

(State Register)

Tape Read Head

2 S2 …01000… 3 S2 …01000… 4 S3 …01000… 5 S4 …01010… 6 S5 …01010… 7 S5 …01010… 8 S1 …11010… 9 S2 …10010… 10 S3 …10010… 11 S3 …10010… 12 S4 …10011… 13 S4 …10011… 14 S5 …10011… 15 S1 …11011… --HALT--

Turing Machine


Sequential State Machine

Another type of sequential circuit Combines combinational logic with storage “Remembers” state, and changes output (and state)

based on inputs and current state

State Machine

CombinationalLogic Circuit

StorageElements

Inputs Outputs



State of a System

The state of a system is a snapshot of all the relevant elements of the system at the moment the snapshot is taken.

Examples: The state of a basketball game can be represented by

the scoreboard (ie. number of points, time remaining, possession, etc.)

The state of a tic-tac-toe game can be represented by the placement of X’s and O’s on the board.



State Diagram

Our lock example has four different states, labeled A-D: A: The lock is not open, and no relevant

operations have been performed. B: The lock is not open, and the user

has completed the R-13 operation. C: The lock is not open, and the user

has completed R-13, followed by L-22. D: The lock is open.

30

15

5

1020

25

Sequential - Success depends on the sequence of values (e.g, R-13, L-22, R-3).

State Diagram shows states and actions that cause a transition between states.

Open = 0

Open = 0

Open = 0Open = 1


BYU CS 224 56


Finite State Machine A description of a system with the following components:

A finite number of states A finite number of external inputs A finite number of external outputs An explicit specification of all state transitions

Often described by a state diagram. Inputs trigger state transitions. Outputs are associated with each state (or with each transition).

Frequently, a clock circuit triggers transition from one state to the next.

At the beginning of each clock cycle, the state machine makes a transition, based on the current state and the external (or internal) inputs.


One Cycle

"1"

"0" time

BYU CS 224 57


FSM Implementation Combinational logic

Determine outputs and next state. Storage elements

Maintains state representation.

State Machine

CombinationalLogic Circuit

StorageElements

Inputs Outputs

Clock



Asleep or Awake? What is the output of this circuit?


0 or 1 ???

Awake

OutputAsleepAsleep Awake

We isolate current state from next state with a Master/Slave flip-flop. State moves thru flip-flop on each clock cycle Master captures input value when clock is LOW Slave stores Master value when clock goes HIGH

D

E

Q

Q'

D

E

Q

Q'

Clk

Master SlaveD Q

Storage: Master-Slave Flipflop



“1”“0”

time

HOLD SET/RESET

Slave Master

Captures State

Master stores input value when clock is LOW

Storage: Master-Slave Flipflop



“1”“0”

time

HOLDSET/RESET

Slave Master

Moves State to Slave

Slave stores Master value when clock goes HIGH

S02 - Digital Logic

Simple FSM Example

63


“1”“0”

time

Combinational Logic

BYU CS 224 63

S02 - Digital Logic

Simple FSM Example (Lab 2)

64


Combinational Logic

Sequential Logic

BYU CS 224 64


Storage Elements Each master-slave flip flop stores one state bit. The number of storage elements (flip flops) needed is

determined by the number of states (and the representation of each state).

Examples: Sequential lock

4 states – 2 bits Basketball scoreboard

7 bits for each score, 5 bits for minutes, 6 bits for seconds, 1 bit for possession arrow, 1 bit for half, …

Blinking traffic sign 4 states – 2 bits



1. Design a State Diagram for a blinking traffic sign as follows: Switch OFF

No lights Switch ON, repeat

No lights on 1 & 2 on 1, 2, 3, & 4 on 1, 2, 3, 4, & 5 on

Exercise 2.6Finite State Machine

1

2

34

5

2. Create truth table for all values. (X=1,2 Y=3,4 Z=5)

3. Create equations for next state and output values.



Current State Next State Lights

Sw S1 S0 S'1 S'0 X Y Z

0 --- ---

1

1

1

1

12

34

5X

Y

Z

S'1 =

S'0 =

X =

Y =

Z =



4. Implement your state machine with combinational and sequential logic.


From Logic to Data Path The data path of a computer uses logic to

process information. Combinational Logic

Decoders -- convert instructions into control signals Multiplexers -- select inputs and outputs ALU (Arithmetic and Logic Unit) -- operations on data

Sequential Logic State machine -- coordinate control signals and data

movement Registers and latches -- storage elements



MSP430 Finite State Machine

DECODE:NOCLK:MOV||EVSRCEVDST:CLK1:MOV,Rd|D,ROX=Rd|STOREEVSRC:CLK1:MOV,Rs|S,ROX=Rs|EVDSTSTORE:CLK1:MOV,Rd|ALU,RWE,RIX=Rd|FETCH...


STORE:CLK1:MOV,Rd

Current State

ALU,RWE,RIX=Rd

Action

FETCH

Next State

1.2 - digital logic

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