10/10/2008 EECS150 Lab Lecture #7 1

The Project & Digital Video

EECS150 Fall2008 - Lab Lecture #7

Arjun SinghAdopted from slides designed by Greg Gibeling and Chris Fletcher

10/10/2008 EECS150 Lab Lecture #7 2

Today Project Introduction Good Design (Part 2)

Interfaces and Handshaking Video Encoder

Digital Video ITU-R BT.601/ITU-R BT.656 Video Encoder I2C Bus More Information

10/10/2008 EECS150 Lab Lecture #7 3

The Project (1) Digital Storage Oscilloscope

Display audio as waveforms Stream audio from network audio or from a microphone

Store audio stream Playback audio stream Trigger and freeze under different conditions

Extra Credit A major part of this project Will augment checkpoints 3, 4 and 5

10/8/2004 EECS150 Lab Lecture #6 4

The Project (2)

Checkpoints Require more design work than labs

We’re not telling you exactly what to do Part of your project

Design them well Test them thoroughly! Don’t lose your code

Require more time

10/10/2008 EECS150 Lab Lecture #7 5

The Project (3) Checkpoint Roadmap

Video Encoder SDRAM in Simulation SDRAM in Hardware + SDRAM Arbiter Waveform Generator + OScope features AC97 Audio Extra Credit

Check calendar page and project spec for dates

10/10/2008 EECS150 Lab Lecture #7 6

Interfaces & Handshaking (1) Connect two modules with just wires No combinational logic Unidirectional Data-flow

Source Sink

10/10/2008 EECS150 Lab Lecture #7 7

Interfaces & Handshaking (2)

Handshaking Signals Valid (from Source) Ready (from Sink)

Don’t rely on timing assumptions

10/10/2008 EECS150 Lab Lecture #7 8

Interfaces & Handshaking (3)

Data Transfer Synchronous When Ready and Valid are both high

Checkpoint #1: Video Encoder Video Encoder

Sets up NTSC framing Blanking, SAV, EAV

Request Data & Display it

10/10/2008 EECS150 Lab Lecture #7 9

AD

V7194

Monitor

Outgoing V

ideo(S

-Video O

ut Cable)

Test ROM

Video Encoder32b N

TS

C V

ideo(N

o Blanking)

8b NT

SC

Video

(Com

plete)

Video Line &

Pair

Address

10/10/2008 EECS150 Lab Lecture #7 10

Digital Video (1) Pixel Array

A digital image is represented by a matrix of pixels which include color information.

Frames Motion is created

by flashing a series of still frames

1920

1080High-Definition Television (HDTV), 2 Mpx

1152

900Workstation, 1 Mpx

800

600PC/Mac,1‡2 Mpx

640

480Video, 300 Kpx

352

240

SIF,82 Kpx

High-Definition Television (HDTV), 1 Mpx

1280

720

10/10/2008 EECS150 Lab Lecture #7 11

Digital Video (2) Scanning

Images are generated on the screen by scanning pixel lines, left to right, top to bottom

Early CRTs required time to get from the end of a line to the beginning of the next. Therefore each line of video consists of active video portion and a horizontal blanking interval

To reduce flicker, each frame is divided into two fields: odd and even

10/10/2008 EECS150 Lab Lecture #7 12

Digital Video (3) Colors

Usually represented as red, green and blue

In the digital domain we could transmit 8bits each for RGB.

Transition from B&W Didn’t want to break old TVs Added separate color or “Chroma” signals

Y: Luma (Black and White) Cr: Chroma Red (New color signal) Cb: Chroma Blue (New color signal)

10/10/2008 EECS150 Lab Lecture #7 13

Digital Video (4) Chroma Subsampling

Human eye is sensitive to Luma more than Chroma

R0

R2

R1

R3

G0

G2

G1

G3

B0

B2

B1

B3

Y0

Y2

Y1

Y3

CB

CB

CB

CB

CR

CR

CR

CR

Y0

Y2

Y1

Y3

CB 0-1

CB 2-3

CR 0-1

CR 0-1

Y0

Y2

Y1

Y3

CB 0-3

CR 0-3

Y0

Y2

Y1

Y3

CB 0-3

CR 0-3

RGB 4:4:4 Y CR CB 4:4:4 4:2:2 (ITU-601) 4:2:0 (MPEG-1) 4:2:0 (MPEG-2)

10/10/2008 EECS150 Lab Lecture #7 14

Administrative Info (1)

Project Partners Talk to us ASAP if you don’t have one

SVN Repositories Chris will give introduction next

Tuesday, 3:30-5:00pm (his OH time) Introduction will be audio-cast

(Audio-cast guaranteed this time)

10/10/2008 EECS150 Lab Lecture #7 15

Administrative Info (2)

Design Reviews Grading

You have it or you don’t Bring diagrams

Schematic “On a napkin”

Bubble-and-arc Block Diagrams

NO VERILOG

10/10/2008 EECS150 Lab Lecture #7 16

NO DESIGN NO HELP

10/10/2008 EECS150 Lab Lecture #7 17

ITU-R BT.601 Formerly, CCIR-601.

Designed for digitizing broadcast NTSC

National Television System Committee

Variations: 4:2:0 Chroma

Subsampling PAL (European) version

Component streaming: line i: CB Y CR Y CB Y CR Y line i+1: CB Y CR Y CB Y CRY

Effective Bits/Pixel: 4 components / 2 pixels =

32/2 = 16 bits/pixel

Active Frame Size

720 x 507

Frame Rate 29.97 /sec

Scan Interlaced

Chroma subsampling

4:2:22:1 in X onlyCoincedent

Bits per component

8

Effective bits/pixel

16

10/10/2008 EECS150 Lab Lecture #7 18

ITU-R BT.656 (1)

Details Pixels/Line: 858 Lines/Frame:525 Frames/S: 29.97 Pixels/S: 13.5M

Active Pixels/Line: 720 Lines/Frame:487

Blanking SAV/EAV: 4B/4B Black filler

7 1 8 7 1 9 72 0 7 2 1 0 1 2

3 59 3 6 0 0 1

359 3 6 0 0 1

7 3 67 3 2( )

3 6 83 66( )

3 6 83 6 6( )

8 5 78 6 3)(

Y 71

8

Y 71

9C

36

0B Y 72

0C

36

0R

Y 7

21

C

359

B

C

359

R

Y 7

36(7

32)

C

368(

366)

B

C

368(

366)

R

Y 85

5(86

1)C

42

8(43

1)B

Y 8

56(8

62)

Y 85

7(86

3)C

0

B

Y 0

C

0R

Y 1

C

428(

431)

R

C

0B

Y 0

Y 1

C

0R

C

359

B

Y 71

8

Y 71

9C

35

9R

L as t sam p leof d igi ta l act iv e l in e

S am p le d a tafor O i n st an t

F irs t sam p leof d igi ta l act iv e l in eH

Lu m in an ced a ta , Y

C h ro m in an ced a ta , C R

C h ro m in an ced a ta , C B

R e p lace d byti m in g referen ce

s ign al

R ep laced b yd igi tal b la nk in g d a t a

R ep l aced b yt im i n g re fe r en ce

s ig na l

E n d ofact iv e v id eo

Star t ofact iv e v id eo

T im in g refere nce si gn a ls

N o te 1 – Sam p le i d en ti fi cat io n nu m b ers i n pa ren the se s a re for 6 2 5 -li ne syst em s w h e re th e se di ffe r fro m th os e for 5 2 5 -li n e s yst em s . (Se e a lso R eco m m en d ation IT U -R B T .8 0 3 .)

FIG U RE 1

C om po sit ion of in te r fa c e da ta s tre a m

D 0 1

10/10/2008 EECS150 Lab Lecture #7 19

ITU-R BT.656 (2) Odd Field (262 Lines)

Total: 262 Lines 16 Vertical Blanking 244 Active 2 Vertical Blanking

Even Field Total: 263 Lines 17 Vertical Blanking 243 Active 3 Vertical Blanking

10/10/2008 EECS150 Lab Lecture #7 20

ITU-R BT.656 (3)

F: Field Select (0: Odd, 1: Even) V: Vertical Blanking Flag H: EAV/SAV Flag (0: SAV, 1: EAV) E[3]=V^H, E[2]=F^H, E[1]=F^V, E[0]=F^V^H

P9 P8 P7 P6 P5 P4 P3 P2

1’b1 1’b1 1’b1 1’b1 1’b1 1’b1 1’b1 1’b1

1’b0 1’b0 1’b0 1’b0 1’b0 1’b0 1’b0 1’b0

1’b0 1’b0 1’b0 1’b0 1’b0 1’b0 1’b0 1’b0

1’b1 F V H E[3] E[2] E[1] E[0]

10/10/2008 EECS150 Lab Lecture #7 21

Video Encoder (1) Analog Devices ADV7194

Supports ITU-R BT.601/656 S-Video and Composite Outputs I2C Control (We will give this to you)

10/10/2008 EECS150 Lab Lecture #7 22

Video Encoder (2)Signal Widt

hDir Description

VE_P 10 O Outoing NTSC Video (Use {Data, 2’b00})

VE_SCLK 1 O I2C Clock (For Initialization)

VE_SDA 1 O I2C Data (For Initialization)

VE_PAL_NTSC

1 O PAL/NTSC Mode Select (Always 1’b0)

VE_RESET_B_

1 O Active low reset (~Reset)

VE_HSYNC_B_

1 O Manual Control (Always 1’b1)

VE_VSYNC_B_

1 O Manual Control (Always 1’b1)

VE_BLANK_B_

1 O Manual Control (Always 1’b1)

VE_SCRESET 1 O Manual Control (Always 1’b0)

VE_CLKIN 1 O Clock (27MHz, Just send Clock)

10/10/2008 EECS150 Lab Lecture #7 23

Video Encoder (3)Signal Width Dir Description

Clock 1 I Clock input (27MHz)

Reset 1 I Reset input

Data 32 I Requested Data from ROM

DataValid 1 I Data is valid this cycle

DataReady 1 O The Video Encoder is ready to receive more data. If DataReady and DataValid are both high, the VideoEncoder should latch in Data on the next rising edge.

AddressLine 9 O Line of Video ({Line[7:0], Field}) The ROM will return a pixel pair from this line.

AddressPair 9 O Pair of Pixels. The line will return data for this pixel pair.

AddressValid 1 O AddressLine and AddressPair are valid this cycle.

AddressReady 1 I The sink connected to AddressLine/AddressPair is ready to receive those signals.

10/10/2008 EECS150 Lab Lecture #7 24

Video Encoder (4)A

DV

7194

Monitor

Outgoing V

ideo(S

-Video O

ut Cable)

Test ROM 32b N

TS

C V

ideo(N

o Blanking)

10b NT

SC

Video

(Com

plete)

I2C Control

Address Counter

H FSM V FSM

Blank Gen

(Mux)

Data Clip

VideoEncoder

IOR

egI2C

Clock &

data

I2C C

lock & data

32b Clipped YCrYCb(0x10≤Data≤0xF0)

Blank Control

I 2C D

one

General Video Encoder Block DiagramA

ddre

ss

Cou

nter

AddressValid

AddressReady

Address Lines

10/10/2008 EECS150 Lab Lecture #7 25

Video Encoder (5) Basic Design

Stream EAV, Blank, SAV, Active Lines Generate EAV/SAV/Blank using a mux Register output data (Timing reasons)

Request Incoming Data Request it the cycle before you need it Must be clipped

Minimum data is 0x10 Maximum data is 0xF0 Otherwise it will appear to be blanking signals

10/10/2008 EECS150 Lab Lecture #7 26

Video Encoder (6) Testing

Test thoroughly Simulation is difficult with test ROM Try using values which count, so you can

see it Design your testbench early

Perhaps one partner should design the module, one should design the testbench

Ensure that you test corner cases First and last lines Off-by-one errors in counters

10/10/2008 EECS150 Lab Lecture #7 27

I2C ADV7194 Initialization using I2C

Requires only 2 wires Serial Data (Bidirectional) Clock (Driven by master)

Runs at up to 400kHz Bidirectional Communication

Given to you Complicated to get right Hard to debug

10/10/2008 EECS150 Lab Lecture #7 28

I2C (2) Physical Protocol

Data Open collector

bidirectional bus Driven by sender

Clock Open collector

unidirectional bus Driven by master May be pulled low

to stall transmission

10kΩ Pullup 10kΩ Pullup

DIn

DO

ut

Ena

ble

DIn

DO

ut

Ena

ble

Endpoint BEndpoint A

Bidirectional Open Collector Bus

10/10/2008 EECS150 Lab Lecture #7 29

I2C (3) Protocol

Start Condition Address Address Acknowledge Data Transfer Data Acknowledge Stop Condition

10/10/2008 EECS150 Lab Lecture #7 30

I2C (4) Arbitration

Anyone can drive bus at any time No central arbiter No short circuits (Impossible in open

collector) Decentralized Arbitration

Check data bus against value you’re sending Mismatch means someone else is

transmitting So let them finish, and then try again

Inherently gives preferences to accesses with more 1’b1s in them

10/10/2008 EECS150 Lab Lecture #7 31

More Information Checkpoint Writeup Documents Page of the Website

Video in a Nutshell ADV7194 Datasheet

Complete ADV7194 reference ITU-R BT.656 & ITU-R BT.601 Standards

Complete video standards I2C Bus Specification

READ THE DATASHEETS!