3/10/2006eecs150 lab lecture #81 chipcon 802.15.4 transceiver eecs150 spring 2006 lab lecture #8...
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3/10/2006 EECS150 Lab Lecture #8 1
Chipcon 802.15.4 Transceiver
EECS150 Spring 2006Lab Lecture #8
David Lin
3/10/2006 EECS150 Lab Lecture #8 2
Project Overview N64 Controller
User input to your game. Video
Game output to the user. Chipcon Transceiver: the “FUN” Two-
Week One! =) Bidirectional communication between games.
Game Engine Drives game play. “Glue logic.” Handles
communication handshaking.
3/10/2006 EECS150 Lab Lecture #8 3
Transceiver Overview (1) 3rd party chip mounted on expansion board.
Uses a PCB antenna. Take a look! IEEE 802.15.4 standard support. Zigbee
ready. Transmits on unlicensed 2.4 GHz spectrum.
16 communication channels. Overlaps with Wi-Fi.
250 kbps maximum data rate. We will only be using a very small percentage of this.
Configure, send, receive, and issue commands to chip over SPI to CC2420 registers.
3/10/2006 EECS150 Lab Lecture #8 4
Transceiver Overview (2) 33 configuration registers.
We change 3 of them. 15 command strobe registers.
We issue 6 of them. These change the state of the CC2420
internal FSM. 128-byte RX FIFO & 128-byte TX FIFO
Accessed via 2 additional registers. Also accessible as RAM (i.e. by addressing).
Only for debugging! Probably not necessary.
3/10/2006 EECS150 Lab Lecture #8 5
CC2420 Inputs & Outputs
FPGA
VREG_EN
RF_RESET_
Single bit status signals. High level transceiver
operation information. Initialization signals.
Drive signals once and forget about it.
SPI interface. Interface to rest of chip
via CC2420 registers. Send, receive,
configuration, detailed status.
3/10/2006 EECS150 Lab Lecture #8 6
Single Bit Status Indicators FIFO – Goes high when there’s received
data in RX FIFO. FIFOP – Goes high when # bytes received
exceeds set threshold. CCA – Indicates that the transmission
medium (air) is clear. Only valid after 8 symbol periods in RX mode.
SFD – Goes high after SFD is transmitted & low after packet completely sent.
3/10/2006 EECS150 Lab Lecture #8 7
SPI Interface Serial interface with 4 wires:
SClk – Clock signal you generate. CS_ – Active-low chip select. SI – Output to the CC2420. SO – Input from the CC2420.
Described earlier in class lecture. Interface to the chip! Initialization,
configuration, TX, RX, detailed status. Luckily for you, it’s provided as a black
box.
3/10/2006 EECS150 Lab Lecture #8 8
CC2420-specific SPI (1):First Byte
First byte always has above format. Bit 7 – Set to 0 for register access. Bit 6 – Read/write control. Bits 5:0 – Address of register. P. 60 of datasheet.
Followed by data specific to register being accessed.
Sent First Bit Position Sent Later
7 6 5:0
1 = RAM access (not used)0 = register access
1 = read0 = write
Address of register. Refer to p. 60 of the datasheet.
3/10/2006 EECS150 Lab Lecture #8 9
CC2420-specific SPI (2):Writing to Configuration Reg.
First byte followed by 2 bytes of configuration data. Data on SO invalid here.
Transceiver replies when first byte is sent out with status byte.
True for all SPI accesses. Not necessary to inspect, but can be helpful for debugging!
Sent First Byte Number Sent Later
1 2 - 3
Sent on SI address byte, described above 16 bits of data to be written to register
Received on SO
status byte 16’bX
3/10/2006 EECS150 Lab Lecture #8 10
CC2420-specific SPI (3):Issuing Command Strobes
One byte only. Nothing follows. Address sent indicates the command strobe
being issued. Note that 0x00 is NO OP. This is useful for
explicitly retrieving status byte.
Byte Number
1
Sent on SI address byte, described above
Received on SO status byte
3/10/2006 EECS150 Lab Lecture #8 11
CC2420-specific SPI (4):Saving to TX FIFO
After first byte, send n bytes of data to transmit over wireless.
SPI session only ends when CS_ is pulled high.
CC2420 replies with a new status byte with each byte that’s saved to FIFO.
Sent First Byte Number Sent Later
1 2 to n
Sent on SI address byte, described above data bytes to be transmitted
Received on SO status byte
3/10/2006 EECS150 Lab Lecture #8 12
CC2420-specific SPI (5):Receive from RX FIFO
After first byte, send a n bytes of “don’t care” in order to receive data.
During first byte, CC2420 replies with status. Subsequent bytes are data saved in FIFO.
Must be careful not to request data from empty FIFO! SPI session only ends when CS_ is pulled high. Reading from a configuration register is the same.
Received First Byte Number Received Later
1 2 to n
Sent on SI address byte, described above 8’bX
Received on SO status byte data from the RX FIFO
3/10/2006 EECS150 Lab Lecture #8 13
Configuration Registers
Register Address Bit(s) of Interest
Purpose
MDMCTRL0 0x11 11 Turn off automatic address recognition. You must set bit 11 to 1’b0.
FSCTRL 0x18 9:0 Channel changing.
IOCFG0 0x1C 6:0 Changes the threshold of number of bytes in RX FIFO before FIFOP goes high. Defaults to 64. You may want to change this value.
3/10/2006 EECS150 Lab Lecture #8 14
Command Strobe Registers
Register Address Purpose
SNOP 0x00 No operation.
SXOSCON 0x01 Turns on the crystal oscillator and will be used as part of the initialization process.
SRXON 0x03 Moves the CC2420 into the receive state and will be used as part of the initialization and channel changing process.
STXON 0x04 Instructs the CC2420 to transmit the data contained in the TX FIFO.
SRFOFF 0x06 Turns off RX/TX and frequency synthesizer and will be used as part of channel changing.
SFLUSHRX 0x08 Flushes the RX FIFO. This command will be used a lot!
3/10/2006 EECS150 Lab Lecture #8 15
TX/RX FIFO Registers
Register Address Purpose
TXFIFO 0x3E For saving bytes to transmit into the TX FIFO. You must not write data to the FIFO while a transmission is in progress.
RXFIFO 0x3F For retrieving bytes from the RX FIFO.
3/10/2006 EECS150 Lab Lecture #8 16
Initialization
Assert VREG_EN.
Check if oscillator’s running.
Issue SXOSCON.
Change to assigned channel.
Turn off address
recognition.
Lower FIFOP threshold (optional).
Issue SRXON to enter receive
state.
Pulse RF_RESET_.
Wait a few ms.
Running.
Not running.
3/10/2006 EECS150 Lab Lecture #8 17
Transmit
Save data into TX FIFO.
Wait.Issue
STXON.Return to
Start state.Wait.
Check CCA
signal.
Clear. SFD low to high. SFD low to high.At least 60 clock
cycles.
Not clear.
3/10/2006 EECS150 Lab Lecture #8 18
Receive (1)
Start.Receive source
address.
Receive length.
Receive payload.
Receive destination address.
Begin RX FIFO recv.
FIFO and/or FIFOP high.
Length is 8 bytes.
Source address matches.
Destination address matches.
Receive CRC.
Retained saved bytes.
Discard saved bytes. CRC doesn’t
check.
CRC checks.
3/10/2006 EECS150 Lab Lecture #8 19
Receive (2)
Packets are only received after CC2420 has spent 12 symbol periods in receive mode.
There must be wait time between transmissions. Allows the transceiver to look for and
receive data.
3/10/2006 EECS150 Lab Lecture #8 20
Announcements
Next week’s lab lecture is Thursday 8-9P. Come with questions!
Groups have been assigned channels and addresses. Check online grade book.
3/10/2006 EECS150 Lab Lecture #8 21
Design Structure (1)
SPIFifo(provided)
SPI(provided)
Chipcon CC2420
Control FSM
RX Arbitration
Logic
Control FSM
IORegister
TX Arbitration
Logic
Arbitration Logic
SPI: SClk, CS_, SI, SO
delayedCCA, SFD,
FIFO, FIFOP
VReg_En,Rf_Reset_
control signals
Start Ready
inputs & handshaking
controlsignals
SrcAddr
DestAddr
control signals
Out, NewData
In, SrcAddrIn,DestAddrIn &handshaking
InRequest,InValid, In
NewData
Out
SrcAddrOut
DestAddrOut
Channel
In
CCA, SFD, FIFO, FIFOP
REn
Game Engine(Checkpoint 4)
FPGA_TOP
Transceiver
SPI Abstraction
Note: Clock and Reset signals are not shown.
3/10/2006 EECS150 Lab Lecture #8 22
Design Structure (2)
Transceiver – Highest level block. 32-bit input/output, channel changing, addressing. SPI Abstraction – Takes care of details of
CC2420 SPI interface. Arbitrates between TX/RX.
SPI (provided) – Handles details of interface timing.
SPIFifo (provided) – Storage place for filtered, received data.
3/10/2006 EECS150 Lab Lecture #8 23
Packet Format
MPDU
Preamble SFD Length Source Dest. Payload Frame Check Sequence (CRC)
4 bytes 1 byte 1 byte 1 byte 1 byte 4 bytes 2 bytes
0x00 0x7A 0x08sender’s
addr.
recipient’s addr. or 0xFF for broadcast
data
On transmit, 0x00. On receive, bit 7 of the 2nd
byte is 1 when CRC ok, 0 otherwise.
On transmit, only fill TX FIFO starting with length byte. Preamble & SFD automatically appended. Transmit all zeros for CRC. CC2420 will replace.
3/10/2006 EECS150 Lab Lecture #8 24
Channel & Addresses
There are 16 channels. Your group has been assigned a channel. You must be able to change channels
without reset! Address are 8-bits wide 256
addresses. Zero is unused. 0xFF is reserved for broadcast. Your group has been assigned 2
addresses.
3/10/2006 EECS150 Lab Lecture #8 25
Interference & Debugging Roughly 2-3 groups per channel. Each
group in a particular lab has distinct channel. Can also pick up data on neighboring channel. Very first goal is robust channel changing
during initialization. Can pick up 802.11 packets sometimes.
Your module must recover gracefully. Your project interferes with Wi-Fi & vice
versa.
3/10/2006 EECS150 Lab Lecture #8 26
Handshaking:InRequest/Invalid
XXXXXXX In0 XX
Clock
InRequest
InValid
In In1
SPI uses a variation of this. You may want to use this internally.
3/10/2006 EECS150 Lab Lecture #8 27
Handshaking:Ready/Start
Transceiver uses this interface for input & output.
Clock
Ready
Start
In XXX In0 XIn1
3/10/2006 EECS150 Lab Lecture #8 28
Debugging Tools
Chipscope! We will be releasing some
debugging utilities. Packet sniffer. Packet counter.
3/10/2006 EECS150 Lab Lecture #8 29
Get Started! Don’t count on spring break.
This is meant to replace a ~50 hour (avg.) SDRAM checkpoint.
There are many subtleties that you must address (e.g. when are RX flushes used?).
I will monitor newsgroup over spring break, but less frequently.
Next week’s lab lecture is CP3 Q&A. Come with questions.
Read the datasheet!