1 motivation and design issues interest in exhibiting advantage of cmos based digital control very...
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1
Motivation and Design Issues
• Interest in exhibiting advantage of CMOS based digital control
• Very low standby power feasible in PFM (low power) mode
• Dramatic power saving in PWM mode due to internal power management
2
System Block Diagram
•Two modes: PWM and PFM
REF
FB
SWPFMcontrol
PWMcontrol
digitaldither ring
osc.
MUX
soft start counter
ring ADC
clk
De
Dc
comparator
PVIN
PGND
MODEENSGND
SVDD
digital controller
clk
3
Berkeley Switcher Specifications
Symbol
Parameter Min Typ Max Units
fsw Switching Freq 500 1500 kHz
Io,max Max Output Current 500 mA
VIN Input Voltage 2.8 5.5 V
Ilim Switch Peak Current Limit 1000 mA
ΔVADC PWM Mode ADC Quantization Bin 16 mV
ton PFM Fixed On-time 1.3 μs
NDPWM PWM Resolution 5 + 5 Bit
NDITH PWM Digital Dither Resolution 5 Bit
Tsoft-start Soft start duration 1100 μs
IPFMQuiescent current in PFM mode 3 μA
4
Power Train
Problem: high input voltage vs low voltage process
Solutions: 1. Cascoded stucture2. Lateral drain extension structure
5
Power Train: Cascoded Structure
Drain
VBias
VIN
Source
VOX
Gate oxide breakdown voltage ~5V
Drain
Source
VOX
VIN
Working voltage ~ 2.5V
6
Power Train: LDD Structure
n well
com
pos
ite
gat
e
n well
com
pos
ite
gat
e
com
pos
ite
gat
e
com
pos
ite
gat
e p-LDD layout
n-LDD layout
0
0.3
0.6
0.9
1.2
1.5
1.8
0 2 4 6 8 10
Vgs=1.4V Vgs=2.5V
n-LDD (Ω) 0.27 0.22
p-LDD (Ω) 1.03 0.51
Rdson:
0
0.4
0.8
1.2
1.6
0 2 4 6 8 10
Measured break down voltage
I D (
mA
)
I D (
mA
)
VDS (V) VDS (V)
n-LDD: 7.5~8V p-LDD: 6.5~7.2V
7
Cascoded Structure Test Results
20000
0.24
10000
0.24
PVIN
PVIN/2
GND
SW
Vgs=1.4V Vgs=2.5V
NMOS (Ω) 0.33 0.25
PMOS (Ω) 0.60 0.35
Rdson:
NMOS break down voltage: 7.7V
VDS (V)
I D (
uA
)
Rdson:
0
50
100
150
200
250
0 2 4 6 8 100
20
40
60
80
100
120
7.4 7.5 7.6 7.7 7.8 7.9 8 8.1
PMOS break down voltage: 7.9V
8
Internal Power Management
20000
0.24
10000
0.24
NFET signal
PVIN
PVIN/2
GND
PFET signal
SW
Digital controller
Voltage regulator
Scavenges power from gate drive discharge
Offers safe supply voltage for controller circuitry
80A
40A
40A PWM
9
Internal Voltage Regulations
• Total current consumptions: 1A
• BW of each amplifier: 40kHz
PVIN
PGND
VCext
PVIN
PGND
V/2
V/2 Cext
10
Control Law
• PFM Mode (low power, low quiescent curr.)• Fixed on-time control avoids ripple jitter due to
discrete sampling of comparators at rising Vout in hyst
ctrl
• ton = 0.8 Tsw = 1.33 s Vripp,max = 90 mV @ Vin = 5.5 V,
Iout = 0.1 mA
• At high output loads, still jitter due to sampling
• PWM Mode• PID control with digital dither
• Saturated controller response (for large transients)
11
PFM (Fixed On-time) Mode
12
ADC and DPWM Resolution
VADC = 16 mV = 0.8% reg @ Vout = 1V
VDPWM = 5.4 mV @ Vin = 5.5 V• 5 bit ring osc + 5 bit digital dither • no limit cycling in steady state
• Sampled at fsw
13
PWM Mode: DPWM Module
PWM off
VDD
VSS
5-bit Differential Ring
5-bit MUX
5
VDD
1 pair of differential signals
VDDL
Isupply
Ring-MUX Structure
Level Shifter
Dc
14
Protection Mode Soft Start
• Build into digital control loop
• Disable PD control
• Make error signal slew the digital integrator
to the appropriate level corresponding to
Vout = Vref
• Gain of error signal set to effect desired
duration of soft-start sequence, tsoft-start =
1100 s
15
Digital processing core
PD
Int
Comb
Logic
Dither
Fully on
Fully off
Dc_calcDe Dc
Clamp
From ringAD
C en
en
Pin: EN Soft start
counter
en Soft_start
Go to DPWM
16
Ring ADC Basics
Frequency of ring oscillator has linear relation with Itot when voltage swing is below threshold:
VDD
Itot
4-stage differential ring oscillator running at sub-threshold current
bImf tot
Simulated oscillator frequency versus supply current
3.0E+06
4.0E+06
5.0E+06
6.0E+06
7.0E+06
4.E-07 5.E-07 6.E-07 7.E-07 8.E-07 9.E-07
r2=0.99991m=6.83e12b=378034
Supply Current (A)
Frequency
(H
z)
17
Ring ADC Architecture
0
0
( )st T
e o reftD V V dt
Sampling freq=500kHz, LSB=16mV, approx 100mV window, VDD=1.5V
Measured current: 36.72A, area = 0.15 mm2
De’
LevelShifter
LevelShifter
CounterN
Counter1
LevelShifter
Counter1
LevelShifter
CounterN
N
N
Σ
Σ
VDD
VSS
Vo Vref
D1
D2
Analog Block
Digital Block
18
PFM Mode: Comparator Details
CK
CK
CK
CK
CK
Vin
Vip
Vop
Von
19
PFM Mode Quiescent Current
Simulation: 600kHz sampling frequency Comparator, ring osc., level shifters(from
ring voltage to internal VDD), and clock generation: 3μA (from PVIN/2)
Internal voltage regulators: 1.0μA(from PVIN)
20
Berkeley Switcher Layout
Ring ADC
DPWM &
Clk Gen
Digi
Core
PFM ModeComparator
Power Train
Gate Drives
PFET
NFET500μm
2.6mm
1.7
mm
21
Comparison between Analog and Digital Controllers
For mobile phone application:
Controller Total Quiescent Current
PFM Mode PWM Mode (not include power train)
LM2612 150A 550A
Berkeley Switcher (Simulated)
3 A
22
Berkeley Switcher Pin Description
Pin Number
Pin Name Function
1 FB ADC input. Connect directly to Vout
2 REF Analog voltage reference Vref
3 MP Internal Voltage Level, mid-point of PVIN & PGND
4 MODE High for PFM mode
Low for PWM mode
5 EN Enable Input
6 PGND Power Ground
7 SW Switching Node connection to internal PFET & NFET
8 PVIN Power Supply Input to internal PFET switch
9 SVDD Signal Supply Input
10 SGND Analog and Control Ground• Taped-out in Oct 10, 2002, packaged chip returned Jan.20, 2003
• Implemented in 0.25um CMOS
23
Personnel and Roles
• Prof. Seth Sanders, project leader
• Jinwen Xiao, PhD student (5th year), leadership on IC designs
• Angel Peterchev, PhD student (4rd year), leadership on architecture issues
• Kenny (Jianhui) Zhang, PhD student (2nd year), responsibility for power train design
24
• Y.C. Liang, visiting Nov.2001~Sep.2002 from Natl. Univ. Singapore, for advising on power train design
• Joe Emlano for packaging the chip
Thanks To