11

Logic synthesis from Logic synthesis from concurrent specificationsconcurrent specifications

Jordi CortadellaJordi Cortadella

Universitat Politecnica de CatalunyaUniversitat Politecnica de CatalunyaBarcelona, SpainBarcelona, Spain

In collaboration with M. Kishinevsky,A. Kondratyev, L. Lavagno and A. Yakovlev

22

OutlineOutline

Overview of the synthesis flowOverview of the synthesis flow

SpecificationSpecification

State graph and next-state functionsState graph and next-state functions

State encodingState encoding

Implementability conditionsImplementability conditions

Speed-independent circuitSpeed-independent circuit Complex gatesComplex gates C-element architectureC-element architecture

Review of some advanced topicsReview of some advanced topics

33

Book and synthesis toolBook and synthesis tool

J. Cortadella, M. Kishinevsky, A. Kondratyev,J. Cortadella, M. Kishinevsky, A. Kondratyev,L. Lavagno and A. Yakovlev,L. Lavagno and A. Yakovlev,Logic synthesis for asynchronousLogic synthesis for asynchronouscontrollers and interfaces,controllers and interfaces,Springer-Verlag, 2002Springer-Verlag, 2002

petrify:petrify:http://www.lsi.upc.es/petrifyhttp://www.lsi.upc.es/petrify

44

Specification(STG)

State Graph

SG withCSC

Next-state functions

Decomposed functions

Gate netlist

Reachability analysis

State encoding

Boolean minimization

Logic decomposition

Technology mapping

Design flowDesign flow

55

x

y

z

x+

x-

y+

y-

z+

z-

Signal Transition Graph (STG)

xy

z

SpecificationSpecification

66

x

y

z

x+

x-

y+

y-

z+

z-

Token flowToken flow

77

x+

x-

y+

y-

z+

z-

xyz000

x+

100y+z+

z+y+

101 110

111

x-

x-

001

011y+

z-

010

y-

State graphState graph

88

x z x y ( )

y z x

z x y z

Next-state functionsNext-state functionsxyz000

x+

100y+z+

z+y+

101 110

111

x-

x-

001

011y+

z-

010

y-

99

x

z

y

Gate netlistGate netlist

x z x y ( )

y z x

z x y z

1010

Specification(STG)

State Graph

SG withCSC

Next-state functions

Decomposed functions

Gate netlist

Reachability analysis

State encoding

Boolean minimization

Logic decomposition

Technology mapping

Design flowDesign flow

1111

VME busVME bus

DeviceLDS

LDTACK

D

DSr

DSw

DTACK

VME BusController

DataTransceiver

BusDSr

LDS

LDTACK

D

DTACK

Read Cycle

1212

STG for the READ cycleSTG for the READ cycle

LDS+ LDTACK+ D+ DTACK+ DSr- D-

DTACK-

LDS-LDTACK-

DSr+

LDS

LDTACK

D

DSr

DTACK

VME BusController

1313

Choice: Read and Write cyclesChoice: Read and Write cycles

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

DTACK-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

DTACK-

LDS-

LDTACK-

1414

Choice: Read and Write cyclesChoice: Read and Write cycles

DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

1515

CircuitCircuit synthesissynthesis

Goal:Goal: Derive a hazard-free circuitDerive a hazard-free circuit

under a given delay model andunder a given delay model andmode of operationmode of operation

1616

Speed independenceSpeed independence

Delay modelDelay model Unbounded gate / environment delaysUnbounded gate / environment delays Certain wire delays shorter than certain paths in the Certain wire delays shorter than certain paths in the

circuitcircuit

Conditions for implementability:Conditions for implementability: ConsistencyConsistency Complete State CodingComplete State Coding PersistencyPersistency

1717

Specification(STG)

State Graph

SG withCSC

Next-state functions

Decomposed functions

Gate netlist

Reachability analysis

State encoding

Boolean minimization

Logic decomposition

Technology mapping

Design flowDesign flow

1818

STG for the READ cycleSTG for the READ cycle

LDS+ LDTACK+ D+ DTACK+ DSr- D-

DTACK-

LDS-LDTACK-

DSr+

LDS

LDTACK

D

DSr

DTACK

VME BusController

1919

Binary encoding of signalsBinary encoding of signals

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

2020

Binary encoding of signalsBinary encoding of signals

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

10000

10010

10110 01110

01100

0011010110

(DSr , DTACK , LDTACK , LDS , D)

2121

QR (LDS+)QR (LDS+)

QR (LDS-)QR (LDS-)

Excitation / Quiescent RegionsExcitation / Quiescent Regions

ER (LDS+)ER (LDS+)

ER (LDS-)ER (LDS-)

LDS-LDS-

LDS+

LDS-

2222

Next-state functionNext-state function

0 1

LDS-LDS-

LDS+

LDS-

1 0

0 0

1 1

1011010110

2323

Karnaugh map for LDSKarnaugh map for LDS

DTACKDSrD

LDTACK 00 01 11 10

00

01

11

10

DTACKDSrD

LDTACK 00 01 11 10

00

01

11

10

LDS = 0 LDS = 1

0 1-0

0 0 0 0 0 0/1?

1

111

-

-

-

---

- - - -

-

- ---

- - -

2424

Specification(STG)

State Graph

SG withCSC

Next-state functions

Decomposed functions

Gate netlist

Reachability analysis

State encoding

Boolean minimization

Logic decomposition

Technology mapping

Design flowDesign flow

2525

Concurrency reductionConcurrency reduction

LDS-LDS-

LDS+

LDS-

1011010110

DSr+

DSr+

DSr+

2626

Concurrency reductionConcurrency reduction

LDS+ LDTACK+ D+ DTACK+ DSr- D-

DTACK-

LDS-LDTACK-

DSr+

2727

State encoding conflictsState encoding conflicts

LDS-

LDTACK-

LDTACK+

LDS+

10110

10110

2828

Signal InsertionSignal Insertion

LDS-

LDTACK-

D-

DSr-

LDTACK+

LDS+

CSC-

CSC+

101101

101100

2929

Specification(STG)

State Graph

SG withCSC

Next-state functions

Decomposed functions

Gate netlist

Reachability analysis

State encoding

Boolean minimization

Logic decomposition

Technology mapping

Design flowDesign flow

3030

Complex-gate implementationComplex-gate implementation

)(csccsc

csc

csc

LDTACKDSr

LDTACKD

DDTACK

DLDS

3131

Implementability conditionsImplementability conditions

ConsistencyConsistency Rising and falling transitions of each signal Rising and falling transitions of each signal

alternate in any tracealternate in any trace

Complete state coding (CSC)Complete state coding (CSC) Next-state functions correctly definedNext-state functions correctly defined

PersistencyPersistency No event can be disabled by another event No event can be disabled by another event

(unless they are both inputs)(unless they are both inputs)

3232

Implementability conditionsImplementability conditions

Consistency + CSC + persistencyConsistency + CSC + persistency

There exists a speed-independent circuit There exists a speed-independent circuit that implements the behavior of the STGthat implements the behavior of the STG

(under the assumption that ay Boolean function (under the assumption that ay Boolean function can be implemented with one complex gate)can be implemented with one complex gate)

3333

PersistencyPersistency

100 000 001a- c+

b+ b+

a

cb

a

c

b

is this a pulse ?

Speed independence glitch-free output behavior under any delay

a+

b+

c+

d+

a-

b-

d-

a+

c-a-

0000

1000

1100

0100

0110

0111

1111

1011

0011 1001

0001

a+

b+

c+

a-

b-

c-

a+

c-

a-

a-

d-d+

0000

1000

1100

0100

0110

0111

1111

1011

0011 1001

0001

a+

b+

c+

a-

b-

c-

a+

c-

a-

a-

d-d+

abcd 00 01 11 10

00

01

11

10 1

1 1 11

10

0 000

ER(d+)

ER(d-)

abcd 00 01 11 10

00

01

11

10 1

1 1 11

10

0 000

adcd

0000

1000

1100

0100

0110

0111

1111

1011

0011 1001

0001

a+

b+

c+

a-

b-

c-

a+

c-

a-

a-

d-d+

Complex gate

3737

Implementation with C elementsImplementation with C elements

CR

S z

• • • S+ z+ S- R+ z- R- • • •

• S (set) and R (reset) must be mutually exclusive

• S must cover ER(z+) and must not intersect ER(z-) QR(z-)

• R must cover ER(z-) and must not intersect ER(z+) QR(z+)

abcd 00 01 11 10

00

01

11

10 1

1 1 11

10

0 000

0000

1000

1100

0100

0110

0111

1111

1011

0011 1001

0001

a+

b+

c+

a-

b-

c-

a+

c-

a-

a-

d-d+

CS

Rdc

ca

abcd 00 01 11 10

00

01

11

10 1

1 1 11

10

0 000

0000

1000

1100

0100

0110

0111

1111

1011

0011 1001

0001

a+

b+

c+

a-

b-

c-

a+

c-

a-

a-

d-d+

CS

Rdc

cba

Monotonic covers

4242

C-based implementationsC-based implementations

CS

Rdc

cbaC

d

ab

c

a

b

cd

weak

a

cd

generalized C elements (gC)

weak

4343

Speed-independent Speed-independent implementationsimplementations

Implementability conditionsImplementability conditions ConsistencyConsistency Complete state codingComplete state coding PersistencyPersistency

Circuit architecturesCircuit architectures Complex (hazard-free) gatesComplex (hazard-free) gates C elements with monotonic coversC elements with monotonic covers ......

4444

Synthesis exerciseSynthesis exercisey-

z- w-

y+ x+

z+

x-

w+

1011

0111

0011

1001

1000

1010

0001

0000 0101

0010 0100

0110

y-

y+

x-

x+w+

w-

z+

z-

w-

w-

z-

z-y+

y+

x+

x+

Derive circuits for signals x and z (complex gates and monotonic covers)

4545

Synthesis exerciseSynthesis exercise1011

0111

0011

1001

1000

1010

0001

0000 0101

0010 0100

0110

y-

y+

x-

x+w+

w-

z+

z-

w-

w-

z-

z-y+

y+

x+

x+

wxyz 00 01 11 10

00

01

11

10

-

-

-

-

Signal x

1

0

1

1

1

1

1

0 0

0

0

0

4646

Synthesis exerciseSynthesis exercise1011

0111

0011

1001

1000

1010

0001

0000 0101

0010 0100

0110

y-

y+

x-

x+w+

w-

z+

z-

w-

w-

z-

z-y+

y+

x+

x+

wxyz 00 01 11 10

00

01

11

10

-

-

-

-

Signal z

1

0 0

0

0

11 1

0

0 0

0

4747

y-

z- w-

y+ x+

z+

x-

w+

1001 1011

1000

1010

0001

0000 0101

0010 0100

0110 0111

0011

y-

y+

x-

x+w+

w-

z+

z-

w-

w-

z-

z-y+

y+

x+

x+

Logic decomposition: exampleLogic decomposition: example

4848

yz=1yz=0

1001 1011

1000

1010

0001

0000 0101

0010 0100

0110 0111

0011

y-

y+

x-

x+w+

w-

z+

z-

w-

w-

z-

z-y+

y+

x+

x+

1001 1011

1000

1010

0001

0000 0101

0010 0100

0110 0111

0011

y-

y+

x-

x+w+

w-

z+

z-

w-

w-

z-

z-y+

y+

x+

x+

C

C

x

y

x

y

w

z

xyz

y

zw

z

w

z

y

Logic decomposition: exampleLogic decomposition: example

4949

s-

s+

s-

s-

s=1

s=0

1001 1011

1000

1010

0111

0011y+

x-

w+

z+

z-

0001

0000 0101

0010 0100

0110

x+

w-

w-

w-

z-

z-y+

y+

x+

x+

1001

1000

1010

y+

z-

0111

C

C

x

y

x

y

w

z

x

y

z

w

z

w

z

y

sy-

Logic decomposition: exampleLogic decomposition: example

5050

y-

z- w-

y+ x+

z+

x-

w+

s-

s+

s-

s+

s-

s-

s=1

s=0

1001 1011

1000

1010

0111

0011y+

x-

w+

z+

z-

0001

0000 0101

0010 0100

0110

x+

w-

w-

w-

z-

z-y+

y+

x+

x+

1001

1000

1010

y+

z-

0111

y-

Logic decomposition: exampleLogic decomposition: example

5151

Speed-independent NetlistSpeed-independent Netlist

LDS+ LDTACK+ D+ DTACK+ DSr- D-

DTACK-

LDS-LDTACK-

DSr+

DTACKD

DSr

LDS

LDTACK

csc

map

5252

Adding timing assumptions Adding timing assumptions

LDS+ LDTACK+ D+ DTACK+ DSr- D-

DTACK-

LDS-LDTACK-

DSr+

DTACKD

DSr

LDS

LDTACK

csc

map

LDTACK- before DSr+

FAST

SLOW

5353

Adding timing assumptionsAdding timing assumptions

DTACKD

DSr

LDS

LDTACK

csc

map

LDS+ LDTACK+ D+ DTACK+ DSr- D-

DTACK-

LDS-LDTACK-

DSr+

LDTACK- before DSr+

5454

State space domainState space domain

LDTACK- before DSr+

LDTACK-

DSr+

5555

State space domainState space domain

LDTACK- before DSr+

LDTACK-

DSr+

5656

State space domainState space domain

LDTACK- before DSr+

LDTACK-

DSr+

Two more unreachable states

5757

Boolean domainBoolean domain

DTACKDSrD

LDTACK 00 01 11 10

00

01

11

10

DTACKDSrD

LDTACK 00 01 11 10

00

01

11

10

LDS = 0 LDS = 1

0 1-0

0 0 0 0 0 0/1?

1

111

-

-

-

---

- - - -

-

- ---

- - -

5858

Boolean domainBoolean domain

DTACKDSrD

LDTACK 00 01 11 10

00

01

11

10

DTACKDSrD

LDTACK 00 01 11 10

00

01

11

10

LDS = 0 LDS = 1

0 1-0

0 0 - 0 0 1

1

111

-

-

-

---

- - - -

-

- ---

- - -

One more DC vector for all signals One state conflict is removed

5959

Netlist with one constraintNetlist with one constraint

LDS+ LDTACK+ D+ DTACK+ DSr- D-

DTACK-

LDS-LDTACK-

DSr+

DTACKD

DSr

LDS

LDTACK

csc

map

6060

Netlist with one constraintNetlist with one constraint

LDS+ LDTACK+ D+ DTACK+ DSr- D-

DTACK-

LDS-LDTACK-

DSr+

DTACK D

DSr LDS

LDTACK

LDTACK- before DSr+

TIMING CONSTRAINT

6161

ConclusionsConclusions

STGs have a high expressiveness power at a low level STGs have a high expressiveness power at a low level of granularity (similar to FSMs for synchronous systems)of granularity (similar to FSMs for synchronous systems)

Synthesis from STGs can be fully automatedSynthesis from STGs can be fully automated

Synthesis tools often suffer from the state explosion Synthesis tools often suffer from the state explosion problem (symbolic techniques are used)problem (symbolic techniques are used)

The theory of logic synthesis from STGs can be found in:The theory of logic synthesis from STGs can be found in:

J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno and A. Yakovlev,J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno and A. Yakovlev,Logic Synthesis of Asynchronous Controllers and InterfacesLogic Synthesis of Asynchronous Controllers and Interfaces ,,Springer Verlag, 2002.Springer Verlag, 2002.