1. introduction to the design of analog integrated circuitspserra/uab/damics/damics-1-intro.pdf ·...

1. Introduction to the Design of Analog ICs

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells

1/129CMOS Idea-to-Chip Modeling OpAmp Lab

1. Introduction to the Designof Analog Integrated Circuits

Francesc Serra Graells

[email protected] de Microelectrònica i Sistemes Electrònics

Universitat Autònoma de Barcelona

[email protected] Circuits and Systems

IMB-CNM(CSIC)




CMOS Technologies1

From the Idea to the Chip2

Device Modeling for Analog Design3

The Operational Amplifier and its FoMs4

Lab Proposal5




CMOS Technologies1




Lab Proposal5




Moore's Law

Number of transistorsper chip doubles every24 months

wikipedia.org/wiki/Transistor_count

1970 1980 1990 2000 2010 2020Date of Introduction

Mic

rop

roce

ssor

Transi

stor

Cou

nt

Intel 4004

80808085

Z80

Intel8088

WDC 65C02

Intel 80186Motorola

Intel 80286Motorola 68020

Intel 80386

ARM 1ARM 2

TI Explorer

Intel i960

Intel 80486

ARM 3

MIPS R4000

ARM 6

Intel Pentium

ARM 7

ARM 9

Intel Pentium ProAMD K5

Pentium IIAMD K6 Pentium III

AMD K7

Intel Pentium 4

Intel Pentium D

Intel Atom

AMD K8

Intel Itanium 2AMD K10

ARM A9

Intel 4-Core i7IBM POWER6 Apple A7

Itanium 2

Apple A8IBM POWER8Intel 61-Core Xeon

Xbox One

Oracle SPARC M7

Zilog

68000

8086

Intel 2-Core Intel8-Core i7

1k

10k

100k

1M

10M

100M

1G

10G

1 oct / 2 year1971-2016 data collected from:

http://dx.doi.org/10.1109/N-SSC.2006.4785860Gordon E. Moore,Cramming More Components onto Integrated Circuits,Electronics Magazine, 38(8):114–117, Apr 1965 3 dec / 20 years

1 oct / 1 year




Moore's Law


Thanks to scaling, not atchip (yield!), but attransistor (litho) level

3nm-Hafnium dielectric

Technology nodes200490nm

200665nm

200845nm

201032nm

SiGe-strainedSilicon

High-kmetal gate

GEN1 GEN2 GEN1 GEN2

1.2-nm SiO2 dielectric(5 atomic layers!)

Silicon substrate

Work-function metal

Low-resistance layer

25mm

Typ. reticle size

25mm

625mm2

Front-endof line

(FEOL)




Moore's Law



3nm-Hafnium dielectric


200665nm

200845nm

201032nm

SiGe-strainedSilicon

High-kmetal gate

GEN1 GEN2 GEN1 GEN2

1.2-nm SiO2 dielectric(5 atomic layers!)

Silicon substrate

Work-function metal

Low-resistance layer

7M, Al 9M, low-k, Cu

25mm

Typ. reticle size

25mm

625mm2

Front-endof line

(FEOL)

Back-endof line

(BEOL)intel.com




More Moore



201414nm

201710nm

20197nm

TriGate/FinFETand double patterning

GEN1 GEN2

Fin optimization

>10M, ultra low-k

???

Si Substrate

Metal Gate

Si Substrate

Metal Gate

- Triple patterning?- FDSOI?- EUV lithography?- Gate-all-around/nanowire?

- Air gaps?


intel.com




More Moore


intel.com

Cut-off frequency increases,but not exploited due to RF andpower limitations → parallelism

itrs.net

wavelength

isscc.org





More Moore


Cost/transistorimproved also due towafer scaling (capacity)

waferdiameter

8"

12"



intel.com

198019751970 1991 2001 2020?

4"100mm2"

50mm

6"150mm

8"200mm

12"300mm

18"450mm




More Moore


Small is beautiful, but what to dowith so many, inexpensive andsuper fast devices?

Oracle SPARC 4.1-GHz 32-core M7 processor in13-metal 20-nm FinFET TSMC technology

featuring 10-billion transistors

Cost/transistorimproved also due towafer scaling (capacity)






More than Moore

Ubiquitous computing

Diversification oftechnology applications

Not only signalprocessing but:

Power controlWireless communicationsSmart sensing

Multi-domainintegrated systems:

BiologyChemistryPhysics

Medicine

Health

Transport

Energy

Communication

Security

Society trends

Markets

Infotainment

Data

Proce

ssin

g

Comm

unicat

ion

Consum

er

Autom

otive

Indust

rial

Med

ical

Iden

tific

atio

n

Personal healthmonitoring

Drivermonitoring Biosensors

TelematicsSmartkey

Autom. farecollection

Ultra lowpower

Powerefficiency

Hybrid electricdriving

Smartmetering

Smart sensortags

Motor managementCrash free E-blister E-gov

Ultra lowpower

Wirelessconnectivity

Connectedcar

Widebandtuning




More than Moore

Ubiquitous computing

Diversification oftechnology applications

Not only signalprocessing but:

Multi-domainintegrated systems:

New challenges (beside miniaturization):

Application-specific packaging

CMOS technologies with extra process modules Advanced mixed-signal circuit design (A/D/RF/MEMS/power...)

Power controlWireless communicationsSmart sensing

BiologyChemistryPhysics

Medicine




Silicon Wafer

Polished monocrystalline slice

Flat side

p111

<110>

p100

n111

n100

Periodic atomic lattice

CMOS technologies Bipolar technologies

Doping typeCrystalline plane

~5Å lattice spacing




Silicon Wafer


Flat side

Obtained from cylindrical ingotswikipedia.org

Czochralski method

Melting of polysiliconat 1425oC

(99.9999999% purity)

Introduction of the seed

crystal

Beginning ofthe crystal

growth

Crystal pulling at25mm/h

Formed crystal (1m to 2m)

with a residue of melted silicon





Silicon Wafer


Flat side

Obtained from cylindrical ingots

Grinding, slicing and polishing


Diameter grinding Flat grinding Wafer slicing

Edge rounding Two-side lapping Chemical etching

Slurry Head

Surface polishing

200-µm to 750-µm thicknesssBulk, epitaxial, Silicon-on-insulator (SOI)




Wafer Processing

Patterning areasusing photolithography

Resist strip

Positive tone Negative tone

Mask

ResistSubstrate

Resist coat

Exposure

Develop

Processing (e.g. etching)

idesa-training.org




Wafer Processing

1. Vapor prime 2. Spin coat

Resist

3. Soft bake

Mask

UV Light/Laser

4. Alignmentand exposure

5. Post-expsure bake 6. Develop 7. Hard bake 8. Inspection


idesa-training.org




Wafer Processing


Light source

Contact

Lenses

Wafer

Mask

Proximity Scanning projection10µmPhotoresist

Slit

Limited mask lifetimeSimple equipment

5:1 shrinking

Resolution >3µmNo direct contact

Expensive and slowerHigh resolution




Wafer Processing


Stepper equipment

Wafer Stage

InterferometerMirror Set

Alignment Laser

Projection Lens

Wafer

InterferometerLaser

X

Y

Reticle Stage

Reference Mark

Reticle

Light Source




Wafer Processing


Light source Name Wavelength (nm) Application featuresize (µm)

G-line 436 0.50

Mercury Lamp H-line 405

I-line 365 0.35 to 0.25

XeF 351

XeCl 308

Excimer Laser KrF (DUV) 248 0.25 to 0.15

ArF 193 0.18 to 0.13

Fluorine Laser F2 157 0.13 to 0.1




Wafer Processing

Depth Depth Depth

Dens

ity

Dens

ity

Dens

ity

Channeling

Lattice damageDepth control

Lateral effect Shadowing

Adding materials:


Ion implantation




Wafer Processing

Doping applications

Adding materials:


Ion implantation




Wafer Processing

Adding materials:


Ion implantationDiffusionThin-film growingThin-film deposition

Diffusion profile

e.g. Si doping (hours, 800oC to 1200oC)

Quartz tube

Flowcontroller

Resistance-heated furnaceH 2OO 2 N2

Si wafers

e.g. SiO2 oxidation (hours, 700oC to 1200oC)

1.0

Oxidation time (h)

Oxi

de

thic

kn

ess

(m

)

0.10.01

0.1

1.0

(100)

1,100o C wet

1,000o C w

et

900o C w

et

900o C dry1,000o C dry1,100o C dry1,200

o C dry

1,200o C wet

10

10 100




Wafer Processing

Adding materials:


Removing materials:


CleaningEtching

PhotoresistFilmSubstrate

Anisotropic(dry etching)

Isotropic(wet chemical etching)

UndercutMaterial selectivity

e.g. physical/chemicalreactive ion etching (RIE)

for micromachining




Wafer Processing

Adding materials:

Thermal treatment:


Removing materials:


CleaningEtching

AnnealingReflowingAlloying

Chemical-mechanicalplanarization (CMP)

e.g. 6-metal 0.18µm BEOL

Slurry

Polishing Pad

Pressure

Wafer HolderWafer

Membrane

Platen

Slurry Dispenser

Retaining Ring




CNM25 Technology Example

2.5-µm polySi-insulator-polySi (PiP) 1M twin-well CMOS process:

N and P wellsFEOL stages:

4-inch wafers22-mm x 22-mm (484mm2) stepper reticle8-mask layout design

Starting waferGeneral cleaning

Initial pad oxidation (314Å to 415Å)Nitride deposition (1050Å to 1300Å)NTUB photolithography

Photoresist

Wafer processing steps:

SiO2

Si3N4

Si

Si

M. Zabala and A. Sánchez, IMB-CNM(CSIC)






4-inch wafers

8-mask layout designInitial pad oxidation (314Å to 415Å)Nitride deposition (1050Å to 1300Å)NTUB photolithography

Photoresist


Nitride etchingN-well implantation

SiO2

Si3N4

Si

P P

SiO2

Si3N4

Si

P P PP PP PP


22-mm x 22-mm (484mm2) stepper reticle







4-inch wafers

8-mask layout designWafer processing steps:

Well-oxide grow (3500Å to 4500Å)Nitride strippingP-well implantation

Nitride etchingN-well implantation

P P

SiO2

Si3N4

Si

P P PP PP PP

SiO2

B B B B PB PB PBB B

Si









4-inch wafers


Well-oxide grow (3500Å to 4500Å)Nitride strippingP-well implantation

SiO2

B B B B PB PB PBB B

Si

SiP-well N-well

Oxide strippingP-well (7µm) N-well (5µm) drive-in and oxide grow (1500Å to 1750Å)Oxide stripping









4-inch wafers


SiP-well N-well

Oxide strippingP-well (7µm) N-well (5µm) drive-in and oxide grow (1500Å to 1750Å)Oxide stripping

Pad oxidation (150Å to 225Å)Nitride deposition (1050Å to 1300Å)GASAD photolithography

SiP-well N-well

SiO2

Si3N4

Active areas









4-inch wafers


Pad oxidation (150Å to 225Å)Nitride deposition (1050Å to 1300Å)GASAD photolithography

Nitride etchingField implantation

SiP-well N-well

SiO2

Si3N4

SiP-well N-well

B B B B PB PB PBB B B B

SiO2

Si3N4

Active areas









4-inch wafers


LOCOS* (10000Å to 11200Å)Nitride etching

Nitride etchingField implantation

SiP-well N-well

B B B B PB PB PBB B B B

SiO2

Si3N4

SiP-well N-well

SiO2

*LOCal Oxidation of Silicon

Active areas









4-inch wafers


*LOCal Oxidation of Silicon

Active areas

LOCOS* (10000Å to 11200Å)Nitride etching

SiP-well N-well

SiO2

Sacrifitial oxidation (850Å to 1050Å)Gate implantationPre-poly cleaning

SiP-well N-well

SiO2

B B PB B B PB









4-inch wafers


Active areas

Sacrifitial oxidation (850Å to 1050Å)Gate implantationPre-poly cleaning

SiP-well N-well

SiO2

B B PB B B PB

PiP capacitor

PolySi deposition (3200Å to 3800Å)N-type doping

SiP-well N-well

SiO2

POCl3 POCl3 POCl3 POCl3 POCl3 POCl3 POCl3 POCl3

PolySi









4-inch wafers


Active areasPiP capacitor

PolySi deposition (3200Å to 3800Å)N-type doping

POLY0 photolithography

SiP-well N-well

SiO2

POCl3 POCl3 POCl3 POCl3 POCl3 POCl3 POCl3 POCl3

PolySi

SiP-well N-well

SiO2

PolySi









4-inch wafers



POLY0 photolithography

SiP-well N-well

SiO2

PolySi

SiP-well N-well

SiO2

PolySi

PolySi etchingSacrifitial oxide stripping









4-inch wafers



SiP-well N-well

SiO2

PolySi

PolySi etchingSacrifitial oxide stripping

MOS gate

SiP-well N-well

SiO2

Gate-oxide growing (340Å to 390Å)









4-inch wafers


Active areasPiP capacitorMOS gate

SiP-well N-well

SiO2

Gate-oxide growing (340Å to 390Å)

PolySi deposition (4500Å to 5100Å)POLY1 photolithography

SiP-well N-well

SiO2







PolySi deposition (4500Å to 5100Å)POLY1 photolithography

SiP-well N-well

SiO2


4-inch wafers


PolySi etching

SiP-well N-well

SiO2


Active areasPiP capacitorMOS gate







PolySi etching

SiP-well N-well

SiO2

NPLUS photolithographyN-type doping


4-inch wafers


P P P

SiP-well N-well

SiO2


Active areasPiP capacitorMOS gateMOS source and drain







NPLUS photolithographyN-type doping

P P P

SiP-well N-well

SiO2


4-inch wafers


P-type dopingB B PB

B B PB

SiP-well N-well

SiO2









P-type dopingB B PB

B B PB

SiP-well N-well

SiO2


4-inch wafers


*TEtraethyl OrthoSilicate

TEOS* deposition (12000Å to 13000Å)N++(1µm) and P++(3µm) D/S diffusion

SiP-well N-well

SiO2



Interlevel oxideBEOL stages:







TEOS* deposition (12000Å to 13000Å)N++(1µm) and P++(3µm) D/S diffusion

SiP-well N-well

SiO2


4-inch wafers


*TEtraethyl OrthoSilicate

WINDOW photolithography

SiP-well N-well

SiO2




Contacts







WINDOW photolithography

SiP-well N-well

SiO2


4-inch wafers



Active areasPiP capacitorMOS gateMOS source and drain Al metalization

METAL photolithography

SiP-well N-well

SiO2

Al


ContactsMetal







Al metalizationMETAL photolithography

SiP-well N-well

SiO2

Al


4-inch wafers


Al etchingAl

SiP-well N-well

SiO2




ContactsMetal







Al etchingAl

SiP-well N-well

SiO2



4-inch wafers

8-mask layout design

Oxidation (4000Å)Nitride deposition (4000Å)CAPS photolithography

SiO2

N-wellP-wellSi

Al Si3N4

N and P wellsActive areas

FEOL stages:

PiP capacitorMOS gateMOS source and drain


ContactsMetalPassivation and pads







Oxidation (4000Å)Nitride deposition (4000Å)CAPS photolithography

SiO2

N-wellP-wellSi

Al Si3N4


N and P wellsActive areas

FEOL stages:


PiP capacitorMOS gateMOS source and drain


ContactsMetalPassivation and pads

4-inch wafers

8-mask layout design

Nitride etchingOxide etching

Wire-bonding pad







Modern Technologies

Advanced MOSFETdevice structure

SpacerSalicidePoly gate

Gate dielectricD/S extension

Salicide

HaloHeavily doped D/SChannel & well profiles

idesa-training.org




Modern Technologies


Device isolationLocal Oxidation

of Silicon

LOCOS

Shallow Trench

Isolation

STI

Bird's beak

Si

Si3N4

SiO2

Pad oxide growth + nitride deposition Pattern and etch Si3N4 and SiO2

Si3N4

SiSiO2

Si3N4

SiSiO2

Si3N4

Trench etch into Si

SiO2 depth= ~ 350 nm;“shallow”

Si3N4

Si

SiO2

SiO2

Deposition of trench filling oxide(No thermal growth!)

SiSiO2

Si3N4

Oxide CMP polish step with stop on nitride

SiSiO2

Field oxide recess (HF dip)

Removal of nitride layer (H3PO4)

idesa-training.org




Modern Technologies


Device isolation

Cu interconnections metal

oxide

oxide

1) metal deposition

2) etching of metal lines

3) oxide gapfill + oxide CMP

metal

oxide

1) etching of oxide trenches

2) metal deposition

3) metal CMP

Lower resistivityHigher melting pointLower thermalexpansionLower electromigration

Classical Al metallisation Damascene Cu metallisation

idesa-training.org




Mixed-Signal Technology Modules

shallow trenchisolation (STI)

P-well

P-sub

N-well

P+P+ p-p-n-n- N+N+P+ N+

Deep N-wellP-well N-well

P+P+ p-p-n-n- N+N+P+ N+

BS G DD G S B B S G DD G S B

(half circuit)

Gate-bootstrapping in SC circuits(e.g. input samplers, charge pumps)

Twin vs triple well

Isolation against substrate noise

CMOS process options for each IC application:





CMOS process options for each IC application:Twin vs triple well

Several MOSFET threshold-voltage families





CMOS process options for each IC application:Twin vs triple well


Metal-insulator-metal (MiM) and fringe linear capacitors

High-resistance polySi (HIPO) linear and low-TC resistors

Thick top metal for high-Q RF inductors

4M fringecapacitor

Triple MIMcapacitor

Differentialinductor





CMOS process options for each IC application:

Many modules = higher mask/process costs + difficult circuit design migration

Twin vs triple well


Metal-insulator-metal (MiM) and fringe linear capacitors

High-resistance polySi (HIPO) linear and low-TC resistors

Thick top metal for high-Q RF inductors

Linear varactors for continuous RF tuning

High-voltage (HV) and LDMOS transistors for power management

Non-volatile memory (NVM) for chip ID, configuration, tunning...

Anti-reflective coating and optimum doping profiles for CMOS image sensors (CIS)

Lateral and vertical bipolar transistors for bandgap references

P-

P-sub

N-

N+P+

P-

P+

Anti-reflectivecoating (ARC)




Hybrid-Packaging Alternatives

Classic wire-bonding approach:

Monolithic solution (signal integrity, production)

Sensor needs to be CMOS compatible

Area costs

Wire-bonding costs for large arrays

CMOSSensor

Package/PCB





Classic wire-bonding approach:

Monolithic solution (signal integrity, production)

Sensor needs to be CMOS compatible

Area costs


Bump-bonding flip-chip:

Heterogeneous sensor/CMOS technologies

Sensor area can be reused for circuits

Back-side sensing


CMOSSensor

Package/PCB





3D stacking with through-Silicon vias (TSV):

Heterogeneous sensor/CMOS technologies

Sensor area can be reused for circuits

Front-side sensing

Wire-bonding free

CMOS

Package/PCB

Redistributionlayers (RDL) side

Sensor

Standardwafer

thickness

CMOS side

Deepreactive-ion

etching(DRIE)

Height/diameter < 20

pF-range parasitic capacitance

< 1-Ω series resistance

Typ. diameter 50μm to 100μm





3D stacking with through-Silicon vias (TSV):

Redistributionlayers (RDL) side

Standardwafer

thickness

CMOS side

Deepreactive-ion

etching(DRIE)

TSV downscaling by wafer chemical-mechanical polishing (CMP):

imec.be

Height/diameter < 20

pF-range parasitic capacitance

< 1-Ω series resistance

Typ. diameter 50μm to 100μm




CMOS Technologies1




Lab Proposal5




IC Design Scenario

Synthesis vs analysis:

I R mVppCMR Upper >4 V

Lower <1OR >3 VppVof f ±σ <10 mVrmsPd Vin = 2.5V <1.5 mWGDC >60 dBCMRRDC >50 dBPSRRDC + >50 dB

− >50SR + >1.5 V/ µs

− >1.5ts(1%) Vout = 2 → 3V <1500 ns

Vout = 3 → 2V <1500fmax Vout = OR KHzTHD Vout = OR/ 2@10KHz <1 %BW −3dB HzGBW >1 MHzφm >50 degVnieq 100Hz to 10MHz <1 mVrms

Area <0.025 mm2

Synthesis

SpecificationsSchematics Layout

Analysis

Synthesis

Analysis

Circuit Physical

vs

modeling -cause/effect -

simplification -multi-disciplinar -

- exhaustive- high speed - high precision- large database

EDA tools do not design ICs!




Analog vs Digital

If it can be done by digital, don't use analog!

Analog IC design is complex...

Background in physics, electronics, information and control theory,signal processing, communications

High dependence from technology

Modeling skills Complex EDA tools

Analogway

Digitalway

Variety of state-of-the-art solutionsWhat isthis?




Analog vs Digital


...but still necessary!





Variety of state-of-the-art solutions

μP μC

DSPFPGAMemory

ADCDAC AGC

PLL

Reference

VCO

Mixer

LNA

PA

FilterPreamp

Powermanager

Transducers

Supp

ly Comm

unications




Analog vs Digital


Most modern ICs arereally mixed-signal

...but still necessary!





Variety of state-of-the-art solutions

μP μC

DSPFPGAMemory

ADCDAC AGC

PLL

Reference

VCO

Mixer

LNA

PA

FilterPreamp

Powermanager

Transducers

Supp

ly Comm

unications

ImagerTouchscreen

Audioinput/output

Accelerometer

RFfrontend

Batterymanager

Temperaturesensing

MagnetometerLight sensing




IC vs PCB

What can analog IC design offer compared to PCB?

Good Bad




IC vs PCB

Good Bad

Small size and high density

Complex systems

High speed operation

Low power consumption

Heterogeneous SoC (A/D/RF/MEMS/Power)

Low production costs





IC vs PCB

Small size and high density Low observability/controllability

Complex systems

High speed operation

Low power consumption

Heterogeneous SoC (A/D/RF/MEMS/Power)

Low production costs

Few device primitives

Technology variability(process and mismatching)

Complex modeling

High design costs(EDA/personnel)

High prototyping costs

Long design cycles

Good Bad





IC Flavors

Each application may require a different IC solution:

Full-customDensity

FlexibilityPerformanceDesign time

Prototype costsEDA tools

Mixed-modeTarget volume

Hand-drawn geometryAll layers customized

HighA and D

Application-specific IC(ASIC) result

cnm25modn(w=28,l=6,mx=4,my=2,common_d=False,common_g=False,common_s=True)




IC Flavors


Full-custom Macro-cellDensity




Automated routingAll layers customized

HighA and D A and D

High

Predefined macro blocks (ADC, memory...)

Still an ASIC

Magali 65-nm SoC for 4G communication with 22 IPs




IC Flavors






Regular floorplanAll layers customized

HighA and D A and D

High

Standard-cell

DHigh

I/Opad ring

Row of cells

Routing

Gate level cells + automated routing

Still an ASIC




IC Flavors






Only routing layers customized

HighA and D A and D

High

Standard-cell

DHigh

Gate-array

DMedium

Pre-built transistors/gates/IPs

Structured ASIC




IC Flavors






Programmable logic blocksProgrammable routingNot an ASIC

HighA and D A and D

High

Standard-cell

DHigh

Gate-array

DMedium

FPGA

D (A)Low

AlteraCyclone III




IC Flavors





Mixed-modeTarget volume High

A and D A and DHigh

Standard-cell

DHigh

Gate-array

DMedium

FPGA

D (A)Low




Full-Custom Design

WidthLengthMultiplicity

non-linear!

Fixed CMOS technology:

Analog design space:

Device biasingDevice horizontal sizing

Materials and processesVertical dimensions p-well n-well

n+p+p+n+n+p+

Circuit topology




Full-Custom Design

Number of turnsInner DiameterSpacingWidth

other device cases:

Fixed CMOS technology:



Materials and processesVertical dimensions p-well n-well

n+p+p+n+n+p+

Circuit topology




Full-Custom DesignFixed CMOS technology:



Materials and processesVertical dimensions

Circuit topology

Analog IC designoptimization rules

Figure of Merit (FoM)

Performance

Silicon area (costs, packaging...)Power consumption (lifetime, range...)

Resources

http://www.stanford.edu/~murmann/adcsurvey.html1 E-01

1 E+00

1 E+01

1 E+02

1 E+03

1 E+04

1 E+05

1 E+06

1E+07

10 20 30 40 50 60 70 80 90 100 110 120

P/f

snyq

[pJ]

SNDR @ fin,hf [dB]

ISSCC 2013VLSI 2013ISSCC 1997-2012VLSI 1997-2012FOMW=10fJ/conv-stepFOMS=170dB

B. Murmann, ADC Performance Survey

e.g. ADC circuits




System ComplexityAnalog IC designers deal with several hierarchy and abstraction levels

electrochemicalsmart sensor

e.g.





Physical(FE simulators)

Devices

Circuits

Systems

Electrical(SPICE)

Functional(Verilog/VHDL/SystemC-AMS, XSpice, Simulink)

Bottomup

Topdown

switch (action) case SAMPLING: /* Sampling action */ OUTPUT_CHANGED(out) = FALSE; *inp_mem = inp; break; case QUANTIZATION: /* Quantization action */ OUTPUT_CHANGED(out) = TRUE; if (*inp_mem>inp_th) out = ONE; OUTPUT_DELAY(out) = t_rise; else out = ZERO; OUTPUT_DELAY(out) = t_fall; OUTPUT_STATE(out) = out; OUTPUT_STRENGTH(out) = STRONG; *out_mem = out; break; case HOLDING: /* Holding action */ OUTPUT_CHANGED(out) = FALSE;





switch (action) case SAMPLING: /* Sampling action */ OUTPUT_CHANGED(out) = FALSE; *inp_mem = inp; break; case QUANTIZATION: /* Quantization action */ OUTPUT_CHANGED(out) = TRUE; if (*inp_mem>inp_th) out = ONE; OUTPUT_DELAY(out) = t_rise; else out = ZERO; OUTPUT_DELAY(out) = t_fall; OUTPUT_STATE(out) = out; OUTPUT_STRENGTH(out) = STRONG; *out_mem = out; break; case HOLDING: /* Holding action */ OUTPUT_CHANGED(out) = FALSE;

Mixing different abstraction levels during design

Simulation speed upStudy of circuitnon-ideal effectsMulti-level and multi-domainsimulation needed (singleengine or glue approach)




ASIC Development

Alignment with foundry fixed run calendar

Typical project scheduling:

M0

Specs Design Integration Testing

Long design iterations (typ. 6M)

First complete prototype >18M

Completesystem-on-chip (SoC)

Custom librarytest chips

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24




CMOS Technology Costs

Stepperreticle

25mm

25mm

1 layer/mask36-mask set

Mask costs: 100 k€Die size: < 625 mm2

Samples: > 50 die/waferProcessing costs: 2 k€/wafer

Intended for full production (> 200 wafer/year)

layer#1depending on

process modules!

Full-mask regular run

Wafer map∅ 200mm

e.g. 0.15-μm 1P6M CMOS technology






Stepperreticle

25mm

25mm


Die size: > 4 mm2

Samples: < 100 dieMask and processing costs: 1 k€/mm2

Intended for prototyping

Multi-project wafer (MPW) run

design#N

design#1

Wafer map∅ 200mm







Multi-project wafer (MPW) runMulti-layer mask (MLM) engineering run

Stepperreticle

12.5mm

12.5mm


layer#1

4-MLM


Samples: > 200 die/waferProcessing costs: 2 k€/wafer (6-wafer lots)

Intended for small series (< 100 wafer/year)

#2

#3 #4

Wafer map∅ 200mm








9-MLM

Stepperreticle

8.3mm

8.3mm


layer#1


Samples: > 450 die/wafer Processing costs: 2 k€/wafer (6-wafer lots)

Intended for small series (< 100 wafer/year)

#4 #6#5

#3#2

#7 #9#8

Wafer map∅ 200mm








Wafer-scale stitching run


Stepperreticle

25mm

25mm


Wafer map∅ 200mm

Mask costs: 100 k€Die size: 150x150 mm2

Samples: 1 die/wafer Processing costs: 2 k€/wafer

Intended for limited series

block #2 #3#1

#5 #6#4

#8 #9#7

Low yield (acceptable for imagers)

imagesensors.org

singlechip




CMOS Technologies1




Lab Proposal5




Bulk Enhancement MOSFETIntrinsic and extrinsic model parts

GB S

p-well

n+n+p+

D





GB S

p-well

n+n+p+

D

. MODEL MY_NMOS BSIM3V3 TYPE=N+ VERSION=3.2 PARAMCHK=1+ NSUB=2.161E+19 NCH=1.280E+17 XJ=1.500E-07 LINT=7.639E-04+ WINT=3.669E-04 LL=0 LLN=0 LW=0 LWN=0 LWL=0 WL=-1.253E-10+ WLN=1 WW=-2.595E-07 WWN=4.475E-01 WWL=0 DWG=0 DWB=0+ TOX=3.800E-08 TOXM=3.800E-08 XT=1.000E-07 RDSW=3.580E+02+ PRWB=6.678E-03 PRWG=4.740E-04 WR=4.148E-01 + VTH0=7.874E-01 K1=1.233E+03 K2=-6.791E-02 K3=8.227E+03+ K3B=-5.071E-01 W0=2.500E-06 NLX=0 DVT0=5.820E+00 DVT1=5.168E-01+ DVT2=-2.594E-01 DVT0W=0 DVT1W=5.300E+06 DVT2W=-3.200E-02+ A0=8.010E-01 B0=0 B1=0 A1=0 A2=1 AGS=1.006E-01 KETA=-1.385E-02+ MOBMOD=1 U0=6.020E+02 VSAT=1.746E+08+ UA=9.395E-07 UB=2.828E-15 UC=5.191E-08+ DROUT=5.600E-01 PCLM=3.178E+03 PDIBLC1=4.811E+03+ PDIBLC2=8.600E-03 PDIBLCB=0 PSCBE1=4.240E+08+ PSCBE2=1.000E-05 PVAG=0 DELTA=1.000E-02+ CDSC=2.953E-02 CDSCB=7.380E-03 CDSCD=-2.864E-03+ NFACTOR=6.727E-01 CIT=0 VOFF=-6.277E-02+ DSUB=5.600E-01 ETA0=0 ETAB=-1.653E-01+ CAPMOD=3 DWC=3.669E-04 DLC=0 CLC=1.000E-07+ CLE=6.000E-01 CF=0 ELM=2 ACDE=1 MOIN=15+ NOFF=1 VOFFCV=0 XPART=6.000E-01 LLC=0+ LWC=0 LWLC=0 WLC=-1.253E-10 WWC=-2.595E-07 WWLC=0+ ALPHA0=2.725E-03 ALPHA1=-7.804E-01 BETA0=3.180E+01+ JS=1.000E-04 JSW=0 NJ=1 IJTH=1.000E-01+ CJ=5.000E-04 MJ=5.000E-01 PB=1+ CJSW=5.000E-10 MJSW=3.300E-01 PBSW=1+ CJSWG=5.000E-10 MJSWG=3.300E-01 PBSWG=1+ CGSO=0 CGDO=0 CGBO=0 CGSL=0 CGDL=0 CKAPPA=6.000E-01+ TNOM=27 KT1=-1.100E-01 KT1L=0 KT2=2.200E-02 AT=3.300E+04+ UA1=4.310E-09 UB1=-7.610E-18 UC1=-5.600E-11 PRT=0 UTE=-1.5+ XTI=3 TPB=0 TPBSW=0 TPBSWG=0 TCJ=0 TCJSW=0 TCJSWG=0+ NOIMOD=1 KF=1.000E-17 AF=1.5 EF=1.5 NOIA=2.000E+29+ NOIB=2.000E+29 NOIC=2.000E+29 EM=4.100E+07+ XL=0 XW=0 PK1=1.711E-01 PK2=-6.688E-02+ PUA=6.246E-04 PUB=-3.418E-12 LUC=1.519E-05+ PUC=-5.063E-05 PAGS=2.532E-01 PRDSW=-1.071E+04+ WVSAT=0 PVSAT=-1.800E+05 PVTH0=-1.644E-01

Analytical (physical) vsnumerical (fitting) modeling





Accurate results from electrical simulationToo complex for hand design!

GB S

p-well

n+n+p+

D

. MODEL MY_NMOS BSIM3V3 TYPE=N+ VERSION=3.2 PARAMCHK=1+ NSUB=2.161E+19 NCH=1.280E+17 XJ=1.500E-07 LINT=7.639E-04+ WINT=3.669E-04 LL=0 LLN=0 LW=0 LWN=0 LWL=0 WL=-1.253E-10+ WLN=1 WW=-2.595E-07 WWN=4.475E-01 WWL=0 DWG=0 DWB=0+ TOX=3.800E-08 TOXM=3.800E-08 XT=1.000E-07 RDSW=3.580E+02+ PRWB=6.678E-03 PRWG=4.740E-04 WR=4.148E-01 + VTH0=7.874E-01 K1=1.233E+03 K2=-6.791E-02 K3=8.227E+03+ K3B=-5.071E-01 W0=2.500E-06 NLX=0 DVT0=5.820E+00 DVT1=5.168E-01+ DVT2=-2.594E-01 DVT0W=0 DVT1W=5.300E+06 DVT2W=-3.200E-02+ A0=8.010E-01 B0=0 B1=0 A1=0 A2=1 AGS=1.006E-01 KETA=-1.385E-02+ MOBMOD=1 U0=6.020E+02 VSAT=1.746E+08+ UA=9.395E-07 UB=2.828E-15 UC=5.191E-08+ DROUT=5.600E-01 PCLM=3.178E+03 PDIBLC1=4.811E+03+ PDIBLC2=8.600E-03 PDIBLCB=0 PSCBE1=4.240E+08+ PSCBE2=1.000E-05 PVAG=0 DELTA=1.000E-02+ CDSC=2.953E-02 CDSCB=7.380E-03 CDSCD=-2.864E-03+ NFACTOR=6.727E-01 CIT=0 VOFF=-6.277E-02+ DSUB=5.600E-01 ETA0=0 ETAB=-1.653E-01+ CAPMOD=3 DWC=3.669E-04 DLC=0 CLC=1.000E-07+ CLE=6.000E-01 CF=0 ELM=2 ACDE=1 MOIN=15+ NOFF=1 VOFFCV=0 XPART=6.000E-01 LLC=0+ LWC=0 LWLC=0 WLC=-1.253E-10 WWC=-2.595E-07 WWLC=0+ ALPHA0=2.725E-03 ALPHA1=-7.804E-01 BETA0=3.180E+01+ JS=1.000E-04 JSW=0 NJ=1 IJTH=1.000E-01+ CJ=5.000E-04 MJ=5.000E-01 PB=1+ CJSW=5.000E-10 MJSW=3.300E-01 PBSW=1+ CJSWG=5.000E-10 MJSWG=3.300E-01 PBSWG=1+ CGSO=0 CGDO=0 CGBO=0 CGSL=0 CGDL=0 CKAPPA=6.000E-01+ TNOM=27 KT1=-1.100E-01 KT1L=0 KT2=2.200E-02 AT=3.300E+04+ UA1=4.310E-09 UB1=-7.610E-18 UC1=-5.600E-11 PRT=0 UTE=-1.5+ XTI=3 TPB=0 TPBSW=0 TPBSWG=0 TCJ=0 TCJSW=0 TCJSWG=0+ NOIMOD=1 KF=1.000E-17 AF=1.5 EF=1.5 NOIA=2.000E+29+ NOIB=2.000E+29 NOIC=2.000E+29 EM=4.100E+07+ XL=0 XW=0 PK1=1.711E-01 PK2=-6.688E-02+ PUA=6.246E-04 PUB=-3.418E-12 LUC=1.519E-05+ PUC=-5.063E-05 PAGS=2.532E-01 PRDSW=-1.071E+04+ WVSAT=0 PVSAT=-1.800E+05 PVTH0=-1.644E-01

Process

Thresholdvoltage

Mobility

Outputresistance

Subthreshold

Chargemodel

Substrate

Junctiondiode

Overlap cap.Thermal

modelNoisemodel

Scaling

Analytical (physical) vsnumerical (fitting) modeling

SPICE




Classic large signal I/V model:

Bulk Enhancement MOSFET

G

S

D

Linearmode

Saturationregion

Channelcut-off

Nonlinear

Pinch-offvoltageCurrent factor

Channel length modulation (CLM):negligible for large signal, but critical in small signal

CLM




Classic large signal I/V model:


G B

S

D

Simple enough for hand design

Body effect in stacked circuits?

Asymmetrical D/S model!

Subthreshold operation?

Single expression wanted forall regions with continuousderivatives (small signal)...

or ?

Body effectcoefficient

Pinch-offvoltageCurrent factor

Nonlinear

Channel length modulation (CLM):negligible for large signal, but critical in small signal




EKV large signal I/V model:


G

B

SD

Subthreshold slope(1<n<2)

EnzKrummenacherVittoz

http://ekv.epfl.ch

Forward Reverse

Specific current Pinch-off voltage

Inversion coefficient

Weak inversion(subthreshold)

Cond

uctio

nSa

tura

tion

(for

ward

)

Strong inversion




EKV large signal I/V model:


G

B

SD

Simple enough for hand design

Symmetrical D/S expressions

Single expression fromstrong to weak inversion andfrom conduction to saturation

EnzKrummenacherVittoz

http://ekv.epfl.ch

Continuous derivatives forsmall signal parameters

Explicit body effect

Strong inversionModerate

Weak

Leakage

Forward saturation example(neglecting CLM):




Classic small signal transconductance model:


G B

S

DSmall signal

increments only

Non-linearoperating point

Linearequivalent circuit

G

D

BS

Analog circuits biased throughcurrent sources → op as afunction of drain current






G B

S

DSmall signal

increments only



G

D

BS

Analog circuits biased throughcurrent sources → op as afunction of drain current






G B

S

DSmall signal

increments only



G

D

BS

Asymmetrical parameters andnon-explicit expressions...




EKV small signal transconductance model:


Small signalincrements only



G

D

BS

G

B

SD

Weak inversion (subthreshold)

Cond

uctio

nSa

tura

tion

(for

ward

)

Strong inversion




EKV small signal transconductance model:





G

D

BS

G

B

SD

Equivalence between models: Continuty between operating regions:

Stronginversion

Moderate

WeakBest powerefficiency




Quasi-static transcapacitance model:



G

B

SD

Input only elements:

Stronginversion

Moderate

Weak

G

B

SD

Non-reciprocal!

(e.g. n = 1.3)

Conduction Fwd. Saturation

Gate oxide cap.3.9 (SiO2)




Small signal noise model:


Thermalagitation

Thermal (white) component:

Power spectral density (PSD) statistics:

OS interfacetrapping

Flicker (pink) component:

Memoryeffect

Technology dependent(NMOS >> PMOS)

Uncorrelated phenomena:

ThermalFlicker

-10dB/dec




Small signal noise model:


Thermalagitation

Thermal (white) component:

OS interfacetrapping

Flicker (pink) component:

Noise-aware analog IC design: Signal

full scale

Low-powercircuit design

Signal-to-noiseratio

DynamicRange Power

Circuit designscalability

DynamicRange Area

Memoryeffect

Technology dependent(NMOS >> PMOS)




Bulk Enhancement MOSFETExtrinsic D/S diffusion diodes:

GB S

p-well

n+n+p+

D

n+

p-well

Bottomplate

Sidewalls

Geometry parameters:Reverse leakage current:

Depletion capacitance:




EKV Model ExtractionSequential methodology to minimize errors:

W/L array oftransistors toadjust modelscalability

, ,

VP vs. VG

VTO GAMMA PHI

ID vs. VG

KP , E0

WIDELONG

specific current

measurement

VP vs. VGLETA

,

ID vs. VD

UCRIT LAMBDA

WIDESHORT

VP vs. VG

WETA

NARROWLONG

PRELIMINARYEXTRACTION

Extraction of

DL , DW , RSHfrom severalgeometries

final checkand fine tuning

NARROWSHORT

VP vs. VGLETA

VP vs. VG

LETA , Q0 , LK

L

IB vs. VG

IBA , IBB , IBN

specific current

measurement

specific current

measurement

WideLong

Narrow Short Wide Short

NarrowLong

http://dx.doi.org/10.1109/ICMTS.1996.535636M.Baucher et al., An Efficient Parameter Extraction Methodologyfor the EKV MOST Model, IEEE ICMTS, Mar 1996




EKV Model ExtractionSequential methodology to minimize errors:

W/L array oftransistors toadjust modelscalability

, ,

VP vs. VG

VTO GAMMA PHI

ID vs. VG

KP , E0

WIDELONG

specific current

measurement

VP vs. VGLETA

,

ID vs. VD

UCRIT LAMBDA

WIDESHORT

VP vs. VG

WETA

NARROWLONG

PRELIMINARYEXTRACTION

Extraction of

DL , DW , RSHfrom severalgeometries

final checkand fine tuning

NARROWSHORT

VP vs. VGLETA

VP vs. VG

LETA , Q0 , LK

L

IB vs. VG

IBA , IBB , IBN

specific current

measurement

specific current

measurement

WideLong

Narrow Short Wide Short

NarrowLong





EKV Model Extractione.g. specific-current estimation:


Weakinversion

Stronginversion




EKV Model Extractione.g. specific-current estimation:


Weakinversion

Stronginversion

e.g. threshold-voltage estimation:

GAMMA

PHI

IB

VG

VS=VP




Passive ComponentsCoplanar capacitors:

Overlap + fringing capacitance:

Low-ohmicconnectorsInter-layer

thin insulator

Top plate

Typ. available CMOS structures:

Voltagelinearity

MOSPiP or MiM

Temp.indep.

>11~10

PolySi-insulator-PolySi

Bottom plate

Notstretchable!

Electricalpermittivity

[F/m]

Processdependent

Metal-insulator-Metal Sandwitch techniques...http://dx.doi.org/10.1109/EDL.1982.25610C.P.Yuan and T.N.Trick, A Simple Formula for the Estimation of the Capacitance of Two-Dimensional Interconnects in VLSI Circuits, IEEE Electron Device Letters, 3(12):391-3, Dec 1982




Passive ComponentsSerpentine resistors:

Square resistance:

Low-ohmicconnectors

Highly resistivestripes

Notstretchable!

Volumeresistivity

[Ωm]

Processdependent

Designaspect ratio

Typ. available CMOS structures:

Voltagelinearity

WellDiffusion

PolySiMetal

Temp.indep.

~1k~100~10~1m

HiPo 1k~10k

HighlyresistivePolySi




Statistical Gaussian model:

Technological Mismatching

GeneralPelgrom Law

e.g. dopantnon-uniformity

e.g. thicknessgradient

http://dx.doi.org/10.1109/JSSC.1989.572629M.J.M.Pelgrom et al., Matching Properties of MOS Transistors, IEEE Journal Solid-State Circuits, 24(5):1433-9, Oct 1989

CMOS processdependent

Standarddeviation

Deviceparameter

P ?








e.g. MOS differential pair:

M1 M2

small-signaluncorrelatedphenomena



GeneralPelgrom Law

Standarddeviation







StronginversionModerateWeak

M1 M2


Typically, VTH mismatch is dominant...

Best areaefficiencye.g. MOS current mirror: small-signal

uncorrelatedphenomena



GeneralPelgrom Law

Standarddeviation








0 10 20 30 40 50 600

5

10

15

20

25

30

35

40

45

50

tox [nm]

A VTH

N[m

Vµm

]

NMOS VTH mismatching: 0.8mVµm × tox[nm]

Analog design scalability?

Precision Area

2.5µm

Rule of thumb:

2.5µm

2.0µm 2.0µm

1.6µm

1.2µm

1.0µm

0.8µm

0.7µm

0.6µm

0.35µm

0.30µm0.25µm

0.18µm

0.12µm

Depletionlayer



GeneralPelgrom Law

Standarddeviation




CMOS Technologies1




Lab Proposal5




Universal Analog Building BlockOperational voltage amplifier (OpAmp)

Analog signal processing functions

e.g. I/V converter

e.g. Instrumentation amplifier

Non-linear, temp. uncompensated...

As far as OpAmpgain and bandwidth

are large enoughWantedperformance

Single endedcase study




Universal Analog Building BlockOperational voltage amplifier (OpAmp)

Analog signal processing functions

Non-linear, temp. uncompensated...

As far as OpAmpgain and bandwidth

are large enoughWantedperformance

e.g. switched capacitor (SC) filters

Single endedcase study

CMOS OpAmp known as operationaltransconductance amplifier (OTA)




OpAmp Performance Parameters

Commonmodeinput

Differentialinput

Input range

Output range

Equivalent input offset

Open loop differential DC gain

Large signal static figures (ideal):

Systematic

Open-loop differential DC voltagetransfer curve (VTC) at constant CM:

Mismatchingsupply voltage

Finite





Input common-mode DC sweep:

Common mode range

Input range

Output range

Equivalent input offset


Large signal static figures (ideal):

Depending on feedback topology!






Bandwidth

Gain-bandwidth product

Phase margin

AC Bode diagram:

Equivalent input noise

Small signal dynamic figures (ideal):

Frequency

-20dB/dec

-40






Bandwidth


Phase margin

AC Bode diagram:



Common mode rejection ratio

Frequency

-20dB/dec

-40






Bandwidth


Phase margin

AC Bode diagram:



Common mode rejection ratio

Power supply rejection ratio

Frequency

-20dB/dec

-40





Large signal dynamic figures (ideal) Transient step response:Settling time

Time

Amplitude independance (linear behaviour)





Large signal dynamic figures (ideal) Transient step response:

Slew rate

Settling time

Time


Time

Amplitude dependence (non-linear behaviour)

Finitepower!

Slope limit[V/s]





Large signal dynamic figures (ideal)

Maximum frequency

Transient harmonic response:

Slew rate

Settling time

Time

Amplitude dependence (non-linear behaviour)

Finitepower!


TimeSmall/large

signal boundary





Large signal dynamic figures (ideal)

Maximum frequency

Total harmonic distortion

Transient harmonic response:

Slew rate

Settling time

Time

Amplitudecompression

Slopelimitation

Both static and dynamic non-linearity = signal distortion




Electricalsimulation

Designmodification

OpAmp FoMs

Quantitative design comparisonUseful in circuit optimization:

Optimizationrule

Costevaluation





Designmodification

OpAmp FoMs

Quantitative design comparison Too many performance parameters!Useful in circuit optimization:

Application specific FoMs...

Optimizationrule

Costevaluation

PerformanceResources




CMOS Technologies1




Lab Proposal5




My OpAmp in CNM25

Two-stage MillerOpAmp design caseSimple 2.5μm 2P2MCMOS technology (CNM25)

M2

M8

M1Vin-

M3 M4 M6

M7

Ccomp

M5

Vin+

Vout

VSS

VDD

+

-

Vin+

Vin-

VDD

VSS

Vout

G G

G

B B

B

D S D S

D S

B T

B T

NTUB

GASADPOLY0

POLY1NPLUS

WINDOW METAL

METAL2

VIA

p-well n-welln+p+p+

n+n+p+

G

B

D S




My OpAmp in CNM25I R mVppCMR Upper >4 V

Lower <1OR >3 VppVof f ±σ <10 mVrmsPd Vin = 2.5V <1.5 mWGDC >60 dBCMRRDC >50 dBPSRRDC + >50 dB

− >50SR + >1.5 V/ µs

− >1.5ts(1%) Vout = 2 → 3V <1500 ns

Vout = 3 → 2V <1500fmax Vout = OR KHzTHD Vout = OR/ 2@10KHz <1 %BW −3dB HzGBW >1 MHzφm >50 degVnieq 100Hz to 10MHz <1 mVrms

Area <0.025 mm2


OpAmp circuit optimzation

Full-custom analogCMOS layout

My schematic

My layout

M2

M8

M1

M3 M4 M6

M7M5

Choose one outof these three FoM!

Initial specsElectrical

simulation

Circuitoptimization

Physicalverification

Maskdesign




My OpAmp in CNM25


Freeware and multi-OS(MS Windows, Linux)EDA tools

Work at homeand tutorial at lab...

Physicaldesign

SpiceOpus

Glade

SpiceOpus

GladeCircuit-levelschematic


PCell-based andnetlist-driven layout

Design rulechecker

Layout versusschematic

3D parasiticsextraction

Post-layoutsimulation

Tape-out

Device symbolsand netlisting rules

Process andmismatchdevice models

Physical design kit(PDK)

PCell layoutgeneration code

Layer boolean opsand rules script

Technologycross section

Parasitics models

Layer map table

PCell extractioncode andmatching rules

fastcap

gemini

python

python

Glade

Mask makingWafer processingScreeningDicingPackaging

ICfunctionalspecifications

ICprototypesamplesSemiconductor

Foundry

Schematicdesign

OpAmp circuit optimzation

Full-custom analogCMOS layout

http://www.cnm.es/~pserra/uab/damics/lab.html

1. introduction to the design of analog integrated circuitspserra/uab/damics/damics-1-intro.pdf ·...

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