1. introduction 2. features · the n25q032/64a block protection bits bp[3:0] are located in status...

APPLICATION NOTE

Comparing Micron N25Q032A/064A with Macronix MX25L3235E/6435E

P/N: AN0260 Ver.1, Sep. 30, 2013 1

1. Introduction This application note serves as a guide to compare the Micron N25Q032A and N25Q064A with the Macronix MX25L3235E and MX25L6435E 3V 32Mb and 64Mb Serial Flash. The document does not provide detailed information on each individual device, but highlights the similarities and differences between them. The comparison covers the general features, performance, command codes, and other differences. If common features are used in standard traditional modes, they may need only minimal software modification. The information provided in this document is based on datasheets listed in Section 9. Newer versions of the datasheets may override the contents of this document. 2. Features Both flash device families have similar features and functions as shown in Table 2-1. Table 2-1: Feature Comparison

Feature Macronix MX25L_35E Micron N25Q_A VCC Voltage Range 2.7V-3.6V 2.7V-3.6V Sector Size 4KB/32KB/64KB 4KB/64KB Program Buffer Size 256Byte 256Byte Security OTP 512Byte 64Byte HOLD# or RESET# Pin Hold# Hold# or Reset# Normal Read Clock Frequency 50MHz 54MHz Maximum Fast Read Clock Frequency*1 104MHz 108MHz Dual Output (DREAD) (1-1-2) Yes Yes Dual I/O (2READ) (1-2-2) Yes Yes Quad Output (QREAD) (1-1-4) Yes Yes Quad I/O (4READ) (1-4-4) Yes Yes Configurable Dummy Cycle Yes Yes Block Protection Mode (BP bits) Yes Yes Individual Sector Protection Mode (Volatile)*2 Yes Yes XIP / Performance Enhanced Mode*3 Yes Yes Program/Erase Suspend & Resume - Yes Adjustable Output Driver - Yes Deep Power Down Yes - S/W Reset Command Yes - Program/Erase Cycles 100K 100K Notes:

1. Maximum clock frequency with 8 dummy cycles.

2: Please see App Note section 4-6 for detailed comparison of Individual Sector Protection.

3. Macronix supports 1-4-4 Quad I/O mode XIP; Micron supports XIP in all Fast Read modes.

APPLICATION NOTE


P/N: AN0260 Ver.1, Sep. 30, 2013 2

Table 2-2: Read Performance

I/O Mode

Macronix MX25L_35E Micron N25Q_A Default Dummy Cycles

Max Speed @ Default

Dummy Cycles

Default Dummy Cycles

Max Speed @ Default

Dummy Cycles Fast Read (1-1-1)

8 104MHz 8 108MHz

Dual Output (DREAD) ( 1-1-2)

4 86MHz 8 108MHz

Dual I/O (2READ) (1-2-2)

4 86MHz 8 108MHz

Quad Output (QREAD) (1-1-4)

6 86MHz*1 8 108MHz

Quad I/O (4READ) (1-4-4)

6 86MHz*1 8 108MHz

Note 1: 104MHz with 8 Dummy clock cycles.

3. Package and Pinout Both devices are available in similar packages with similar footprints. Pinout definitions are identical with the two minor exceptions shown in Table 3-2. Where Macronix has a HOLD#/SIO3 pin, Micron has either a HOLD#/DQ3 or a RESET#/DQ3 pin. If the Micron device has a HOLD# pin, then the devices are pin compatible. If the Micron device has a Reset# pin, but the Reset# function is not used, then the devices are also pin compatible. Macronix does not support the VPP (10V Fast Programming Voltage) function available on Micron’s W#/VPP/DQ2 pin. This function is normally only used on external programmers to accelerate Program/Erase operations and is generally not used for “in-circuit” programming. Please consult the latest Macronix datasheet for new package additions. Table 3-1: Packages

Packages MX25L_35E N25Q_A 8-WSON (6x5mm) 32Mb, 64Mb 32Mb, 64Mb 8-WSON (8x6mm) 64Mb 32Mb, 64Mb 8-USON (4x3mm) - 32Mb 8-SOP (150mil) - 32Mb 8-SOP (209mil) 32Mb, 64Mb 32Mb, 64Mb 16-SOP (300mil) 32Mb, 64Mb 32Mb, 64Mb 24-TFBGA (4x6 ball array) 64Mb 64Mb 24-TFBGA (5x5 ball array) Note*1 32Mb, 64Mb Note 1: 24-TFBGA (5x5 ball array) is currently available in MX25L_55/56E family. Contact Macronix sales.

APPLICATION NOTE


P/N: AN0260 Ver.1, Sep. 30, 2013 3

Table 3-2: Pin Definition Comparison (8-SOP and 8-WSON)

Pin Number Macronix

MX25L_35E Micron

N25Q_A Comments

Pin #1 CS# S# -

Pin #2 SO/SIO1 DQ1 - Pin #3 WP#/SIO2 W#/ VPP /DQ2 Macronix does not support VPP

Pin #4 GND VSS -

Pin #5 SI/SIO0 DQ0 - Pin #6 SCLK C -

Pin #7 HOLD#/SIO3 HOLD#/DQ3 or RESET#/DQ3

Dedicated Micron part numbers offer RESET# instead of HOLD#.

Pin #8 VCC VCC -

Figures 3-1 through 3-4 show that supported packages have similar footprints and pinouts. Figure 3-1: 8-WSON (6x5mm)

CS# 1 8 VCC S# 1 8 VCC

SO/SIO1 2 7 HOLD#/SIO3 DQ1 2 7 HOLD#/DQ3

WP#/SIO2 3 6 SCLK WP#/Vpp/DQ2 p 3 6 C

GND 4 5 SI/SIO0 VSS 4 5 DQ0

MX25L_35E N25Q0_A

Figure 3-2: 8-SOP (209 mil)

CS# VCC S# VCC

SO/SIO1 2 HOLD#/SIO3 DQ1 2 HOLD#/DQ3

WP#/SIO2 3 6 SCLK WP#/Vpp/DQ2 3 6 C

GND 4 5 SI/SIO0 VSS 4 5 DQ0

1 8

7

1 8

7MX25L_35E N25Q0_A

APPLICATION NOTE

Comparing Micron N25Q032A/064A with Macronix MX25L3235E/6435EF

P/N: AN0260 Ver.1, Sep. 30, 2013 4

Figure 3-3: 16-SOP (300mil)

HOLD#/SIO3 SCLK HOLD#/DQ3 1 16 C

VCC 2 SI/SIO0 VCC 2 15 DQ0

NC 3 14 NC DNU 3 14 DNU




CS# 7 10 GND S# 7 10 VSS

SO/SIO1 8 9 WP#/SIO2 DQ1 8 9 WP#/Vpp/DQ2

1 16

15

MX25L_35E N25Q0_A

Note: NC = Not Connected. DNU = Do Not Use.

Figure 3-4: 24-TFBGA (6x8mm with 4x6 Ball Array)

4 NC VCCWP#SIO2

HLD#SIO3

NC NC 4 NC VCCWP#/

VPP/DQ2

HLD#DQ3

NC NC

3 NC GND NCSI

SIO0NC NC 3 NC VSS NC DQ0 NC NC

2 NC SCLK CS#SO

SIO1NC NC 2 NC C S# DQ1 NC NC

1 NC NC NC NC NC NC 1 NC NC NC NC NC NC

A B C D E F A B C D E F

MX25L6435E N25Q064A

Note: NC = Not Connected

APPLICATION NOTE


P/N: AN0260 Ver.1, Sep. 30, 2013 5

4. Key Feature and Operational Differences 4-1 Status Register and Configuration Register Differences Both devices use registers to control device behavior and report status. The registers and bits used are similar but not identical. Both the Micron and Macronix devices use BP bits to select groups of memory areas for protection. The N25Q032/64A Block Protection bits BP[3:0] are located in Status Register (bits [6,4:2]). The Top/Bottom bit is located in Status Register bit 5 and selects whether block protection starts at the top or bottom of memory. The BP[3:0] and Top/Bottom bits are nonvolatile and reprogrammable. The MX25L32/6435E Block Protection bits BP[3:0] are located in Status Register bits [5:2]. The Top/Bottom bit is located in the Configuration Register bit 3. The protected areas are the same. Table 4-1: Status Register

Register Bit Macronix MX25L32/6435E Micron N25Q032/64A Bit0 WIP; 1=write operation WIP; 1=write operation

Bit1 WEL; 1=write enable WEL; 1=write enable

Bit2 BP0; BP protection BP0; BP protection



Bit5 BP3; BP protection T/B; Top/Bottom Protect

Bit6 QE; 1=Quad mode enable BP3; BP protection

Bit7 SRWD; 1=SR write disable SRWE/D; 1=SR write disable Table 4-2: Nonvolatile Configuration Register

Register Bit Macronix MX25L32/6435E Micron N25Q032/64A Bit0 Reserved Reserved

Bit1 Reserved Reserved

Bit2 Reserved Dual I/O protocol

Bit3 TB; 1=Bottom area protect Quad I/O protocol

Bit4 Reserved Reset/hold

Bit5 Reserved Reserved

Bit6 Reserved Output Driver Strength

Bit7 DC; Dummy cycle Output Driver Strength

APPLICATION NOTE


P/N: AN0260 Ver.1, Sep. 30, 2013 6

Table 4-3: Macronix Security Register vs. Micron Flag Status Register Register Bit Macronix MX25L32/6435E Micron N25Q032/64A

Bit0 4Kb Secured OTP; 1=factory lock Reserved

Bit1 LDSO; 1=OTP lock down Protection

Bit2 Reserved Program suspend

Bit3 Reserved Vpp

Bit4 Continuous Program Mode Program; 1=Program fail

Bit5 P_FAIL; 1=Program fail Erase; 1=Erase fail

Bit6 E_FAIL; 1=Erase fail Erase Suspend Bit7 WPSEL; 1=Individual WP Program/Erase Controller

4-2 Quad I/O Mode Micron’s Quad I/O mode is entered by setting a bit in the Nonvolatile Configuration Register (NVCR[3]) or by setting a bit in the Enhanced Volatile Configuration Register (VCR). The MX25L32/6435E requires bit 6 of the Status Register to be set =1 to enable Quad I/O mode operation. The WP# and Hold# pin functions are disabled in Quad mode. 4-3 XIP Differences The XIP (eXecute In Place) feature (Macronix refers to this as Performance Enhance Mode) is only used during Fast Read operations and eliminates the need to input read commands prior to entering an address and reading data. This is an overhead reduction feature that increases data throughput. Both devices offer this feature, but entry and exit methods are different. Macronix supports 1-4-4 Quad I/O mode XIP; Micron supports XIP in all Fast Read modes. 4-4. Block/Sector Sizes The MX25L_35F has uniform 64KB blocks that are each subdivided into two 32KB blocks and sixteen 4KB sectors. The N25Q0_A has uniform 64KB main blocks subdivided into 4KB sectors. No change is necessary to erase block size or erase commands when migrating from the Micron to Macronix flash, even though Macronix offers an additional 32KB block erase option. 4-5. Block Protection Mode Both the Micron and Macronix devices use BP bits to select groups of memory areas for write protection. Although the location of the bits in the Status and Configuration Registers may be different, the protected regions are similar.

APPLICATION NOTE


P/N: AN0260 Ver.1, Sep. 30, 2013 7

4-6 Individual Sector Protection Differences Both devices have the ability to write protect individual 64KB sectors/blocks of memory. Individual Sector Protection does not use the nonvolatile BP bits in the Status Register. With the Micron flash, it is possible to use both methods of write protection (BP bits and Individual Sector Protection) simultaneously, and the protected area is the combination of the two. When using the Macronix flash, either BP bit Protection or Individual Sector Protection can be selected exclusively, with the default being the use of the BP bits. The N25Q_A have one volatile Lock Register for each 64KB sector to control the sector’s program/erase protection status. The protection can be turned on or off at any time unless the sector’s Lock Register has been locked by the application. Once locked, its associated sector will remain in the protected or unprotected state until the next power cycle or reset. All sectors not protected by the Status Register BP configuration will be unprotected after power up and all Lock Registers will be unlocked. The MX25L_35E have one volatile protection register for each of the top sixteen 4KB sectors, bottom sixteen 4KB sectors, and the remaining middle 64KB blocks (the MX25L3235E has 62 middle blocks and the MX25L6435E has 126 middle blocks). These protection registers can only be used after permanently disabling the Status Register BP protection bits. This is done by executing the WPSEL instruction once. Please note that this irreversible and Individual Sector Protection method will be permanently selected. After permanently selecting the Individual Sector Protection method for the MX25L_35E, all sectors and blocks will be locked by default on power up. Sectors/blocks must be unlocked before they can be programmed or erased. Unlocking sectors/blocks can be done on an individual basis with the SBULK (Single Block Unlock) command or on all sectors/blocks with the GBULK (Global Block Unlock) command. Sectors and blocks can be relocked as necessary with the SBLK (Single Block Lock) command or GBLK (Global Block Lock) command. Since the smallest individual sector protection size in the N25Q_A is 64KB, if an application is currently locking/unlocking the top and/or bottom 64KB sector(s), it will need to lock/unlock each of the 16 top and/or bottom 4KB sectors in the MX25L_35E for equivalent results. 4-7. Secure OTP Differences Both device families provide a secure One Time Programmable (OTP) area outside of the main memory array for user defined storage. The sizes, features, and access methods are different. The N25Q0_A has commands to directly read and program the 64 byte OTP area and does not need to explicitly open this area for read and write operations. The MX25L_35E operates in the OTP area using normal read and program instructions after explicitly opening the OTP area with the Enter Secured OTP (ENSO) command. While the OTP area is open, the main array is not accessible. When finished in the OTP area, the Exit Secure OTP (EXSO) command must be issued to return to the Read Main Array mode. The MX25L_35E OTP area has 512 bytes available for user data. The user may permanently lock the whole OTP area to prevent new data from being stored there. This area can optionally be programmed with user supplied data and factory locked by Macronix.

APPLICATION NOTE


P/N: AN0260 Ver.1, Sep. 30, 2013 8

5. Performance Table 5-1 and 5-2 show that the two devices have similar AC and DC performance.

Table 5-1: AC Parameter Comparison

Parameter Symbol

Condition Macronix

MX25L_35E Micron

N25Q_A Macronix Micron Clock High / Low Time tCH / tCL tCH / tCL min 4.5ns 4ns

Clock Low to Output Valid tCLQV tCLQV

max 10pF, x1 5ns 5ns max 10pF, x4 6ns 5ns max 15pF, x1 6ns - max 15pF, x4 6ns - max 30pF, x1 7ns 7ns max 30pF, x4 8ns 7ns

Data In Setup Time tDVCH tDVCH min 2ns 2ns Data In Hold Time tCHDX tCHDX min 3ns 3ns

Page Program Time (256 Bytes) tPP tPP typ 1.4ms 0.4ms

max 3ms 5ms

Erase 4KB Subsector/Sector tSSE tSE typ 60ms 250ms

max 300ms 800ms

Erase 32KB Sector tBE32 - typ 500ms -

max 2s -

Erase 64KB Sector/Block tBE tSE typ 700ms 700ms

max 2s 3s

Bulk Erase / Chip Erase (32Mb) tCE tBE typ 25s 30s

max 50s 60s

Bulk Erase / Chip Erase (64Mb) tCE tBE typ 50s 60s

max 80s 120s

Table 5-2: DC Parameter Comparison

Parameter Symbol

Condition Macronix MX25L_35E

Micron N25Q_A Macronix Micron

Leakage Current ILI/ILO ILI/ILO max +/- 2uA +/- 2uA Standby Current ISB1 ICC1 max 80uA 100uA

Deep Power Down Current ISB2 ICC2 typ 5uA - max 40uA -

VCC Read Current (Fast Read) ICC1 ICC3

max 108MHz, x4 - 20mA max 104MHz, x4 35mA - max 108MHz, x1 - 15mA max 104MHz, x1 19mA -

VCC Program Current ICC2 ICC4 max 25mA 20mA VCC Write Status Register Current

ICC3 ICC5 max 20mA 20mA

VCC Erase Current ICC4,5 ICC6 max 25mA 20mA

APPLICATION NOTE


P/N: AN0260 Ver.1, Sep. 30, 2013 9

6. Command Code Both devices use the same basic command set, but there are a few minor differences highlighted in Table 6-1. Table 6-1: Command Code Comparison Instruction

Type Instruction Description

Macronix MX25L_35E

Micron N25Q_A

Read ID RDID Read Identification 9Fh 9Eh/9Fh REMS Read Electronic Manufacturer ID 90h - REMS2/4 Multi I/O Read ID EFh/DFh AFh

Read

READ Read Data Bytes 03h 03h FAST_READ Read Data Bytes at Higher Speed 0Bh 0Bh DOFR Dual Output Fast Read 3Bh 3Bh DIOFR Dual Input/Output Fast Read BBh BBh QOFR Quad Output Fast Read 6Bh 6Bh QIOFR Quad Input/Output Fast Read EBh EBh W4READ Quad Input/Output Fast Read (4-dummy) E7h - RDSFDP Read Serial Flash Discoverable Parameters 5Ah 5Ah

Write

WREN Write Enable 06h 06h WRDI Write Disable 04h 04h PP Page Program 02h 02h CP Continuous Program ADh - - Dual Input Fast Program (1-1-2) - A2h - Dual I/O Fast Program (1-2-2) - D2h - Quad Input Fast Program (1-1-4) - 32h 4PP Quad Page Program (1-4-4) 38h 12h SE Sector Erase 4KB 20h 20h BE 32K Block Erase 32KB 52h - SE 64K Block Erase 64KB D8h D8h CE Chip Erase 60 or C7h C7h

OTP

ENSO Enter Secured OTP B1h - EXSO Exit Secured OTP C1h - ROTP Read OTP Area - 4Bh POTP Program OTP Area - 42h

APPLICATION NOTE


P/N: AN0260 Ver.1, Sep. 30, 2013 10

Table 6-1: Command Code Comparison - Continued Instruction

Type Instruction Description

Macronix MX25L_35E

Micron N25Q_A

Registers and

Other

RDSR Read Status Register 05h 05h WRSR Write Status Register 01h 01h RDSCUR Read Security Register 2Bh - WRSCUR Write Security Register 2Fh - RDLR Read Lock Register - E8h WRLR Write Lock Register - E5h RFSR Read Flag Status Register - 70h CLFSR Clear Flag Status Register - 50h

- Read Non-volatile Configuration Register

15h B5h

- Write Non-volatile Configuration Register

- B1h

- Read Volatile Configuration Register - 85h - Write Volatile Configuration Register - 81h

- Read Enhance Volatile Configuration Register

- 65h

- Write Enhance Volatile Configuration Register

- 61h

PGM/ERS Suspend

Program or Erase Suspend - 75h

PGM/ERS Resume

Program or Erase Resume - 7Ah

ESRY Enable SO to output RY/BY# 70h - DSRY Disable SO to output RY/BY# 80h - RSTEN Reset Enable 66h - RST Reset Memory 99h - NOP No Operation 00h - DP Deep Power Down B9h - RDP Release From Deep Power Down ABh - WPSEL Write Protect Selection (OTP) 68h - GBLK Gang Block Lock 7Eh - GBULK Gang Block Unlock 98h - SBLK Single Block Lock 36h - SBULK Single Block UnLock 39h - RDBLOCK Read Block Lock 3Ch -

APPLICATION NOTE


P/N: AN0260 Ver.1, Sep. 30, 2013 11

7. Manufacturer and Device ID Table 7-1: Manufacturer and Device ID Comparison

ID Type Macronix

Micron

MX25L3235E MX25L6435E N25Q32A N25Q64A Manufacturer ID C2h C2h 20h 20h JEDEC Device ID 2016h 2017h BA16h BA17h Unique ID N/A N/A 17 Bytes 17 Bytes 8. Summary The Macronix MX25L3235E/6435E and Micron N25Q032/64A have similar commands, functions, and features. The devices are command compatible for basic read, program, and erase (4KB and 64KB) operations. The devices are essentially pin compatible if the Reset# function is not used. A more detailed analysis should be done if “special” functions such as XIP, Suspend/Resume, or Individual Sector Protection are used. If common features are used in standard traditional modes, they may need only minimal software modification. 9. References Table 9-1 shows the datasheet versions used for comparison in this application note. For the most current, detailed Macronix specification, please refer to the Macronix Website at http://www.macronix.com/. Table 9-1: Datasheet Version

Datasheet Location Date Issued Version

MX25L3235E Macronix Website APR. 2013 1.3

MX25L6435E Macronix Website APR. 2012 1.2

n25q_32mb_3v_65nm Micron Website APR. 2013 I

n25q_64mb_3v_65nm Micron Website AUG. 2013 K

APPLICATION NOTE


P/N: AN0260 Ver.1, Sep. 30, 2013 12

10. Appendix Table 10-1 shows the basic part number and package information cross reference between Macronix MX25L3235E and Micron N25Q032A parts. Table 10-2 shows the basic part number and package information cross reference between Macronix MX25L6435E and Micron N25Q064A parts. Table 10-1: 32Mb Part Number Cross Reference

Macronix Part No. Micron Part No. Package Dimension Note MX25L3235EM2I-10G N25Q032A13ESE40 8-SOP 209 mil Hold# pin, Micron XIP MX25L3235EM2I-10G N25Q032A23ESE40 8-SOP 209 mil Hold# pin, basic XIP MX25L3235EM2I-10G N25Q032A33ESE40 8-SOP 209 mil Reset# pin, Micron XIP MX25L3235EM2I-10G N25Q032A43ESE40 8-SOP 209 mil Reset# pin, basic XIP MX25L3235EMI-10G N25Q032A13ESF40 16-SOP 300 mil Hold# pin, Micron XIP MX25L3235EMI-10G N25Q032A23ESF40 16-SOP 300 mil Hold# pin, basic XIP MX25L3235EMI-10G N25Q032A33ESF40 16-SOP 300 mil Reset# pin, Micron XIP MX25L3235EMI-10G N25Q032A43ESF40 16-SOP 300 mil Reset# pin, basic XIP MX25L3235EZNI-10G N25Q032A13EF640 8-WSON 6x5 mm Hold# pin, Micron XIP MX25L3235EZNI-10G N25Q032A23EF640 8-WSON 6x5 mm Hold# pin, basic XIP MX25L3235EZNI-10G N25Q032A33EF640 8-WSON 6x5 mm Reset# pin, Micron XIP MX25L3235EZNI-10G N25Q032A43EF640 8-WSON 6x5 mm Reset# pin, basic XIP Table 10-2: 64Mb Part Number Cross Reference

Macronix Part No. Micron Part No. Package Dimension Note MX25L6435EM2I-10G N25Q064A13ESE40 8-SOP 209 mil Hold# pin, Micron XIP MX25L6435EM2I-10G N25Q064A23ESE40 8-SOP 209 mil Hold# pin, basic XIP MX25L6435EM2I-10G N25Q064A33ESE40 8-SOP 209 mil Reset# pin, Micron XIP MX25L6435EM2I-10G N25Q064A43ESE40 8-SOP 209 mil Reset# pin, basic XIP MX25L6435EMI-10G N25Q064A13ESF40 16-SOP 300 mil Hold# pin, Micron XIP MX25L6435EMI-10G N25Q064A23ESF40 16-SOP 300 mil Hold# pin, basic XIP MX25L6435EMI-10G N25Q064A33ESF40 16-SOP 300 mil Reset# pin, Micron XIP MX25L6435EMI-10G N25Q064A43ESF40 16-SOP 300 mil Reset# pin, basic XIP MX25L6435EZNI-10G N25Q064A13EF640 8-WSON 6x5 mm Hold# pin, Micron XIP MX25L6435EZNI-10G N25Q064A23EF640 8-WSON 6x5 mm Hold# pin, basic XIP MX25L6435EZNI-10G N25Q064A33EF640 8-WSON 6x5 mm Reset# pin, Micron XIP MX25L6435EZNI-10G N25Q064A43EF640 8-WSON 6x5 mm Reset# pin, basic XIP MX25L6435EZ2I-10G N25Q064A13EF840 8-WSON 8x6 mm Hold# pin, Micron XIP MX25L6435EZ2I-10G N25Q064A23EF840 8-WSON 8x6 mm Hold# pin, basic XIP MX25L6435EZ2I-10G N25Q064A33EF840 8-WSON 8x6 mm Reset# pin, Micron XIP MX25L6435EZ2I-10G N25Q064A43EF840 8-WSON 8x6 mm Reset# pin, basic XIP MX25L6435EXCI-10G N25Q064A13E1440 24-TFBGA 6x4 ba Hold# pin, Micron XIP MX25L6435EXCI-10G N25Q064A23E1440 24-TFBGA 6x4 ba Hold# pin, basic XIP MX25L6435EXCI-10G N25Q064A33E1440 24-TFBGA 6x4 ba Reset# pin, Micron XIP MX25L6435EXCI-10G N25Q064A43E1440 24-TFBGA 6x4 ba Reset# pin, basic XIP

APPLICATION NOTE


P/N: AN0260 Ver.1, Sep. 30, 2013 13

11. Revision History

Revision Description Date 1.0 Initial Release September 6, 2013

APPLICATION NOTE


P/N: AN0260 Ver.1, Sep. 30, 2013 14

Except for customized products which have been expressly identified in the applicable agreement, Macronix's products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only, and not for use in any applications which may, directly or indirectly, cause death, personal injury, or severe property damages. In the event Macronix products are used in contradicted to their target usage above, the buyer shall take any and all actions to ensure said Macronix's product qualified for its actual use in accordance with the applicable laws and regulations; and Macronix as well as it’s suppliers and/or distributors shall be released from any and all liability arisen therefrom. Copyright© Macronix International Co., Ltd. 2013. All rights reserved, including the trademarks and tradename thereof, such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, NBit, Nbit, NBiit, Macronix NBit, eLiteFlash, HybridNVM, HybridFlash, XtraROM, Phines, KH Logo, BE-SONOS, KSMC, Kingtech, MXSMIO, Macronix vEE, Macronix MAP, Rich Au-dio, Rich Book, Rich TV, and FitCAM. The names and brands of third party referred thereto (if any) are for identification purposes only For the contact and order information, please visit Macronix’s Web site at: http://www.macronix.com

1. introduction 2. features · the n25q032/64a block protection bits bp[3:0] are located in status...

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