1 in 0.53 ga 0.47 as mosfets with 5 nm channel and self-aligned source/drain by mbe regrowth uttam...
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![Page 1: 1 In 0.53 Ga 0.47 As MOSFETs with 5 nm channel and self-aligned source/drain by MBE regrowth Uttam Singisetti PhD Defense Aug 21, 2009 * uttam@ece.ucsb.edu](https://reader036.vdocuments.us/reader036/viewer/2022081519/56649d7a5503460f94a5eb19/html5/thumbnails/1.jpg)
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In0.53Ga0.47As MOSFETs with 5 nm channel and self-aligned source/drain by MBE regrowth
Uttam Singisetti
PhD Defense
Aug 21, 2009
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Outline
• Motivation: why III-V MOSFETs, target device structure
• Approach: self-aligned source/drain by MBE regrowth
• FET and contacts results
• Conclusion and future work
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Why III-V MOSFETs
Silicon MOSFETs:
Gate oxide may limit <16 nm scaling
IBM 45nm NMOS
Narayan et al, VLSI 2006
* Enoki et al , EDL 1990
Alternative: In0.53Ga0.47As channel MOSFETs
low m* (0.041 mo) → high injection velocity, vinj (~ 2-3×107 cm/s)*
→ increase drive current, decreased CV/I
Id / Wg ~ cox(Vg-Vth)vinj
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Key challenge : high-k on III-V
Dielectric goals : 0.6 nm EOT , Dit 1×1012 cm-2 eV-1 ,low leakage
Dielectrics & approaches:
Atomic layer deposition (ALD) Al2O31
Chemical beam deposition ZrO22
Molecular beam epitaxy (MBE) GGO3
3 R.Hill et al, Device research conference, 2009
1 B. Shin et al, ECSSL, 12, G40, 2009
2 R. E. Herbert et al, APL, 95, 0629081, 2009
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MOSFET scaling*: lateral and vertical
Goal :
double package density → lateral scaling Lg, Wg, Ls/d
*Rodwell, IPRM 2008
double the MOSFET speed keep constant gate control
vertical scaling tox, tqw, xj
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Drain modulates b d
b
V
(DIBL)
(DIBL)
Drain induced barrier lowering (DIBL)
g
b
V
Gate modulates b sub-threshold slope (S)
g
b
V
d
b
V
goal >>
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qw
yx
dy
d
dx
d
2
2
2
2
DIBL : 2-D electrostatics*
*Yan et al, TED, 39, 1704, 1992
Cg-ch ~ oxWg Lg / tox Cd-ch ~ qwWg tqw / Lg
aspect ratio Cg-ch / Cd-ch = = ox Lg2
/ tqw tox qw*
= 5-10 for long channel like sub-threshold behavior*
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MOSFET aspect ratio
constant aspect ratio: Lg↓ → tox↓, tqw↓ and xj↓
qwqwoxox
qwg
tt
L
//
/
aspect ratio active region rectangle → → DIBL
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Target device structure
Target 22 nm gate length
Control of short-channel effects vertical scaling
1 nm EOT: thin gate dielectric, surface-channel device
5 nm quantum well thickness
< 5 nm deep source / drain regions
-4
-3
-2
-1
0
1
2
3
0 50 100 150 200 250
En
erg
y (
eV
)
Y (Ang.)
Al2O
3
InGaAs InAlAs
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increase Id to reduce circuit delay (d )
~3 mA/m target drive current low access resistance
self-aligned, low resisitivity source / drain contacts
self-aligned N+ source / drain regions with high doping
InGaAs MOSFET: target drive current
d
ddtotal
d I
VC
v
L
I
VC g
d
ddigs ,
int
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22 nm InGaAs MOSFET: source resistance
IBM High-k Metal gate transistorImage Source:EE Times
smi
did Rg
II
1 g
DSsheet
DSg
cs W
L
LWR
2/
/
LgLS/D
• Source access resistance degrades Id and gm
• IC Package density : LS/D ~ Lg =22 nm c must be low
• Need low sheet resistance in thin ~5 nm N+ layer
• Design targets: c ~1 m2, sheet ~ 400
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22nm ion implanted InGaAs MOSFET
• Shallow junctions ( ~ 5 nm), high (~5×1019 cm-3) doping
• Doping abruptness ( ~ 1 nm/decade)
• Lateral Straggle ( ~ 5 nm)
• Deep junctions would lead to degraded short channel effects
Key Technological Challenges
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InGaAs MOSFET with raised source/drain by regrowth
1Wistey, EMC 20082Baraskar, JVST 2009
Interface
HAADF-STEM1
2 nm
InGaAs
InGaAsregrowth
Self-aligned source/drain defined by MBE regrowth1
Self-aligned in-situ Mo contacts2
Process flow & dimensions selected for 22 nm Lg design; present devices @ 200 nm gate length
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Regrown S/D process: key features
Vertical S/D doping profile set by MBEno n+ junction extension below channelabrupt on ~ 1 nm scale
Self-aligned & low resistivity...source / drain N+ regions...source / drain metal contacts
Gate-firstgate dielectric formed after MBE growth
uncontaminated / undamaged surface
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Process flow*
* Singisetti et al; Physica Status Solidi C, vol. 6, pp. 1394,2009
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SiO2
W
Cr
FIB Cross-section
Damage free channel
Process scalable to sub-100 nm gate lengths
Key challenge in S/D process: gate stack etch
Requirement: avoid damaging semiconductor surface:Approach: Gate stack with multiple selective etches*
* Singisetti et al; Physica Status Solidi C, vol. 6, pp. 1394,2009
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Key challenge in S/D process: dielectric sidewall
Simulation in Atlas, Silvaco
4 1018
8 1018
1.2 1019
1.6 1019
2 1019
2.4 1019
2.8 1019
0 10 20 30 40 50 60 70 80
10nm SiN20 nm SiN30 nm SiNel
ectr
on c
once
ntra
tion
(cm
-3)
distance (nm)
gate source
sidewall
tswn (cm-3) Rs (m)
10 nm > 1×1019 620 nm > 5×1018 2030 nm ~ 4×1018 60
n under sidewall →
electrostatic spillover from source and gate
spillover
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Key challenge in S/D process: dielectric sidewall
Sidewall must be kept thin: avoid carrier depletion, low leakage
• Target < 15 nm sidewall in 22 nm Lg device
• 20-25 nm SiNx thick sidewalls in present devices
• Pulse doping in the barrier: compensate for carrier depletion from Dit
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Surface cleaning before regrowth
• 30 min UV Ozone
• Ex-situ HCl:H2O clean
• In-situ 30 min H clean
Interface
HAADF-STEM*
2 nm
InGaAs
InGaAsregrowth
* Wistey, EMC 2008
c(4×2) reconstruction before regrowth → minimum process contamination
TEM by Dr. J. Cagnon, Stemmer Group, UCSB
MBE growth by Dr. Mark Wistey, device fabrication and characterization by U.Singisetti
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Self-aligned contacts: height selective etching*
Mo
InGaAs
PR
PR PR
* Burek et al, J.Cryst.Growth 2009
Dummy gateNo regrowth
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1st generation MOSFETs
0
20
40
60
80
100
0 0.5 1 1.5 2
Dra
in C
urre
nt,
uA
Vds, Volts
steps V 0.25in V 2 toV 0V
microns 50 Wmicrons, 10
g
g
gL
0
20
40
60
80
100
0 0.5 1 1.5 2
Dra
in c
urr
ent
( A
)
Vgs
(Volts)
Lg=10m, W
g=50m
Vds
=2V
• Extremely low drive current: 2 A/m
• Extremely high Ron= 0.7 Mm
• Why is Rs so high?
Ron ~ 0.7 Mm!
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Source resistance : gap in Regrowth
W / Cr / SiO2
gate
W / Cr / SiO2
gate
SEM
SEM
• Shadowing by gate: No regrowth next to gate
• Gap region is depleted of electrons
High source resistance because of electron depletion in the gap
MBE growth by Dr. Mark Wistey, device fabrication and characterization by U.Singisetti
W/Cr gate
Mo+InGaAs
Ti/Au Pad
Gap in regrowth
SiO2 cap
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Migration enhanced epitaxial (MEE) regrowth*
*Wistey, EMC 2008 Wistey, ICMBE 2008
High T migration enhancedEpitaxial (MEE) regrowth*
regrowth interface
gateNo Gap
45o tilt SEM
Top of SiO2 gate
No Gap
Side of gate
High temperature migration enhanced epitaxial regrowth
MBE growth by Dr. Mark Wistey, device fabrication and characterization by U.Singisetti
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SiO2
WCr
Originalinterface
InGaAsregrowth
SiNx
SiO2
WCr
Originalinterface
InGaAsregrowth
SiNx
W/Cr gate Pad
Ti/Au Pad
Mo+InGaAs
W/Cr gate Pad
Ti/Au Pad
Mo+InGaAs
MEE source/drain regrowth MOSFET SEMs
Cross-section after regrowth, but before Mo deposition
Top view of completed device
MBE growth by Dr. Mark Wistey, device fabrication and characterization by U.Singisetti
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Regrown S/D FETs: Images
MoMo
gate post
gate
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MOSFET characteristics
0
0.2
0.4
0.6
0.8
1
0 0.5 1 1.5 2
Lg=0.8m, W
g,eff=9m
Vgs
= -1 V to 3.5, Vgs_step
=0.5 V
I ds(m
A/
m)
Vds
(V)
• Maximum Drive current (Id): 0.95 mA/m
• Peak transconductance (gm): 0.37 mSm
4.7 nm Al203 , 1×1013 cm-2 pulse doping
Id and gm below expected values
0
0.2
0.4
0.6
0.8
1
0 0.5 1 1.5 2
I ds(m
A/
m)
Lg=1.0m, W
g,eff=12m
Vgs
= -1 V to 3.5, Vgs_step
=0.5 V
Vds
(V)
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SEM
FET source resistance
• Series resistance estimated by extrapolating Ron to zero gate length
• Source access resistance ~ 500 m
0
1000
2000
3000
4000
5000
6000
7000
0 2 4 6 8 10Gate Length (m)
Vgs
=3.0 V
RS+R
D
= 1.0 k m
Ro
n (
m
)
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Source resistance : regrowth TLMs
W / Cr / SiO2
gate
SEM
No regrowth
SEM
• TLMs fabricated on the regrowth far away from the gate
• Regrowth sheet resistance ~ 29
• Mo/InGaAs contact resistance ~ 5.5 m2 (12.6 m)
TLM data does not explain 500 m observed FET source resistance
FETRegrowth TLMs
0
5
10
15
20
25
30
35
40
0 5 10 15 20 25 30
Res
ista
nc
e (
)
Contact Separation ( m)
Rsh
~ 29
Rc ~ 5.5 m2 (12.6 m)
W~ 20 m
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Source resistance: electron depletion near gate
• Electron depletion in regrowth shadow region (R1 )
• Electron depletion in the channel under SiNx sidewalls (R2 )
SiO2
WCr
Originalinterface
InGaAsregrowth
SiNx
SiO2
WCr
Originalinterface
InGaAsregrowth
SiNx
R1
R2
MBE growth by Dr. Mark Wistey, device fabrication and characterization by U.Singisetti
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SiO2
W
Cr
InGaAs
InGaAs
InGaAs
InGaAs
InAlAs
Regrowth profile dependance on As flux*
Uniform filling with lower As flux
multiple InGaAs regrowths with InAlAs marker layers
increasing As flux
regrowth surface
* Wistey et al, EMC 2009 Wistey et al NAMBE 2009
MBE growth by Dr. Mark Wistey, device fabrication and characterization by U.Singisetti
uniform filling
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InAs source/drain regrowth
1 Wistey et al, EMC 2009 Wistey et al NAMBE 2009. 2Bhargava et al , APL 1997
Improved InAs regrowth with low As flux for uniform filling1
InAs less susceptible to electron depletion: Fermi pinning above Ec2
MBE growth by Ashish Baraskar, device fabrication and characterization by U.Singisetti
InAsregrowth
Gate
InGaAs100 nm
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Regrown InAs S/D FETs
Mo S/D metalwith N+ InAsunderneath
side of gate
top of gategate
Mo S/D metal with N+ InAs underneath
4.7 nm Al203, 5×1012 cm-2 pulse doping
MBE growth by Dr. Mark Wistey, device fabrication and characterization by U.Singisetti
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InAs S/D E-FET DC Characteristics
4.7 nm Al203, InAs S/D E-FET
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0 0.2 0.4 0.6 0.8 1V
DS (V)
Lg = 350nm W
g = 8 m
Vgs
: 0 to 4 V in 0.5 V steps
drai
n cu
rren
t, I D
(mA
/m
)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0 0.2 0.4 0.6 0.8 1V
DS (V)
Lg = 0.45 m W
g = 8 m
Vgs
: 0 to 4 V in 0.5 V steps
drai
n cu
rre
nt, I
D (m
A/
m)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0 0.5 1 1.5 2V
DS (V)
Lg = 1 m W
g = 8 m
Vgs
: 0 to 4 V in 0.5 V steps
dra
in c
urre
nt, I
D (m
A/
m)
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InAs S/D E-FET DC characteristics
4.7 nm Al203, InAs S/D E-FET
0
0.2
0.4
0.6
0.8
0 0.5 1 1.5
dra
in c
urre
nt,
I D (m
A/
m)
VDS
(V)
Lg = 200 nm W
g = 8 m
Vgs
: 0 to 4 V in 0.5 V steps
Ron = 600 m
0.85 mA/m peak Id , ~0.36 mS/m peak gm
* Singisetti et al, IEEE EDL, submitted
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Sub-threshold characteristics
• Ion / Ioff~ 104:1
• High sub-threshold swing
• Hysteresis
-1 0 1 2 3 4 5
Vds
=0.1V
Vds
=1.0 V
325 mV/decade
Vgs
(V)
Lg=0.35 m
10-9
10-8
10-7
10-6
10-5
10-4
10-3
10-2
-1 0 1 2 3 4 5
Vds
=0.1V
Vds
=1.0V
290 mV/decadeI d(A)
Vgs
(V)
Lg=1.0 m
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0
0.5
1
1.5
2
2.5
3
0 0.2 0.4 0.6 0.8 1
Ro
n (k
m
)
gate length (m)
600 m
Source-drain access resistance*
• Ron = 600 -m for Lg=0.2 m so Rs< 300 m
• Rs is too small to explain observed gm or Id*Wistey et al, NAMBE 2009
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Source access resistance
Mo/InAs contact resistance : 3.5 m2 (8.5 m)
InAs sheet resistance: 20
Electron depletion at Al2O3/InGaAs interface under sidewall
MBE growth by Ashish Baraskar, device fabrication and characterization by U.Singisetti
InAsregrowth
Gate
InGaAs100 nm
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Key challenge in S/D process: dielectric sidewall
Simulation in Atlas, Silvaco
4 1018
8 1018
1.2 1019
1.6 1019
2 1019
2.4 1019
2.8 1019
0 10 20 30 40 50 60 70 80
10nm SiN20 nm SiN30 nm SiNel
ectr
on c
once
ntra
tion
(cm
-3)
distance (nm)
gate source
sidewall
tswn (cm-3) Rs (m)
10 nm > 1×1019 620 nm > 5×1018 2030 nm ~ 4×1018 60
n under sidewall →
electrostatic spillover from source and gate
spillover
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Gate dielectric Dit
10-9
10-8
10-7
10-6
10-5
10-4
10-3
10-2
-1 0 1 2 3 4 5
Vds
=0.1V
Vds
=1.0V
300 mV/decadeI d(A
)
Vgs
(V)
Lg=1.0 m
decademVc
qDccS
ox
itdox / 60
qw
qwd tc
Dit from sub-threshold swing = 2 ×1013 cm-2 eV-1
oxc
itit qDc
itc
dc
G S
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Threshold voltaget (Vt )
-5
-4
-3
-2
-1
0
1
2
3
10
171
018
10
19
0 50 100 150 200 250 300 350 400
Y (Ang.)
ele
ctro
n c
on
ce
ntra
tion
(cm
-3)
Al2O
3
In0.48
Al0.52
As
InGaAs
En
erg
y (
eV)
Ef
Expected Vt = -0.75 V, actual Vt = 0.6 V
Dit = ∆ Vt / qCox = 1.5 ×1013 cm-2 eV-1
Vg= 0 V
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10-7
10-6
10-5
10-4
10-3
10-2
10-1
100
-1 0 1 2 3 4V
gs(V)
drai
n cu
rren
t, I D
(m
A/
m)
Lg=200 nm
Vds
=0.1 V
500 mV/decade
Higher S in 200 nm device: DIBL ?
higher sub-threshold swing for 200 nm device → is it DIBL
Lg / tqw = 200/5 = 40 → clearly not DIBL
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InAs InAlAs
Electron confinement under source/drain
InGaAs
Insufficient electron confinement under source/drain
Need a AlAsSb barrier or higher p+ doping in buffer
Ef
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• Self-aligned source/drain for thin channels ( ~ 5nm ) → scalable
• InAs Source/Drain E-FETs: Rs < 300 m, peak Id= 0.85 mA/m, peak gm= 0.36 mS/m
• Device gm, Id not limited by Rs
• Next: scale to ~50 nm Lg
scale sidewalls gate dielectric quality
Conclusion
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Acknowledgements
Prof. Mark Rodwell, Prof. Umesh Mishra, Prof. Art Gossard, Prof. Chris Palmstrøm
Dr. Mark Wistey, Dr. Seth Bank, Dr Yong-ju Lee
Stemmer group: Dr Joël Cagnon
McIntyre group (Stanford) : Eunji, Byungha
Yuan Taur group (UCSD) : Yu Yuan
Rodwell group members: Navin, Colin, Zach, Erik, Munkyo, Greg, Vibhor, Evan, Ashish
Mishra group, photonics group clean-room buddies
Nanofab staff: Jack, Brian, Don, Bill, Mike, Bob, Adam, Tony, Aidan, Luis
MRL staff: Dr Tom Mates
Friends and family