1 a 256kb sub-threshold sram in 65nm cmos benton h. calhoun, anantha chandrakasan massachusetts...
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A 256kb Sub-threshold SRAM in 65nm CMOS
Benton H. Calhoun, Anantha Chandrakasan
Massachusetts Institute of Technology, Cambridge, MA
ISSCC 2006 / SESSION 34 / SRAM / 34.4
Presented by: Pouya Kamalinejad
2006/12/28
Advanced VLSI class presentation
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Outline
• Introduction and preliminaries.
• SNM introduction.
• Proposed 10T SRAM
• Simulation and results
• Read SNM free SRAM
• Conclusion
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Why Low Voltage SRAMs?
• The minimum supply voltage of LSIs is limited by their SRAMs for the following two reasons[2]:
1) with decreasing supply voltage (Vdd), SRAM delay increases at a higher rate than does CMOS logic circuit delay.
2) Read operations at low-Vdd levels result in storage data destruction in SRAM cells.
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Preliminaries
Traditional 6-T SRAM column[3] Bitline discharging for the reaoperation[3]
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Static Noise Margin
• The large fraction of chip area often devoted to SRAM makes low power SRAM design very important.
• SNM quantifies the amount of voltage noise required at the internal nodes of a bitcell to flip the cell’s contents.
• degraded SNM can limit voltage scaling for SRAM designs.
Inverter 2Inverter 1
SNM is length of side of the largest embedded square on the butterfly curve
WL BLBBL
Q QBM1
M2
M3
M4M5
M6
VN
VN
[1]
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Cont’d
Moves upward
Moves to the left
SNM is lower during read access because the VTC is degraded by the voltage divider across the access transistor (M2,M5) and drive transistor (M1,M4)[2]
SNM Butterfly Curve
The minimum supply voltage of SRAMs is determined by both Read SNM and Write SNM levels; reducing Vth in the NMOS transistor improves Write SNM but worsens Read SNM.
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SNM during HOLD and READ
Read SNM is worst-case
WL=0BLBBL
1 0M1
M2
M3
M4M5
M6
WL=1BLB prech 1BL prech 1
1 0M1
M2
M3
M4M5
M6
[1]
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Sub-VT SNM Dependencies
• SNM is mainly a function of:
Vdd (limited to Vdd/2)Temperature (higher temp results in
Lower SNM due to lower gain)
Sizing (Cell ratio affects SNM less in
sub-threshold due to logarithmic relation
unless it affects Vt)
Bit-line voltageVt mismatch
Vt mismatch is the worstNormal distribution
Model* gives good estimate forthe distribution of SNM at the
worst-case tail
[1]
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How to reduce Vdd?
Impact of local mismatch on 6T SNM in 65nm. Read SNM has larger standard deviation. Hold SNM at 0.3V has roughly the same mean as Read SNM at 0.5V and same 6σ SNM as Read SNM at 0.6V.[2]
Thus, by eliminating the degraded Read SNM, a bitcell can be operated at 0.3V with the same 6σ
stability as a 6T bitcell at 0.6V. A
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Cont’d
• The idea is to add a 4T buffer at one side:
6T bitcell
4T buffer
WLBLBBL
Q QB
VVDD
RBLRWL
Proposed 10-T bitcell for Sub-VT[1]Proposed 10-T bitcell for Sub-VT[1]
M7 to M10 to remove the problem of Read SNM by buffering thestored data during a read access.
Thus, the worst-case SNM for this bitcell is the Hold SNMrelated to M1 to M6, which is the same as the 6T Hold SNM for same sizedM1 to M6
M9
M8
M10
M7
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10T Bitcell Reduces Bitline Leakage
QB=1
RBL=10
QBB heldnear 1 so the leakage current through M8 is reduced
QB=0
RBL=10QBB =1
leakagereducedby stack
Q QB
for iso-VDD, the 10T cell without M10 (a 9T cell) has 50% higher leakage current than the 6T, but adding M10 drops the overhead
to 16%.
[1]
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Leakage Power Savings with 10T Bitcell
6T memories in 65nm usually at 0.9V or greater (lowest reported is 0.7V)
10T bitcell allows scaling to lower voltages Lower voltage operation reduces leakage power dramatically for unaccessed cells
[1]
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Bitline Leakage Limits Integration Level
16 bitcells on bitline is best can hope for standard 6T
“1”
“0”
“0”
Bit
-li
ne
[1]
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Cont’d
BL leakage limits the number of cells on a BL. The 10T bitcell can sustain 256 cells/BL at 0.3V compared to 16 without M10 (6T or 9T). higher level of integration allowed by the 10T cell reduces the peripheral circuits and slightly mitigates the bitcell area overhead[1].
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10T Bitcell Allows Sub-VT Write
To achieve write in sub-threshold, the virtual supply (VVDD) to the selected cells floats during the write operation
Folded WL shares VVDD
WL
BLBBL
Q QB
VVDD
RBL
RWL
MC
MC MC
MC
VDDon
[1]
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Cont’d
floating
feedbackrestores ‘1’ to VDD
Floating VDD weakens feedback and allows Write.
A virtual supply voltage (VVDD) that floats during write allows robust write operation into sub-VT (mono-stable butterfly curve). VVDD stops floating while WL_WR remains asserted to restore the ‘1’value to full VDD[1].
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Test Chip Architecture
• 256 rows and 128 columns per block
• Static CMOS peripherals
• Separate WL VDD for boosting
• Assumed 1x1 redundancy
• Simulation: Operates at 300mV across all process corners from 0 to 100oC
X8
MC
writeBK
prechBK
VDDfloatEn MP<r>
I<c>
RD
column<c>
writeBK
WL_RD
writeB
K
EN
DIO<c>
MC
row<r>
BLB
BL
WL_WR1
MC
128MCMC
VVDD<r>
BL_RD
256
WLglobal BKsel
Address<0:10>
8:256 3:8
BKsel
WLglobal
1[1]
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256Kb 65nm Sub-VT memory
Test chip addressing the sub-VT problems using 10T bitcell:1.89mm by 1.12mm.
Chip functions to below 400mV, holds without error to <250mV: At 400mV, 3.28mW and 475kHz at 27oC.
Reads without error to 320mV (27oC) and 360mV (85oC).Write without error to 380mV (27oC) and 350mV (85oC).
[1]
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Simulation results
Chip functioned correctly to below 400mV. Scope plot shows 300mVoperation; at this low voltage, some bit errors were observed[1].
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Power Measurements
Relative to 0.6V 6T SRAM, 2.2X less leakage power at 0.4V and 3.3X less leakage power at 0.3V >60X less leakage power than 1.2V
[1]
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Active Energy Savings with 10T Bitcell
200MHz at 1.2V
6T memories in 65nm usually at 0.9V or greater (lowest reported is 0.7V).
Operating 10T bitcell at lower voltages saves energy.
10T memory can provide high frequency operation at higher voltages when necessary.
[1]
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VDD Scaling Limits
Redundancy and/or boosted WL account for mismatch
1x1 redundancy and WL boosting:
Read works to 320mVWrite works to
380mV
1 column (of 1024)
2 cols
3 cols
Read Bit Errors
Write Bit Errors
1 row (of 2048)
4 rows
5 rows
[1]
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Conclusions
Standard 6T approach limited to ~0.6-0.7V and 16 cells per bitline.
Proposed 10T bitcell shows sub-threshold operation with overall power and energy savings.
Sub-VT memory requires circuits and architectures to manage variability and low Ion/Ioff.
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A read SNM free SRAM
• decreases in Read SNM in conventional SRAM cells:
• When SNM>0mV, stable data retention is still achieved even
though the voltage at Node V1 may slightly exceed “0”.
• When SNM<0mV, however, reversal data is overwritten.
1) Node V1 voltage greatly exceeds “0”.
2) Node V2 voltage falls below “1” because Node V1 voltage reaches
the CMOS inverter logic threshold voltage (P2, N2).
3) The fall in Node V2 voltage raises Node V1 voltage further
resulting in the overwriting of reversal data. [3]
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Cont’d
[3]
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Proposed read SNM free SRAM
N5 is added between Node V2 and NMOS transistor N2.
When the cell is not accessed /WL is high and when the cell is accessed /wl is low.
N5 prevents V2 from decreasing and thus the data bit is not reversed even if SNM equals zero.
Period of /activation is less than V2 retention time.
[3]
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Cont’d
A useless gap equal to one transistor results since 7 is a prime number.
A PMOS and an NMOS transistor are placed, respectively, in GAP (P) and GAP (N), between two L-shaped SRAM cells.
Solution: combining the SRAM cell and the sensing circuit.
[3]
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Measurement results
Organization:Clock access time:
Power consumption:Supply voltage:Process technology:
Macro size:Cell size:
4Kword x 16b1.2 ns, at 1.0 V20 ns, at 0.5 V12.9 mA/GHz, at 1.0 V1.0V to 0.44 V90-nm ASPLA CMOS,NMOS Vth: 0.32V,PMOS Vth: -0.33V0.4 mm x 0.7 mm2.09 μm2 (based on logic rules)
Vdd-min decreases with increasing temperature. Vdd-min is determined by the write SNM, which, unlike Read SNM, improves with decreasing Vth levels in NMOS transistors, and Vth decreases with increasing temperature.
[3]
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SRAM macro layout and chip microphotograph
Since both Write SNM and SRAM cell current improve with decreasing Vth levels in NMOS transistors, it is possible to achieve even higher-speed and lower- Vdd operations by reducing Vth levels below 0.32V,
[3]
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REFERENCES
[1]. A 256kb Sub-threshold SRAM in 65nm CMOS
Benton H. Calhoun, Anantha Chandrakasan Massachusetts Institute of Technology, Cambridge, MA ISSCC 2006 / SESSION 34 / SRAM / 34.4
[2]. Analyzing Static Noise Margin for Subthreshold
SRAM in 65nm CMOS Benton H. Calhoun and Anantha Chandrakasan MIT, 50 Vassar St 38-107, Cambridge, MA, 02139 USA {bcalhoun,anantha}@mtl.mit.edu
[3]. A Read-Static-Noise-Margin-Free SRAM
Cell for Low-Vdd and High-Speed Applications
ISCC 2005 / SESSION 26 / STATIC MEMORY / 26.3Koichi Takeda1, Yasuhiko Hagihara1, Yoshiharu Aimoto2, Masahiro Nomura1, Yoetsu Nakazawa1, Toshio Ishii2, Hiroyuki Kobatake
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THANK YOU…