1 ( 10 points) 6 min. · 2016-05-05 · ee201_final_sp2012_q2_for_ee101.fm 4/22/16 ee201l midterm...

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ee201_midterm2_Sp2010.fm 4/30/10 EE201L Midterm #2 - Spring 2010 1 / 12 C Copyright 2010 Gandhi Puvvada Spring 2010 EE201L Instructor: Gandhi Puvvada Midterm Exam 2 (20%) Date: April 30, 2010, Friday Open-Book Open-Notes Exam Time: 4-6:20PM SGM101 Name: Total points: 238 Perfect score: 220 /238 1 ( 10 points) 6 min. Memory width and depth expansion: Build an 8Kx8 using the following 4 chips: -- one 8Kx4 chips making the left 8Kx4 -- two 2Kx4 chips and a 4Kx4 making the right 8Kx4 Complete the design below. Add missing labels, address pin labels,wires, and gates. 2Kx4 8Kx4 4Kx4 2Kx4 D3-D0 A -A0 OE WE 2Kx4 RAM CS D3-D0 A -A0 OE WE 8Kx4 RAM CS D3-D0 A -A0 OE WE 4Kx4 RAM CS OE WE D3-D0 A -A0 OE WE 2Kx4 RAM CS Notes and handouts in ring binders only

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Page 1: 1 ( 10 points) 6 min. · 2016-05-05 · ee201_final_Sp2012_Q2_for_ee101.fm 4/22/16 EE201L Midterm #2 ... 18 min. Topic: Memory 2.1 Memory map reading and interpreting: State the size

ee201_midterm2_Sp2010.fm

4/30/10 EE201L Midterm #2 - Spring 2010 1 / 12C Copyright 2010 Gandhi Puvvada

Spring 2010 EE201L Instructor: Gandhi Puvvada Midterm Exam 2 (20%) Date: April 30, 2010, Friday Open-Book Open-Notes Exam Time: 4-6:20PM SGM101

Name: Total points: 238Perfect score: 220 /238

1 ( 10 points) 6 min.

Memory width and depth expansion: Build an 8Kx8 using the following 4 chips: -- one 8Kx4 chips making the left 8Kx4 -- two 2Kx4 chips and a 4Kx4 making the right 8Kx4

Complete the design below. Add missing labels, address pin labels,wires, and gates.

2Kx4

8Kx4 4Kx4

2Kx4

D3-D0

A -A0

OE

WE

2Kx4 RAM

CS

D3-D0

A -A0

OE

WE

8Kx4 RAM

CS

D3-D0

A -A0

OE

WE

4Kx4 RAM

CS

OE

WE

D3-D0

A -A0

OE

WE

2Kx4 RAM

CS

Notes and handouts in ring binders only

Page 2: 1 ( 10 points) 6 min. · 2016-05-05 · ee201_final_Sp2012_Q2_for_ee101.fm 4/22/16 EE201L Midterm #2 ... 18 min. Topic: Memory 2.1 Memory map reading and interpreting: State the size
Page 3: 1 ( 10 points) 6 min. · 2016-05-05 · ee201_final_Sp2012_Q2_for_ee101.fm 4/22/16 EE201L Midterm #2 ... 18 min. Topic: Memory 2.1 Memory map reading and interpreting: State the size

ee201_Final_Sp2013.fm

May 9, 2013 6:16 pm EE201L Final - Spring 2013 1 / 7C Copyright 2013 Gandhi Puvvada

Spring 2013 EE201L Instructor: Gandhi Puvvada Final Exam (20%) Date: May 9, 2013, Thursday Open-Book Open-Notes Exam Time: 7:30-10:20AM SGM124

Name: Total points: 253Perfect score: 230 / 253

1 ( 20 + 6 = 26 points) 10 min.

Memory width and depth expansion: Build an 8Kx8 ROM memory (with an overall CS chip-select) using the 7 smaller ROM chips as shown in the map on the side. The 8Kx8 ROM has _____ address pins and _______ data pins.Complete the design below. Add missing labels, wires, and gates.

1.1 A ROM can not be used as a RAM (=RWM) because you can’t ________ (read from / write to) it.____________ (However / Also) a RAM (=RWM) ________ (can’t / can) be used as a ROM because _____________________________________________________________________________________________________________________________________________________________________________________________________________________________

1Kx8

4Kx4

4Kx2

4Kx2

1Kx81Kx81Kx8

#0

#4

#5

#6

#7

#1#2

O7-O0

A9-A0

OE

1Kx8 ROM

CE

A11-A0

OE

4Kx4 ROM

CEO1-O0

A11-A0

OE

4Kx2 ROM

CE

4Kx2 ROM

O3-O0

#4

#1#2 #0

O7-O0

A9-A0

OE

1Kx8 ROM

CE#5

O7-O0

A9-A0

OE

1Kx8 ROM

CE#6

O7-O0

A9-A0

OE

1Kx8 ROM

CE#7

Y0A0

G

Y1

Y2

Y3

A1

2 to 4 decoder

6pts

Page 4: 1 ( 10 points) 6 min. · 2016-05-05 · ee201_final_Sp2012_Q2_for_ee101.fm 4/22/16 EE201L Midterm #2 ... 18 min. Topic: Memory 2.1 Memory map reading and interpreting: State the size

ee201_Final_Sp2013.fm

May 9, 2013 12:06 am EE201L Final - Spring 2013 1 / 7C Copyright 2013 Gandhi Puvvada

Spring 2013 EE201L Instructor: Gandhi Puvvada Final Exam 2 (25%) Date: May 9, 2013, Thursday Open-Book Open-Notes Exam Time: 7:30-10:20AM SGM124

Name: Total points: Perfect score:

1 ( points) min.

Memory width and depth expansion: Build an 8Kx8 ROM memory (with an overall CS chip-select) using the 7 smaller ROM chips as shown in the map on the side. The 8Kx8 ROM has _____ address pins and _______ data pins.Complete the design below. Add missing labels, wires, and gates.

1.1 A ROM can not be used as a RAM (=RWM) because you can’t ________ (read from / write to) it.____________ (However / Also) a RAM (=RWM) ________ (Can’t / can) be used as a ROM because _____________________________________________________________________________________________________________________________________________________________________________________________________________________________

1Kx8

4Kx4

4Kx2

4Kx2

1Kx81Kx81Kx8

#0

#4

#5

#6

#7

#1#2

O7-O0

A9-A0

OE

1Kx8 ROM

CE

A11-A0

OE

4Kx4 ROM

CS

O1-O0

A11-A0

OE

4Kx2 ROM

CS

4Kx2 ROM

O3-O0

#4

#1#2 #0

O7-O0

A9-A0

OE

1Kx8 ROM

CE#5

O7-O0

A9-A0

OE

1Kx8 ROM

CE#6

O7-O0

A9-A0

OE

1Kx8 ROM

CE#7

Y0A0

G

Y1

Y2

Y3

A1

2 to 4 decoder

Page 5: 1 ( 10 points) 6 min. · 2016-05-05 · ee201_final_Sp2012_Q2_for_ee101.fm 4/22/16 EE201L Midterm #2 ... 18 min. Topic: Memory 2.1 Memory map reading and interpreting: State the size

ee201_midterm2_Sp2011.fm

4/30/11 EE201L Midterm #2 - Spring 2011 8 / 12C Copyright 2011 Gandhi Puvvada

4 ( 12 + 6 + 4 = 22 points) 20 min.

4.1 Memory depth expansion: Build an 32Kx8 using the following 3 chips: -- one 16Kx8 and two 8Kx8 chips

Complete the design below. Add missing labels, address pin labels, wires, and gates.

4.2 State the starting and ending addresses of 32K range of addresses consisting of the system address 12345678H . This 32K range resides in a system of 4 giga (232 = 1 Giga) address space (00000000H - FFFFFFFFH). ___________________________________________Break that 32KB range into two 16KB ranges. (1) ____________________________ (2) ____________________________

4.3 The following range of address in a 1Mega address space (220 = 1 M) is not a natural range: 24000H to 37FFFH . State the size of this range in Kilo-locations (example 333K) ___________

8Kx8

16Kx8

8Kx8

12 pts

D -D0

A -A0

OE

WE

8Kx8 RAM

CS

D -D0

A -A0

OE

WE

16Kx8 RAM

CS

D -D0

A -A0

OE

WE

8Kx8 RAM

CS

6 pts

4 pts

Page 6: 1 ( 10 points) 6 min. · 2016-05-05 · ee201_final_Sp2012_Q2_for_ee101.fm 4/22/16 EE201L Midterm #2 ... 18 min. Topic: Memory 2.1 Memory map reading and interpreting: State the size

ee201_midterm2_Sp2011.fm

4/29/11 EE201L Midterm #2 - Spring 2011 8 / 12C Copyright 2011 Gandhi Puvvada

4 ( 12 + 6 + 4 = 22 points) 20 min.

4.1 Memory depth expansion: Build an 32Kx8 using the following 3 chips: -- one 16Kx8 and two 8Kx8 chips

Complete the design below. Add missing labels, address pin labels, wires, and gates.

4.2 State the starting and ending addresses of 32K range of addresses consisting of the system address 12345678H . This 32K range resides in a system of 4 giga (232 = 1 Giga) address space (00000000H - FFFFFFFFH). ___________________________________________Break that 32KB range into two 16KB ranges. (1) ____________________________ (2) ____________________________

4.3 The following range of address in a 1Mega address space (220 = 1 M) is not a natural range: 24000H to 37FFFH . State the size of this range in Kilo-locations (example 333K) ___________

8Kx8

16Kx8

8Kx8

12 pts

D -D0

A -A0

OE

WE

8Kx8 RAM

CS

D -D0

A -A0

OE

WE

16Kx8 RAM

CS

D -D0

A -A0

OE

WE

8Kx8 RAM

CS

6 pts

4 pts

Page 7: 1 ( 10 points) 6 min. · 2016-05-05 · ee201_final_Sp2012_Q2_for_ee101.fm 4/22/16 EE201L Midterm #2 ... 18 min. Topic: Memory 2.1 Memory map reading and interpreting: State the size

ee201_final_Sp2012_Q2_for_ee101.fm

4/22/16 EE201L Midterm #2 - Spring 2012 1 / 2 C Copyright 2012 Gandhi Puvvada

2 ( 7+15=22 points) 18 min. Topic: Memory

2.1 Memory map reading and interpreting: State the size and range of the shaded area in the map on the side. Assume that there is a RAM memory chip occupying that area and generate a low active chip-select signal CS when an address appears on A19-A0 which falls in the shaded area. Label the address pins and complete the address connections to the RAM chip below.

2.2 What are the sizes of the 10 memory chips. Using all of them build as big a byte-wide memory system as possible. Produce CSLL (Chip-Select Left Lower), CSLU (Chip-Select Left Upper) and CSR (Chip-Select Right) as function of the overall CS and label the address pins.

00000

FFFFF7pts

D7-D0

A -A0

OE

WECSCS

MEMW

MEMR

D7-D0

Size: __________Range: _________

15pts

D0

A9-A0

OEWECSCSLU

MEMW

MEMR

D0D0D0

D0

A9-A0

OEWECSCSLL

MEMW

MEMR

D0D0D0

D1-D0

A10-A0

OEWECSCSR

MEMW

MEMR

D1-D0

Out of the 10 chips, 8 are of ______________ sizeand two are of _______________ size.Putting these together, you formed x8 size memory,

Page 8: 1 ( 10 points) 6 min. · 2016-05-05 · ee201_final_Sp2012_Q2_for_ee101.fm 4/22/16 EE201L Midterm #2 ... 18 min. Topic: Memory 2.1 Memory map reading and interpreting: State the size

ee201_final_Sp2012_Q2_for_ee101.fm

4/22/16 EE201L Midterm #2 - Spring 2012 2 / 2 C Copyright 2012 Gandhi Puvvada