Въведение в vhdl ... - lark.tu-sofia.bg · start_stop clear counter and display ce. 1...
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Проектиране на Крайни
Автомати с VHDL
Въведение в VHDL
© 2011 Dr. Vassiliy Tchoumatchenko
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Диаграма на Състоянията на Краен Автомат
State 0
X <= ‘0’Y <= ‘1’
State 1
X <= ‘1’Y <= ‘1’
State 2
X <= ‘1’Y <= ‘0’
A = ‘1’B = ‘1’
A = ‘1’
B = ‘1’
1
1
2
2
Reset
State0X <= ‘0’Y <= ‘1’
Състояние
A = ‘0’
Преход
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Видове Крайни Автомати
Stateregister
Nextstatelogic
OutputLogic
Moore – Изхода зависи само от текущото състояниеMealy – Изхода зависи от текущото състояние и от входа
Inputs
Outputs
Clock
Reset
Next State
Current State
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Кодиране на Състоянията
Съответствие между символните имена на състоянията и конкретните двоичнистойности.
Критерии за избор на кодиране:
–Минимален брой тригери
–Сложност на декодиращата логика
–Минимален брой променящи се битове при преход от състояние в състояние
Binary000001010011100
Gray000001011010110
One-Hot0000100010001000100010000
Zero-Hot1111011101110111011101111
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Методология на Проектиране на Крайни Автомати с VHDL
1. Проектиране на алгоритъма на работа и представянето му като диаграма насъстоянията.
2. Определяне на входовете и изходите. Съставяне на интерфейсната част на VHDL модела.
3. Описание на състоянията посредством изброими типове. Дефиниане на типовеи сигнали.
4. Регистър на състоянието
5. Логика за следващо състояние
6. Логика за изходите
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© 2011 Dr. Vassiliy Tchoumatchenko
Структура на VHDL Модела
ProcessStateRegister
ProcessNextStateLogic
ProcessOutputLogic
Signal NextState
Signal CurrentState
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VHDL Код
architecture FSM of DEMO istype StatesEnumeration is ( S1, S2, … );signal CurrentState : StatesEnumeration;signal NextState : StatesEnumeration;
beginStateRegister: process(clock, reset)...
end process;
NextStateLogic: process(CurrentState, входове)...
end process;
OutputLogic: process(CurrentState)...
end process;end FSM;
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Пример
architecture Behavioral of FSM istype StateType is (S0, S1, S2);signal CurrentState, NextState : StateType;
beginStateRegister: process(clk, reset)begin
if(reset = '1')thenCurrentState <= S0;
elsif(rising_edge(clk))thenCurrentState <= NextState;
end if;end process;
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NextStateLogic: process (CurrentState, a, b) begin
case CurrentState iswhen S0 =>
if(a = '1')thenNextState <= S1;
elsif (b = '1')thenNextState <= S2;
elseNextState <= S0;
end if;when S1 =>
if(a = '1')thenNextState <= S2;
elsif (b = '1')thenNextState <= S0;
elseNextState <= S1;
end if;when S2 => NextState <= S0;when others => NextState <= S0;end case;
end process;
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OutputLogic: process (CurrentState) begincase CurrentState iswhen S0 =>
x <= '0';y <= '1';
when S1 =>x <= '1';y <= '1';
when S2 => x <= '1';y <= '0';
when others => null;end case;
end process;end Behavioral;
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Пример – Хронометър
Проектиране на управляваща логика за хронометър
STOPWATCHRESET
START_STOP
CLEARCounter and
Display
CE
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1 State Diagram
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2 Entity
library IEEE;
use IEEE.std_logic_1164.all;
entity STOPWATCH is
port( CLK, RESET, START_STOP: in std_logic;
CE, CLEAR: out std_logic);
end STOPWATCH;
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3 States Enumeration
architecture FSM of STOPWATCH is
type STATE_TYPE is (ZERO, START, COUNT, STOP, STOPPED);
...
begin
...
end FSM;
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4 State Register
architecture FSM of STOPWATCH_CTRL is
type STATE_TYPE is (ZERO, START, COUNT, STOP, STOPPED);
signal CURRENT_STATE, NEXT_STATE : STATE_TYPE;
begin
STATE_REG: process(CLK, RESET)
begin
if(RESET = '0')then
CURRENT_STATE <= ZERO;
elsif(rising_edge(CLK))then
CURRENT_STATE <= NEXT_STATE;
end if;
end process;
...
end FSM;
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5 Next State Logic
NS_LOGIC: process (CURRENT_STATE, START_STOP) begincase CURRENT_STATE iswhen ZERO =>
if(START_STOP = '1')thenNEXT_STATE <= START;
elseNEXT_STATE <= ZERO;
end if;when START =>
if(START_STOP = '1')thenNEXT_STATE <= START;
elseNEXT_STATE <= COUNT;
end if;when COUNT =>
if(START_STOP = '1')thenNEXT_STATE <= STOP;
elseNEXT_STATE <= COUNT;
end if;
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5 Next State Logic
when STOP =>if(START_STOP = '1')then
NEXT_STATE <= STOP;else
NEXT_STATE <= STOPPED;end if;
when STOPPED =>if(START_STOP = '1')then
NEXT_STATE <= START;else
NEXT_STATE <= STOPPED;end if;
when others =>NEXT_STATE <= ZERO;
end case;end process;
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6 Output Logic
OUTPUT_LOGIC: process(CURRENT_STATE) begin
case CURRENT_STATE is
when ZERO =>
CE <= '0'; CLEAR <= '1';
when START =>
CE <= '1'; CLEAR <= '0';
when COUNT =>
CE <= '1'; CLEAR <= '0';
when STOP =>
CE <= '0'; CLEAR <= '0';
when STOPPED =>
CE <= '0'; CLEAR <= '0';
when others =>
CE <= '0'; CLEAR <= '1';
end case;
end process;
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