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QPI and PCI

INTRODUCTION

Short for Peripheral Component Interconnect,

PCI was introduced by Intel in 1992. The PCI bus

Came in both 32-bit(133MBps) and 64-bit versions

and was used to attach hardware to a computer.

Although commonly used in computers from the late

1990s to the early 2000s, PCI has since been

replaced with PCI Express.

PCI (Peripheral Component Interconnect) is an interconnection

system between a microprocessor and attached devices in which

expansion slots are spaced closely for high speed operation. Using PCI,

a computer can support both new PCI cards while continuing to

support Industry Standard Architecture (ISA) expansion cards, an

older standard. Designed by Intel, the original PCI was similar to the

VESA Local Bus . However, PCI 2.0 is no longer a local bus and is

designed to be independent of microprocessor design. PCI is designed

to be synchronized with the clock speed of the microprocessor

The PCI specifications define two different card lengths. The

full-size PCI form factor is 312 millimeters long; short PCIs range

from 119 to 167 millimeters in length to fit into smaller slots

where space is an issue. Like the full-size PCI, the short PCI is a

high-performance I/O bus that can be configured dynamically for

use in devices with high bandwidth requirements. Most current

PCI cards are half-sized or smaller. There are a number of

variations of PCI, including CompactPCI, Mini PCI, Low-Profile

PCI, concurrent PCI, and PCI-X.

SAMPLE OF PCI DEVICES

Modem

Network card

Sound card

Video card

FREQUENCY SPECIFICATIONS

QPI operates at a clock rate of 2.4 GHz, 2.93 GHz, 3.2 GHz, 4.0 GHz

or 4.8 GHz (4.0 GHz frequency is introduced with the Sandy Bridge-

E/EP platform and 4.8 GHz with the Haswell-E/EP platform). The clock

rate for a particular link depends on the capabilities of the components

at each end of the link and the signal characteristics of the signal path

on the printed circuit board. The non-extreme Core i7 9xx processors

are restricted to a 2.4 GHz frequency at stock reference clocks. Bit

transfers occur on both the rising and the falling edges of the clock, so

the transfer rate is double the clock rate.

Intel describes the data throughput (in GB/s) by counting only

the 64-bit data payload in each 80-bit "flit". However, Intel then

doubles the result because the unidirectional send and receive

link pair can be simultaneously active. Thus, Intel describes a 20-

lane QPI link pair (send and receive) with a 3.2 GHz clock as

having a data rate of 25.6 GB/s. A clock rate of 2.4 GHz yields a

data rate of 19.2 GB/s. More generally, by this definition a two-

link 20-lane QPI transfers eight bytes per clock cycle, four in each

direction.