※Inner Block Diagram

0.8V

R1

Application note

Ramp Pin and CT Pin are connected with BJT, R, C.

Refer on the right side file

1. How make the waveform of ramp pin?

CT Pin is connected with ramp through Q9(NPN BJT) through R3 and C2.

In my opinion is, at first Q9 get the signal from CT and then turn on-off of BJT base. so the ramp waveform get the slope(τ, tau)

based on the value of R3 and C2. It is my opinion. How do you think?

2. What is the purpose of R1. (R1 is located between CS Pin and Ramp pin)

3. What is the purpose of 0.8V? See the upper block diagram.

1. Related with Ramp Pin …

2. Related with Refer Pin …

1. What is the purpose of R(①)?

and why is the “R” connected between Ref and EAP?

2. Once output load or output voltage is increased, EAP pin voltage is increased. what is the reason?

As you know, once the photo diode flows the current via A to K, the diode release the light emitting, and then the photo tr works.

once I think about that… when the output load(or output voltage) is increased, the photo diode has got the much light emitting

and then the voltage (C-E) of photo tr might be decreased, therefore the EAP voltage might be decreased.

however, the EAP voltage is increased based on the test result(see the upper ② table).

I am so curious. Why it is different between my thought and test result

The R(①) is connected between Ref and EAP

Load[A] EAP[V]0 1.535 1.61

10 1.6815 1.7620 1.8625 1.9827 2.0329 2.0930 2.11

② EAP Voltage according to output load at my test power

board

③ Photo coupler composition

The circuit using UCC2895

in my SMPS

①

3. Related with the OC limit…

※ the OC limit of CS Pin is composed of the comparator , 2V and 2.5V.

1. What is the difference between 2V and 2.5V?

2. What is the role of this line?

3. As you know, the over current(OC) limit is 2V(or 2.5V) according to UCC2895 data sheet

but, even though my SMPS is not reached until 2V(or 2.5V), the SMPS has the OC limit.

I will explain this in detail. Please see the next page.

4. CS Pin OC Limit waveform…

EA+pin-ch1

　　

EA+ Ramp CS CT

Vrms[V] Vp[V] Vp[V] Vp[V]

Before OC Limit(@normal sta-tus)

1.8 1.4 0.8 2.5

After OC Limit(over current sta-tus)

1.9 1.4 1.4 2.5

CT Pin-ch4

Ramp pin-ch2 CS Pin-ch3

① the waveform before OC Limit.It is normal status

② after OC Limit

※ According to the block diagram, the CS pin is composed of comparator 2V and 2.5V.

So the condition of OC limit is over 2 or 2.5V.

but once I tested my SMPS board, the over current is operated at the same Vpeak(ramp and CS), even though my SMPS

is not

reached until 2V(or 2.5V), the SMPS has the OC limit. Please see upper table and waveform(② after OC limit)

So I thought, the OC limit is related with the voltage peak between ramp and CS.

How do you think about that? And let me know your opinion.

Vpeak of ramp and CS have the same Vpeak

at the moment of OC limit status.