© digital integrated circuits 2nd design methodologies sequential logic 2 storage mechanisms...

© Digital Integrated Circuits2nd Design Methodologies

Sequential LogicSequential Logic

2 storage mechanisms

• positive feedback

• charge-based

COMBINATIONALLOGIC

Registers

Outputs

Next state

CLK

Q D

Current State

Inputs


A simple example of sequential designA simple example of sequential designA one-input, one-output system receives a binary sequence (one bit at each clock cycle) and produces another binary sequence such that the output is 1 whenever a leading subsequence of odd 0s and odd 1s is recognized in the input sequence. For example, the input sequence of

01101010010001111110000100…… causes the output

01000100010100000001010000.


Digital Integrated Digital Integrated CircuitsCircuitsA Design PerspectiveA Design Perspective

VLSI DesignVLSI DesignMethodologiesMethodologies

Jan M. RabaeyAnantha ChandrakasanBorivoje Nikolic

Revised from Digital Integrated Circuits, © Jan M. Rabaey el


Design Abstraction LevelsDesign Abstraction Levels

n+n+S

GD

+

DEVICE

CIRCUIT

GATE

MODULE

SYSTEM


The Design Productivity ChallengeThe Design Productivity Challenge

Source: sematech97

A growing gap between design complexity and design productivity

Designing a multi-million transistor circuit is not possible without good design methodologies and computer tools

58%/Yr. compoundComplexity growth rate

21%/Yr. compoundProductivity growth rate

198

1

10

Log

ic T

ran

sist

ors

pe

r C

hip

(K

)

Pro

du

ctiv

ity (

Tra

ns.

/Sta

ff-M

on

th)

100

1,000

10,000

100,000

1,000,000

10,000,000

1

XX

X XX

X

x

100

1,000

10,000

100,000

1,000,000

10,000,000

100,000,000

10

2.5m

.35m

.10m

198

3

198

5

198

7

198

9

199

1

199

3

199

5

199

7

199

9

200

1

200

3

200

5

200

7

200

9

Transistor/Staff Month


A Simple ProcessorA Simple Processor

MEMORY

DATAPATH

CONTROLIN

PU

T/O

UT

PU

T

These components occurs in almost all processors

Datapath is core of the processor. A typical datapath consists of logic units (AND, OR, XOR etc) and arithmetic operators (ADDER, MULTIPLIER, COMPARATOR, SHIFTER etc)

Control unit can be viewed as a finite state machine.

Memory stores data and instructions.


A Simple ProcessorA Simple Processor

What might be abstracted away from the schematic is interconnection networks, such as on-chip buses, clock and power distribution networks.

For a long time, interconnection network was a afterthought, but due to technology migration, interconnects presents capacitive, resistive and inductive effects, which might affect the system performance.

MEMORY

DATAPATH

CONTROLIN

PU

T/O

UT

PU

T


A System-on-a-Chip: ExampleA System-on-a-Chip: Example

Courtesy: Philips

The simple structure shown in previous slide can be repeated many times on silicon, e.g. a IC chip for HDTV


Impact of Implementation ChoicesImpact of Implementation Choices Choosing an effective implementation approach strongly depends on the function of the modules under consideration.

The choice of implementation can have a tremendous effect on the quality of the final product.

A design with flexibility is very attractive from application point of view. But it comes at a price in both performance and power efficiency.

Providing flexibility also means additional hardware overhead.

Hardware/software co-design (partitioning, task scheduling, resource allocation etc)


Impact of Implementation ChoicesImpact of Implementation ChoicesE

nerg

y E

ffic

ienc

y (i

n M

OP

S/m

W)

Flexibility(or application scope)

0.1-1

1-10

10-100

100-1000

None Fullyflexible

Somewhatflexible

Har

dwire

d cu

stom

Con

figur

able

/Par

amet

eriz

able

Dom

ain

-spe

cific

pro

cess

or(e

.g.

DS

P)

Em

bedd

ed m

icro

proc

ess

or


Design MethodologyDesign Methodology

• Design process traverses iteratively between three abstractions: behavior, structure, and geometry• More and more automation for each of these steps


Implementation ChoicesImplementation Choices

Custom

Standard CellsCompiled Cells

Ma cro Cells

Cell-based

Pre-diffused(Gate Arrays)

Pre-wired(FPGA's)

Array-based

Semicustom

Digital VLSI Implementation Approaches

A number of distinct implementation approaches ranging from high-performance, handcrafted design to fully programmable medium-to-low performance design


The Custom Approach The Custom Approach When performance or design density is of primary importance, handcrafting the design (at both logic level and layout level) seems to be the only option.

The labor–intensive nature of custom design translates into a high cost and long time to market. So, it should be used only under some conditions.

With continuous progress in design automation tools and rapid increase of circuit complexity, full-custom design is reducing.

In fact, library cell design is the only area where custom design still thrives today.

Design support/assistance tools are needed.


The Custom Approach The Custom Approach

Intel 4004

Courtesy Intel


Transition to Automation and Regular StructuresTransition to Automation and Regular Structures

Intel 4004 (‘71)Intel 4004 (‘71)Intel 8080Intel 8080 Intel 8085Intel 8085

Intel 8286Intel 8286 Intel 8486Intel 8486Courtesy Intel



Custom


Ma cro Cells

Cell-based


Pre-wired(FPGA's)

Array-based

Semicustom

Digital VLSI Implementation Approaches



Cell-based DesignCell-based Design Since custom-design approach proves to be prohibitively expensive, a wide variety of design approaches have been introduced to shorten and automate the design process.

The idea behind cell-based design is to reduce the implementation effort by reusing a library of limited cells.

The advantage of the approach is that the cells only need to be designed and verified once for a given technology, and can be reused many times.

The disadvantage is that constrained nature of the library reduces the possibility of fine-tuning the design.

Cell-based approaches can be partitioned into a number of classes depending on the granularity of the library elements.


Cell-based Design (or standard cells)Cell-based Design (or standard cells)

Cells are placed in rows that are separated by routing channels. This requires that all cells have equal height.

Routing channel requirements arereduced by feedthrough cells and more interconnect layers (three dimensional designs)

Functionalmodule(RAM,multiplier,…)

Routingchannel

Logic cellFeedthrough cell

Row

s o

f ce

lls

Standard cell approach standardizes the design entry level at the logic gate.


Standard Cell — ExampleStandard Cell — Example

[Brodersen92]

Today’s standard cell typically employs many versions of each cell, sized for different driving strengths, as well as performance and power consumption level. It is left to synthesis tools to select the correct cells.


Standard Cell – The New GenerationStandard Cell – The New Generation

Cell-structure hidden under interconnect Layers (more interconnect layers). Only a small fraction of the area is wasted for interconnect.


Standard Cell - ExampleStandard Cell - Example

3-input NAND cell(from ST Microelectronics 0.18um):C = Load capacitanceT = input rise/fall time


A Historical Perspective: the PLAA Historical Perspective: the PLA

x0 x1 x2

ANDplane

x0x1

x2

Product terms

ORplane

f0 f1


Two-Level LogicTwo-Level Logic

Inverting format (NOR-NOR) more effective

Every logic function can beexpressed in sum-of-productsformat (AND-OR)

minterm


PLA Layout – Exploiting RegularityPLA Layout – Exploiting Regularity

f0 f1x0 x0 x1 x1 x2 x2

Pull-up devices Pull-up devices

VDD GNDAnd-Plane Or-Plane


Breathing Some New Life in PLAsBreathing Some New Life in PLAsRiver PLAs A cascade of multiple-output PLAs. Adjacent PLAs are connected via river routing.

PRE-CHARGE

PR

E-

CH

AR

GE

PRE-CHARGE

PR

E-C

HA

RG

E

BUFFER

BUFFER

BU

FF

ER

BU

FF

ER

PRE-CHARGE

PR

E-C

HA

RG

E

BUFFER

BU

FF

ER

PRE-CHARGE

PR

E-

CH

AR

GE

BUFFERB

UF

FE

R

• No placement and routing needed. • Output buffers and the input buffers

of the next stage are shared.

Courtesy B. Brayton


Compiled Cell / Automatic Cell GenerationCompiled Cell / Automatic Cell Generation

Courtesy Acadabra

Initial transistorgeometries

Placedtransistors

Routedcell

Compactedcell

Finishedcell

Customized cells are still attractive, hence automated cell generation with adjusted sizes is needed


Macro/Mega Modules and IP blocksMacro/Mega Modules and IP blocks Standardizing at the logic-gate level is attractive for random logic functions, but it turns out to be inefficient for more complex structures such as data paths, memory, microprocessor etc.

By capturing the specific nature of some larger blocks, implementations can be obtained that outperform the standard cell approach.

Cells with a complexity that surpasses what is found in a typical standard cell library are called macrocells/megacells.

Macrocells can also be identified as hard macro or soft macro.


Hard macrocellHard macrocell A hard macro cell represents a module with a given functionality and a pre-determined physical design.

In essence, a hard macro represents a custom design of the requested function (in some cases with parameterization)

The advantage of the hard macro is that it brings with it all the good properties of custom design, and can be reused many times.

The disadvantage is that it is hard to port the design to other technologies.


A hard parameterized macrocellA hard parameterized macrocell

25632 (or 8192 bit) SRAM in 0.18um technologyGenerated by hard-macro module generator/compiler


Soft MacroModulesSoft MacroModules

Synopsys Design Compiler

Soft macro represents a module with a given functionality without a specific implementation, which may vary from instance to instance. It relies more on the semi-custom design approaches. (Mostly need standard cell at lower level).


““Intellectual Property”Intellectual Property” Nowdays, with increasing complexity, circuits are built with more and more reusable building blocks of increasing complexity.

Typically, these modules are acquired from third-party vendors. Macrocells distributed in this way are called Intellectual Property (IP).

Good examples of IP are embedded microprocessors and microcontrollers, DSP processors, FFT module, filter modules, error-correction modules, encoding and decoding modules, etc.

Design of a complex system is becoming an exercise of reuse in different levels of granularity. Future system will use a blend of design styles and design modules.


A Protocol Processor for Wireless

IP block

Soft macrocells

Custom module


Semicustom (cell-based) Design FlowSemicustom (cell-based) Design Flow

HDLHDL

Logic SynthesisLogic Synthesis

FloorplanningFloorplanning

PlacementPlacement

RoutingRouting

Tape-out

Circuit ExtractionCircuit Extraction

Pre-Layout Simulation

Pre-Layout Simulation

Post-Layout Simulation

Post-Layout Simulation

StructuralStructural

PhysicalPhysical

BehavioralBehavioralDesign Capture

Des

ign

Iter

atio

nD

esig

n It

erat

ion

Cadence Encounter

(Synopsys design compiler)

Cadence Encounter

Cadence Primetime(Thermal, timing,

noise analysis)


The “Design Closure” ProblemThe “Design Closure” Problem

Courtesy Synopsys

Iterative Removal of Timing Violations (white lines)

At deep sub-micron, layout parasitics plays an important role. A design is forced to go though a number of iterations to have all timing constraints met. This is called “timing closure”.


Integrating Synthesis with Integrating Synthesis with Physical DesignPhysical Design

Physical SynthesisPhysical Synthesis

RTL (Timing) Constraints

Place-and-RouteOptimization

Place-and-RouteOptimization

Artwork

Netlist with Place-and-Route Info

MacromodulesFixed netlists



Custom


Ma cro Cells

Cell-based


Pre-wired(FPGA's)

Array-based

Semicustom

Digital Circuit Implementation Approaches




Pre-wired(FPGA's)

Array-based

Late-Binding ImplementationLate-Binding Implementation

All design methodologies discussed thus far require a complete run through design and fabrication process, which might lengthen time-to-market.

Consequently, a number of alternative implementation approaches are proposed that do not require a complete run through the manufacturing process, or they avoid dedicated processing completely.


Pre-diffused Gate Arrays / Sea-of-gatesPre-diffused Gate Arrays / Sea-of-gates In this approach, batches of wafers containing arrays of primitive cells or transistors are manufactured by the vendors.

All fabrication steps needed to make the transistors are standardized and executed without regard to the final application.

To transform these uncomitted wafers to an actual design, only the desired interconnections have to be added.


Pre-diffused Gate Arrays: Sea-of-gatesPre-diffused Gate Arrays: Sea-of-gates

rows of

cells

routing channel

uncommitted

VD D

GND

polysilicon

metal

possiblecontact

In1 In2 In3 In4

Out

UncommitedCell

CommittedCell(4-input NOR)

Contact predefined

The primary challenge is to determine the composition of primitive cell and the size of transistors such that the gate array template can be utilized to a maximal extent over a wide range of designs.


Sea-of-gate Primitive CellsSea-of-gate Primitive Cells

NMOS

PMOS

Oxide-isolation

PMOS

NMOS

NMOS

Using oxide-isolation Using gate-isolation


Example: Base Cell of Gate-Isolated GAExample: Base Cell of Gate-Isolated GA

n-well

contact

21GND2019181716151413121110987654321VDD

m2m1polyp-diffn-diffp-well

contact forisolator

continuousn-diff strip

continuousp-diff strip

From Smith97


Example: register in Gate-Isolated GAExample: register in Gate-Isolated GA

CLK

D

Q

GND

VDD

Q

CLR

From Smith97


Sea-of-gatesSea-of-gates

Random Logic

MemorySubsystem

LSI Logic LEA300K(0.6 m CMOS)

Courtesy LSI Logic

Utilization factor varies depending on the application.


The return of gate arrays?The return of gate arrays?

metal-5 metal-6

Via-programmable cross-point

programmable via

Via programmable gate array(VPGA)

[Pileggi02]

Exploits regularity of interconnect


Pre-wired ArraysPre-wired Arrays Pre-diffused arrays offer a faster road to implementation, but it would be even better if dedicated manufacturing steps could be avoided.

This leads to pre-processed die that can be programmed in the file to implement any logic function, called Field Programmable Logic Array (FPGA).

Two main issues in FPGA: how to implement the programmability and how to store the programmability


Pre-wired ArraysPre-wired Arrays Programming Technique (how to store?)

Fuse-based (program-once)

Non-volatile EEPROM based (read-only memory)

RAM based


Fuse-Based FPGAFuse-Based FPGA

antifuse polysilicon

n+ antifuse diffusion

2 l

From Smith97

Open by default, closed by applying current pulse, onlyone-time programmable


Nonvolatile EEPROM FPGANonvolatile EEPROM FPGA

From Smith97

Memory stores its value even when power is down (flash memory or EEPROM)

Once programmed, the logic remains functional until a new programming round.

Extra complexity and cost


Non-volatile memoryNon-volatile memory the transistor has two gates, a control gate (CG) and a floating

gate (FG) insulated all around by an oxide layer.

The FG is interposed between the CG and the MOS channel.

Because the FG is electrically isolated by its insulating layer, any electrons placed on it are trapped there and, under normal conditions, will not discharge for many years.

When the FG holds a charge, it partially cancels the electric field from the CG, which modifies the VT of the cell.

During read-out, a voltage is applied to the CG, and the MOSFET channel will become conducting or remain insulating, depending on the VT of the cell, which is in turn controlled by charge on the FG. The current flow through the MOSFET channel is sensed and forms a binary code, reproducing the stored data.


Non-volatile memoryNon-volatile memory

http://en.wikipedia.org/wiki/Flash_memory


Volatile RAM FPGAVolatile RAM FPGA

From Smith97

By far the most popular approach

Static RAM used, so lose value when power down. Thus, a re-loading of the program from an external permanent memory is needed every time power is on

Parallel interface is needed for today’s large size program


Pre-wired ArraysPre-wired Arrays Programmable Logic (how to implement

programmability?)

For logic function Array-Based Look-up Table

For interconnect Channel-routing Mesh networks


Array-Based Programmable LogicArray-Based Programmable Logic

PLA PROM PAL

I 5 I 4

O0

I 3 I 2 I 1 I 0

O1O2O3

Programmable AND array

ProgrammableOR array I5 I4

O0

I3 I2 I1 I0

O1O2O3

Programmable AND array

Fixed OR array

Indicates programmable connection

Indicates fixed connection

O0

I3 I2 I1 I0

O1O2O3

Fixed AND array

ProgrammableOR array

The later two are variants of the first one with one plane fixed


Programming a PROMProgramming a PROM

f0

1 X 2 X 1 X 0

f1NANA

: programmed node

x2x1x0


More Complex PALMore Complex PAL

From Smith97

programmable AND array (2i 3 jk) k macrocells

j -wide OR array

j

macrocell

productterms

D Q

A

1

j

B

CLK

OUT

C i i inputs

i inputs, j minterms/macrocell, k macrocells


2-input MUX2-input MUXas programmable logic blockas programmable logic block

FA 0

B

S

1

Configuration

A B S F=

0 0 0 00 X 1 X0 Y 1 Y0 Y X XYX 0 YY 0 XY 1 X X + Y1 0 X1 0 Y1 1 1 1

XYXY

XY

=AS+BS


Logic Cell of Actel Fuse-Based FPGALogic Cell of Actel Fuse-Based FPGA

A

B

SA Y

1

C

D

SB

1

S0S1

1


Look-up Table Based Logic CellLook-up Table Based Logic Cell

Out

ln1 ln2

Me

mory In Out

00 00

01 1

10 1

11 0

Programmable memory


LUT-Based Logic CellLUT-Based Logic Cell

Courtesy Xilinx

D4

C1....C4

xxxxxx

D3

D2

D1

F4

F3

F2

F1

Logicfunction

ofxxx

Logicfunction

ofxxx

Logicfunction

ofxxx

xx

xx

4

xxxxxx

xxxxxxxx

xxx

xxxx xxxx xxxx

HP

Bitscontrol

Bitscontrol

Multiplexer Controlledby Configuration Program

x

xx

x

xx

xxx xx

xxxx

x

xxxxxx

xx

x

xx

xxx

xx

Xilinx 4000 Series


Array-Based Programmable WiringArray-Based Programmable Wiring

Input/output pinProgrammed interconnection

InterconnectPoint

Horizontaltracks

Vertical tracks

Cell

M


Mesh-based Interconnect NetworkMesh-based Interconnect NetworkSwitch Box

Connect Box

InterconnectPoint

Courtesy Dehon and Wawrzyniek


Transistor Implementation of MeshTransistor Implementation of Mesh



Hierarchical Mesh NetworkHierarchical Mesh Network

Use overlayed meshto support longer connections

Reduced fanout and reduced resistance



Altera MAXAltera MAX

From Smith97


Altera MAX Interconnect ArchitectureAltera MAX Interconnect Architecture

LAB2

PIA

LAB1

LAB6

tPIA

tPIA

row channelcolumn channel

LAB

Courtesy Altera

Array-based(MAX 3000-7000)

Mesh-based(MAX 9000)


Xilinx 4000 Interconnect ArchitectureXilinx 4000 Interconnect Architecture

2

12

8

4

3

2

3

CLB

8 4 8 4

Quad

Single

Double

Long

DirectConnect

DirectConnect

Quad Long GlobalClock

Long Double Single GlobalClock

CarryChain

Long

12 4 4

Courtesy Xilinx


RAM-based FPGA RAM-based FPGA

Xilinx XC4000ex

Courtesy Xilinx


About FPGA About FPGA

Xilinx XC4000ex

Courtesy Xilinx

To make array-based approach successful, advanced software support in terms of cell placement, signal routing and synthesis is required.

Programmable logic is at least 10 times less efficient in terms of energy and performance with respect to ASIC (Application Specific Integrated Circuit) and custom designs.


Design at a crossroad Design at a crossroad System-on-a-Chip System-on-a-Chip

RAM

500 k Gates FPGA+ 1 Gbit DRAMPreprocessing

Multi-

SpectralImager

Csystem+2 GbitDRAMRecog-

nition

Ana

log

64 SIMD ProcessorArray + SRAM

Image Conditioning100 GOPS

Embedded applications where cost, performance, and energy are the real issues!

DSP and control intensive Mixed-mode Combines programmable

and application-specific modules

Tools plays crucial role

Hybrid implementation seems to be the future!


Heterogeneous Programmable PlatformsHeterogeneous Programmable Platforms

Xilinx Vertex-II Pro

Courtesy Xilinx

High-speed I/O

Embedded PowerPcEmbedded memories

Hardwired multipliers

FPGA Fabric


Addressing the Design Complexity IssueAddressing the Design Complexity IssueArchitecture ReuseArchitecture Reuse

Reuse comes in generationsGeneration Reuse element Status

1st Standard cells Well established

2nd IP blocks Being introduced

3rd Architecture Emerging

4th IC Early research

Source: Theo Claasen (Philips) – DAC 00


Architecture ReUseArchitecture ReUse Silicon System Platform

Flexible architecture for hardware and software Specific (programmable) components Network architecture Software modules Rules and guidelines for design of HW and SW

Has been successful in PC’s Dominance of a few players who specify and control architecture

Application-domain specific (difference in constraints) Speed (compute power) Dissipation Costs Real / non-real time data


Platform-Based DesignPlatform-Based Design

A platform is a restriction on the space of possible implementation choices, providing a well-defined abstraction of the underlying technology for the application developer

New platforms will be defined at the architecture-micro-architecture boundary

They will be component-based, and will provide a range of choices from structured-custom to fully programmable implementations

Key to such approaches is the representation of communication (interconnect) in the platform model

““Only the consumer gets freedom of choice;Only the consumer gets freedom of choice;designers need freedomdesigners need freedom fromfrom choice”choice”

(Orfali, et al, 1996, p.522)(Orfali, et al, 1996, p.522)

Source: R. Newton


SummarySummary

Digital CMOS Design is kicking and healthy

Who can afford design in the years to come? Some major design methodology change in the making!

© digital integrated circuits 2nd design methodologies sequential logic 2 storage mechanisms...

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