1

STRAIN INDUCED EFFECTS ON LATERAL POWER MOSFETS

By

JINGJING MICHELLE LIU

A THESIS PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT

OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF SCIENCE

UNIVERSITY OF FLORIDA

2009

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© 2009 Jingjing Michelle Liu

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To Grandma 王莲云

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ACKNOWLEDGMENTS

I thank Dr. Thompson greatly for giving me fantastic research opportunities to expand my

knowledge and experience and for offering incredible support in a published paper and this

thesis. I thank Drs. Nishida and Eisenstadt for giving me valuable academic advising and being

in my committee. I want to give special thanks to my colleague Uma for teaching and helping

out on my research project from the beginning to the end. I also want to thank Andy and Sri for

all the great suggestions on my thesis presentation and writing. I thank all my lab mates for the

greatest support in research and lab life. The names are listed alphabetically with equal

importance: Amit, Andy, Hyunwoo, Mehmet, Min, Nichole, Ukjin, Uma, Sri, Xiaodong, Yongke

and Younsung.

During the process of writing this thesis, Jeffrey and Yige have given me enormous help

outside the academic field. I also appreciate all the help and caring inquiries my parents and

grandma gave me during this time. I want to give my most thank and deepest love to my

grandma who brought me up but passed away when my paper was being published. I feel the

deepest shame for not seeing her one last time or attending her funeral in China because of my

research timeline. I sincerely thank my family and all my friends for all the emotional

assistance.

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TABLE OF CONTENTS page

ACKNOWLEDGMENTS.................................................................................................................... 4

LIST OF TABLES................................................................................................................................ 7

LIST OF FIGURES .............................................................................................................................. 8

ABSTRACT ........................................................................................................................................ 10

CHAPTER

1 INTRODUCTION....................................................................................................................... 12

Motivation.................................................................................................................................... 12 Power Si MOSFETs .................................................................................................................... 13 Strained Silicon MOSFETs ........................................................................................................ 14 Summary ...................................................................................................................................... 17

2 WAFER BENDING EXPERIMENTS ...................................................................................... 23

Experimental Setup ..................................................................................................................... 23 Strain and Stress .......................................................................................................................... 24 Linear Drain Current Measurements.......................................................................................... 25 Breakdown Voltage Measurements ........................................................................................... 26 Summary ...................................................................................................................................... 26

3 EFFECTS ON STRAINED N-TYPE LATERALLY DIFFUSED MOSFET ........................ 32

Experimental Results .................................................................................................................. 34 On-Resistance Reduction............................................................................................................ 36 Piezoresistance Coefficient Modeling ....................................................................................... 39 Breakdown Voltage ..................................................................................................................... 40 N-LDMOS Results Summary..................................................................................................... 41

4 EFFECTS ON STRAINED P-TYPE DRAIN EXTENDED MOSFET .................................. 50

Experimental Results .................................................................................................................. 51 On-Resistance Reduction............................................................................................................ 53 Piezoresistance Coefficient Modeling ....................................................................................... 55 Breakdown Voltage ..................................................................................................................... 55 P-DEMOS Results Summary ..................................................................................................... 55

5 SUMMARY................................................................................................................................. 64

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LIST OF REFERENCES ................................................................................................................... 67

BIOGRAPHICAL SKETCH ............................................................................................................. 70

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LIST OF TABLES

Table page 3-1 On-resistance reduction per 100 MPa of stress for n-LDMOS and n-MOSFET at low

gate voltage. Both types of devices have surfaces along (100) direction. ......................... 45

3-2 On-resistance reduction per 100 MPa of stress for n-LDMOS and n-MOSFET at high gate voltage. Both types of devices have surfaces along (100) direction. ................ 46

4-1 On-resistance reduction per 100 MPa of stress for p-DEMOS and p-MOSFET at both low and high gate voltage. Both types of devices have surfaces along (100) direction. ................................................................................................................................. 60

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LIST OF FIGURES

Figure page 1-1 Cross sections of two vertical and one lateral power MOSFETs ........................................ 19

1-2 Cross sections of n-type Laterally Diffused MOSFET (N-LDMOS) structures with LOCOS isolation and Shallow Trench Isolation (STI). ....................................................... 20

1-3 Cross sections of p-type Drain Extended power MOSFET (P-DEMOS) structures with LOCOS isolation and Shallow Trench Isolation (STI). .............................................. 21

1-4 The E-k diagram for unstrained and strained silicon ........................................................... 22

2-1 Experimental setup and the four-point wafer bending apparatus. ....................................... 28

2-2 A close look at the wafer bending apparatus and top-down view of an N-LDMOS under the microscope with probe tips landed on the four terminals. .................................. 29

2-3 Four-point wafer bending apparatus ..................................................................................... 30

2-4 Longitudinal and transverse stress, and tensile and compressive stress ............................. 31

3-1 Cross-sections of n-MOSFET and n-LDMOS ..................................................................... 42

3-2 On-resistance distribution of n-LDMOS at low gate voltage and high gate voltage ......... 43

3-3 Linear drain current enhancement versus stress for <110> and <100> channel N-LDMOS at low gate overdrive and high gate overdrive ...................................................... 44

3-4 Comparison of on-resistance reduction per 100 MPa of stress for n-LDMOS and n-MOSFET at low gate voltage. . ............................................................................................ 45

3-5 Comparison of on-resistance reduction per 100 MPa of stress for n-LDMOS and n-MOSFET at high gate voltage ............................................................................................... 46

3-6 The polar plot for π-coefficients of <100> channel and <110> channel n-LDMOS devices on [001] substrate under longitudinal stress. .......................................................... 47

3-7 The polar plot for π-coefficients of <100> channel and <110> channel n-LDMOS devices on [001] substrate under transverse stress. .............................................................. 48

3-8 Breakdown voltage shift due to stress is insignificant for n-LDMOS ................................ 49

4-1 Cross-section of a p-MOSFET and p-DEMOS .................................................................... 57

4-2 On-resistance distribution of p-DEMOS at low gate voltage and high gate voltage ......... 58

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4-3 Linear drain current enhancement versus stress for <110> and <100> channel DEPMOS at low gate overdrive and high gate overdrive ................................................... 59

4-4 Comparison of on-resistance reduction per 100 MPa of stress for p-DEMOS and p-MOSFET at both low and high gate voltages ...................................................................... 60

4-5 The polar plot for π-coefficients of <100> channel and <110> channel p-DEMOS devices on [001] substrate under longitudinal stress. .......................................................... 61

4-6 The polar plot for π-coefficients of <100> channel and <110> channel p-DEMOS devices on [001] substrate under transverse stress. .............................................................. 62

4-7 Breakdown voltage shift due to stress is insignificant for p-DEMOS ................................ 63

5-1 Linear drain current enhancements under high stress. ......................................................... 66

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Abstract of Thesis Presented to the Graduate School of the University of Florida in Partial Fulfillment of the

Requirements for the Degree of Master of Science

STRAIN INDUCED EFFECTS ON LATERAL POWER MOSFETS

By

Jingjing Michelle Liu

December 2009 Chair: Scott E Thompson Cochair: Toshi Nishida Major: Electrical and Computer Engineering

Power MOSFETs are designed for maximum breakdown voltage with minimum on-

resistance. A longer channel or thicker drift region is needed to obtain a higher breakdown

voltage; however, this will degrade the on-resistance. On-resistance and breakdown voltage

trade-off limits performance, therefore a better method is needed to improve power MOSFETs.

Strain in logic MOSFETs has been widely adopted in commercial manufacturing to

achieve better performance and extend scaling. Due to structural similarities between lateral

power MOSFETs and lateral logic MOSFETs, strain has potential to provide performance

enhancements in power MOSFETs. In this work, effects of uniaxial stress on lateral diffused

power MOSFETs are measured and analyzed for the first time. The most beneficial channel

direction and stress type has also been investigated through experiments.

Similar enhancements are observed in strained lateral power MOSFETs. With

advantageous strain, on-resistance improvements are observed in experiments for power

MOSFETs. In n-type power MOSFETs, a maximum enhancement of 2.0% per 100 MPa

uniaxial stress is determined experimentally. This is compared to a maximum of 5.1% in p-type

power MOSFETs. No significant breakdown voltage shift is observed due to stress.

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Experiments demonstrate that strain breaks the on-resistance/breakdown voltage tradeoff by

enhancing on-resistance while maintaining breakdown voltage.

There are differences between logic MOSFETs and power MOSFETs. Experimental

results for n-type power MOSFETs show reduced enhancement with stress. This is explained by

effect of vertical spreading of carriers into the substrate. On-resistance distribution has therefore

been studied and piezoresistance coefficients are modeled to validate experimental results.

In summary, this work proves strain to be beneficial in improving lateral power MOSFETs

performance and provides the most favorable channel direction and stress type for the first time.

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CHAPTER 1 INTRODUCTION

As the scaling trend of silicon device goes into nano-scale, strain has been widely accepted

to be an effective method to further continue the famous Moore’s law. Yet while much research

has been targeted at strained silicon logic MOSFETs, there was little study on how strain affects

the Si power MOSFET. In this work, the performance improvement induced by in-plane

uniaxial stress on lateral Si power MOSFET is explored, and for the first time, the most

beneficial channel direction and stress type is experimentally revealed.

In the first chapter, the strained silicon MOSFET theory is introduced then followed by the

topic of Si power MOSFET. In Chapter 2, a wafer bending experiment is introduced and an

explanation of how to appropriately measure the strain effects on power MOSFET is given.

Chapters 3 and 4 discuss the experimental results of n- and p-type lateral power MOSFETs,

respectively. A summary is provided at the end to summarize the highlights in this work.

Motivation

Unlike silicon logic MOSFETs, integrated power devices such as power MOSFETs need

special design to handle large on-state currents and voltages. For this purpose, much attention in

designing power MOSFETs has been focused on minimizing on-resistance while maximizing the

breakdown voltage.[1]

In 1974, vertical structures such as V-groove MOS (VMOS)[2] and UMOS(Figure 1-1)

were demonstrated to provide low on-resistance and high blocking voltage and most power

switching MOSFETs have been fabricated in vertical structures since then. In the late 1970s,

lateral structure power MOSFET using Reduced Surface Field (RESURF) technology was

proposed to avoid the thicker and lower doped epitaxial layer in vertical devices.[3] Field

plating is another technique that has been used to raise the breakdown voltage by applying a field

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plate near the gate edge.[4] A new category of power MOSFET, the Super-Junction MOSFET

adopting highly doped n-column structures has been commercialized later on, achieved an on-

resistance below the Si-limit and provided high blocking voltage.[5]

Strain technique for power Si MOSFETs has just emerged to be a research interest. It is

predicted that strain will lower on-resistance by improving electron and hole mobility in power

devices since similar effects have been observed in strained silicon logic MOSFETs with similar

structures. Experimental results on mobility enhancement induced by strain have been reported

to be as high as 4.7% for n-MOSFET and 7.1% for p-MOSFET per 100 MPa.[6] Strained Si

technology is proven to be so beneficial that it is being employed in almost all 90nm, 65nm, and

45nm technology nodes.[7] Inspired by this, strained power MOSFET and its effects on the

performance are studied. In the next sections, power Si MOSFET is briefly introduced and

followed by a general idea about strain technology on silicon logic MOSFET.

Power Si MOSFETs

In this work, the two types of power MOSFETs are both of lateral structures: the Lateral

Diffused MOSFET (LDMOS) structure for n-type devices (Figure 1-2) and Drain Extended

MOSFET (DEMOS) structure for p-type devices (Figure 1-3).

One lateral diffused power MOSFET (LDMOS) structure is shown in Figure 1-1 c). Note

that in Figure 1-1 c), the isolation structure is not shown. The LDMOS sometimes use Local

Oxidation of Silicon (LOCOS) isolation or Shallow Trench Isolation (STI) between the gate and

drain region to stand high voltages, shown in Figure 1-2. The isolation structure is essential in

power MOSFET because it prevents leakage current between neighboring source and drain

terminals. However, this structure prevents the current from flowing horizontally. The dominant

on-resistance changes accordingly and therefore needs to be re-modeled and treated differently

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from the traditional lateral devices because of the altered current path. Details about on-

resistance modeling in N-LDMOS with STI are discussed in Chapter 3.

A modified structure of a lateral diffused power MOSFET is the Drain Extended MOSFET

(DEMOS). The biggest advantage of this structure is that it brought low on-resistance and good

breakdown voltage to both n-type and p-type with no extra process steps or cost, making

advanced complementary MOSFET circuits better and cheaper.[8] As shown in Figure 1-3, a

shallow p-well is extended from the heavily doped drain side and a n-well is deeply engineered

beneath the regular p-well to enable the use of p-substrate for the CMOS designs.

The structures of both n-type and p-type silicon MOSFET and power Si MOSFET are

shown in Figure 1-4 and 1-5 for comparison. In both logic and power MOSFET, current flows

from source to drain laterally, under the vertical electric filed confinement controlled by gate

voltage. Within similar physical dimensions, strain should exhibit similar physics effects, such

as similar band splitting or warping. One difference in n-type structures is that the dielectric

isolation STI between under the gate and drain area detours the current to flow around it, thus

brings in an angle for the lateral current path. This affects the on-resistance distribution and a

solution for π-coefficient modeling will be given in Chapter 3.

In order to better understand how strain will affect power Si MOSFET, an introduction of

strained silicon MOSFET technology is provided below.

Strained Silicon MOSFETs

Strained silicon technology has been studied since around 1950s. Bardeen & Shockley

first developed the deformation potential theory in 1950, out of which the band edge shift due to

strain is formulated.[9] In 1956, Herring & Vogt developed the energy shift theory to explain the

conduction band inter-valley scattering rate.[10] Because of valence band warping under strain,

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energy band shift alone cannot explain the hole transport properties. In 1962, the pk ⋅ method

was used to calculate the valence band effective mass in strained silicon.[11] Band warping

under uniaxial stress was soon discovered and thus hole mobility in semiconductors was

understood.[12]

Strain on semiconductor device can be internally inducted by fabrication process or

externally applied mechanically. Advantageous strain decreases crystal symmetry, which caused

band splitting and band warping. Two phenomena observed in the presence of strain are

believed to explain mobility enhancement [13-14]:

For conduction band, the average effective mass reduction and inter-valley scattering rate

suppression are the reasons. For valence band, the average effective mass reduction caused by

band warping is the dominant mechanism.

The effective mass of electrons within a crystal, being a function of the semiconductor

material and all kinds of scattering mechanisms, is different from the mass of electrons within a

vacuum. The effective mass is anisotropic because it is calculated by the curvature reciprocal of

the electron energy in that direction and energy surface in each direction is shaped as an

ellipsoid. At room temperature, the conduction band valley minima in silicon are along Δ

direction. In the momentum space, these valley minima are denoted in six different but

equivalent directions: 001, 010, 100, 00-1, 0-10, and -100. Because of the symmetry of silicon,

these six valleys are degenerate and of equal energy. They are represented by 6 identical

ellipsoids along x, y, and z directions in Figure 1-1 a). For unstrained silicon, the effective mass

is given by:

1)]42(61[* −+=

tl mmm (1-1)

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In this equation, transverse mass tm is the mass that perpendicular to the axis direction and

longitudinal mass lm is the mass that in the axis direction. It is commonly accepted that tm

=0.19 0m and lm =0.98 0m with 0m the free electron mass.

If we select a plane defined by axis kx and ky, the four in-plane valleys (ellipsoids) will be

called Δ4, and the rest two valleys which are out-of-plane will be called Δ2. Here we distinguish

the in-plane valleys from the out-of-plan valleys because in silicon MOSFET, strain eliminates

the degeneracy between the Δ4 and Δ2 valleys, shown in Figure 1-1 b). The 6 bands or valleys

that were previously equal in energy are then split into lower energy Δ2 bands and higher energy

Δ4 bands because Δ2 valleys are more populated with electrons. This means there are now more

electrons with transverse in-plane mass of tm =0.19 0m and longitudinal in-plane mass of lm

=0.98 0m . Thus the total in-plane effective mass is reduced, resulting in a mobility increase.

Scattering is another factor that affects electron mobility. It is complicated to model the

exact scattering to quantify mobility changes but simplified considerations on scattering rate and

simulations have suggested that reduced scattering due to stress enhances the mobility.

A useful parameter to estimate semiconductor device performance under strain is the

piezoresistance coefficient.[6] The piezoresistance coefficient (π-coefficient) provides a way to

experimentally measure and quantify carrier mobility enhanced by strain. Smith was the first to

measure the π-coefficients for bulk silicon and germanium in 1953.[15] His data was widely

recognized to explain the bulk properties under strain. However, π-coefficients in silicon

MOSFET have a big difference due to surface confinement. In 1968, the first π-coefficients

were measured in p-type inversion layer.[16] Later on, both n- and p-type MOSFET π-

coefficients were reported based on measured current enhancement with strain.[17-20]

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In strained Si MOSFETs, π-coefficient is defined as the resistance change due to stress.

This is expressed in the following equation:

00

0 11RR

RRRx ∆

=−

=σσ

π (1-2)

where 0R and xR are the unstressed and stressed resistance, respectively, and R∆ is the

resistance change under the stress σ . Knowing that resistivity ρ is proportional to R, we can

rewrite the above equation using normalized change in resistivity ∆ρ/ρ:

0

1ρρ

σπ ∆= (1-3)

with resistivity given by )/(1 pqnq pn µµρ += . For a given device at room temperature, π-

coefficient is mainly determined by the electron and hole mobility because the carrier densities

(n and p) are more or less constant. Thus, π-coefficient provides a straightforward way to

portray carrier mobility enhancement using experiments.

More details of the experiments will be covered in Chapter 2 and evaluation of on-

resistance reduction in Chapter 3 and 4.

Summary

The goal for this research is to improve performance in lateral power MOSFETs. This can

be done by lowering on-resistance while maintaining a reasonable breakdown voltage. Past

research in strained silicon MOSFETs shows that strain is a very effective way in improving

mobility and boosting performance. From the known effects of strain in logic MOSFETs, we see

the potential for strain to improve power MOSFETs. Because of the similarities in power Si

MOSFET and silicon logic MOSFET, we were inspired to introduce strain into the power

MOSFET. There are differences in device structures between power MOSFETs and logic

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MOSFETs, which bring performance differences. On-resistance distribution will be taken into

account and π-coefficient will be modeled to explain the discrepancies. In general, strain has

been proven successful because of the decrease in on-resistance and stable breakdown voltage

observed in experiments.

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a)

b)

c)

Figure 1-1. Cross sections of two vertical and one lateral power MOSFETs. Vertical structures are a) VMOS and b) UMOS; lateral structure is c) lateral diffused MOSFET, or LDMOS

20

a)

b)

Figure 1-2. Cross sections of n-type Laterally Diffused MOSFET (N-LDMOS) structures with: a) LOCOS isolation, and b) Shallow Trench Isolation, or the STI.

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a)

b)

Figure 1-3. Cross sections of p-type Drain Extended power MOSFET (P-DEMOS) structures with: a) LOCOS isolation, and b) Shallow Trench Isolation, or the STI.

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Figure 1-4. The E-k diagram: the ellipsoids represent constant electron energy in the k-space for unstrained and strained silicon. Also shown are the degenerate six fold conduction band valleys in unstrained silicon and the split Δ2 and Δ4 valleys after advantageous strain applied on the silicon.

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CHAPTER 2 WAFER BENDING EXPERIMENTS

In this work, two kinds of experiments are performed. The main kind of experiment is the

linear drain current measurement under various gate voltages. The other is the drain current

versus drain voltage measurement, also known as breakdown voltage measurement. Both kinds

of experiments are operated under the mechanical stress of interest, normally ranging from 0 to a

maximum of 400 Mega Pascal (MPa) in this work.

Experimental Setup

The setup of the wafer bending experiments is shown in Figure 2-1(a). A three-way

adjustable microscope station is used to accurately locate devices of interest on wafer and the

Source-Measure Units (SMU) manipulators are used for fine adjustments over a small area.

Special probing tips are used to connect the device terminals, applying voltages and conducting

currents according to simulation setup. Currents and voltages are picked up and transported to

the Keithley 4200 Semiconductor Characteristics System where they are processed and stored.

The strain that we incorporated into our devices is mechanical uni-axial stress externally

applied through the four-point wafer bending jig shown in Figure 2-1 (b). The amount of stress

is measured by a micrometer designed on the bending apparatus and calibrated by experiments.

The procedures for the wafer bending experiments are as follows. Firstly, the wafer is

properly positioned in the four-point wafer bending jig so that the device of interest is shown in

the center of the opening on top of the jig. Secondly, use the micrometer screws to apply zero

stress on the wafer as a starting point. Thirdly, securely place the jig in the microscopic probing

station and locate the device through the microscope. Only after the above steps should one start

to land the probe tips. A top-down view of a typical n-LDMOS under microscope is provided in

Figure 2-2(b).

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Strain and Stress

Strain, in the case of a semiconductor, is a measure of lattice displacement. It is defined as

strain-induced normalized lattice change and therefore it is unit-less. Here “ε” is strain and “a”

is the lattice length:

aa∆

=ε (2-1)

In history, strain on metal was studied before it was found out that strain imposes a larger

effect and better improvement in a semiconductor. Strained effect in metal is mainly in the

change of physical dimensions, while that in semiconductor also alters carrier transportation

properties. Previous work[21] has shown that strain induced dimensional change in

semiconductor is negligible compared to the resistance change for the current doable strain

applied via four-point wafer bending jig. In other words, strain can enhance carrier mobility in

semiconductors such as silicon without significant affect on physical dimensions.

Stress has a unit of Pascal or Pa and is defined as

AF

A 0lim→

=σ (2-2)

There are two major types of stress that have been commonly used during the history of

strain research: uniaxial stress and biaxial stress. In the 1980s and 1990s, a leading focus of the

industry was biaxial stress.[22] Starting from the late 1990s and early 2000s, the focus has

shifted to uniaxial stress. Compared to biaxial stress, uniaxial stress brings better mobility

enhancements and affect threshold voltage less, and thus has become more used.[23] In this

work, the uniaxial stress is used to provide performance enhancement in the lateral power

MOSFETs.

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Uniaxial stress can be categorized as longitudinal or transverse according to the direction

in which stress is applied. Longitudinal uniaxial stress refers to stress along the channel

direction, while transverse perpendicular to the channel. Tensile stress is the stress that stretches

the channel away, while compressive stress pushes source and drain terminals into the center of

channel along surface direction. (See Figure 2-4)

Past experience has taught us that too much stress could cause damage to the devices or

even break the wafer. The maximum stress a piece of wafer sample can possibly stand depends

on the physical conditions of the wafer sample (shape, size, number of metal layers and

fabrication conditions, etc). It is a good idea to avoid making any permanent changes to the

material for consistent measurements.

Linear Drain Current Measurements

As mentioned in Chapter 1, π-coefficient is effective in estimating device performance

under strain because it provides a simple way to measure and quantify performance enhanced by

strain experiments. Performance of a power MOSFET is evaluated by its source to drain drive

current. Therefore, linear drain current measurements with stress are conducted in this work to

calculate π-coefficients and the on-resistance reductions. This relationship can be expressed in

Equation (2-1):

D

D

II

RR ∆

−=∆

=σσ

π 11

0

(2-1)

In the linear drain current measurements, we apply a constant DC bias of 0.1 V on the

drain node while sweeping the bias on the gate from 0 V to 7 V while source and substrate are

both grounded to eliminate body effect. This procedure ensures that the power MOSFET is

biased to operate in linear region all the time, as indicated in the name, thus the current is

supposed to be proportional to the drain to source voltage without strain.

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In this way, linear drain currents are measured and current enhancements are plotted with

the stress. On-resistance reductions due to stress are then the current enhancements due to stress

from Equation (2-1). Experimental data of linear drain current enhancement due to stress will be

plotted in Chapter 3 for n-LDMOS and Chapter 4 for p-DEMOS. On-resistance reduction per

100 MPa of stress will be shown in those chapters. The on-resistance is the most important

parameter, besides breakdown voltage, in specifying performance of a power MOSFET. If the

breakdown voltage doesn’t degrade much with the stress, a lower on-resistance will make a

power MOSFET perform better. Our goal in this work is to find the most on-resistance

reduction and the most beneficial stress and channel direction that reduces on-resistance the

most.

Breakdown Voltage Measurements

In the breakdown voltage measurements, we measure drain current with a sweeping drain

voltages of 0 to several volts larger than the rated breakdown voltage in order to obtain the

breakdown point. Gate voltage, however, is set to turn on the transistor.

Breakdown voltages are monitored at a reference drain current of 10nA before and after

applying stress. The goal of this measurement is to see if stress degrades the breakdown voltage.

Breakdown voltages are said to be degraded if they become much bigger due to stress.

Examples of breakdown voltage improvements can be lowered or unchanged breakdown

voltages under the presence of stress. It is safe to consider breakdown voltages as unchanged if

the breakdown voltage shifts are within 0.5% per stress of 100 MPa.

Summary

In this chapter, wafer bending experiments are introduced. The two types of experiments I

did in this work are linear drain current measurements and breakdown voltage measurements.

Both experiments are done under the gradually applied mechanical stress of 0 to around

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100MPa. Stress is applied externally into the device via four-point wafer bending apparatus.

Longitudinal stress is along the channel direction while transverse stress is perpendicular to the

channel direction. Tensile stress is stress that stretches the source and drain away from the gate

on the surface, while compressive stress presses the source and drain to the gate on the surface.

Linear drain current enhancements due to stress are calculated to reflect on-resistance reductions.

Breakdown voltage measurements are conducted to see how stress affects breakdown voltages.

28

(a)

(b)

Figure 2-1. (a) Experimental setup. The main parts are wafer bending apparatus, a 3-way adjustable platform, SMU manipulators and a microscope. (b) The four-point wafer bending apparatus.

29

(a)

(b)

Figure 2-2. (a) A close look at the wafer bending apparatus when the probes are landed. (b) Top-down view of an N-LDMOS under the microscope with probe tips landed on the four terminals.

30

(a)

E = Young’s modulus t = sample thickness y = vertical displacement a, L = rod spacing

(b) Figure 2-3. Four-point wafer bending apparatus. Stress shown is conventionally called

compressive stress: compressive stress is applied on the top surface of the wafer sample and tensile stress on the bottom surface. (a) A piece of wafer sample in between the upper and lower sets of rods, bending upwards[24]. (b) A graphical explanation of picture (a), showing the dimensions and forces. An equation for stress calculation is provided.

−

⋅⋅= =

32

22 aLa

ytE axσ

31

(a)

(b)

Figure 2-4. An N-LDMOS labeled (a) longitudinal and transverse stress, and (b) tensile and compressive stress. Longitudinal stress is along the direction of channel (current flow), whereas transverse stress is perpendicular to the channel. Tensile stress is the stress that stretches the channel away, while compressive stress pushes source and drain terminals into the center of channel along surface direction.

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CHAPTER 3 EFFECTS ON STRAINED N-TYPE LATERALLY DIFFUSED MOSFET

The Laterally Diffused MOSFET (LDMOS) is a widely used lateral design for power

MOSFET. The LDMOS structure provides low on-resistance and high blocking voltage features

because a p-well under the Source and Gate is diffused in a low-doped n-type drain region for n-

type devices. Under practical relevant condition, a large depletion layer is formed inside the

laterally diffused p-well under the Source and Gate due to the low-doping concentration of

electrons in the n-type drain region. This depletion layer blocks high voltage between source and

drain, giving the MOSFET a large breakdown voltage. A low on-resistance is observed because

of a high current handling capability in the short channel made possible by defining the channel

region diffusion with the same mask as the source region.[25]

Device structures for logic n-MOSFET and n-LDMOS are shown in Figure 3-1. The n-

type LDMOS has a similar structure as the lateral logic n-MOSFET. The source, drain and gate

terminals are on top of the device and substrate on the bottom. Currents flow vertically from

source to drain, under the control of gate voltage. In the channel region, the main difference

between an n-LDMOS and an n-MOSFET is that there is shallow trench isolation (STI) between

under the gate region and the drain in the n-LDMOS, as shown in Figure 3-2 with a big circle.

Shallow trench isolation technology (STI) was pioneered as the device feature size scaled

down to 0.25µm to replace the older isolation technology of LOCOS.[26-27] STI then has

become the mainstream isolation technology because it can accommodate better isolation,

smaller channel-width, and smaller parasitic capacitance.[28] The critical advantage in

performance brought by STI is that the trench structures provide very good isolation between the

source and the drain thus can minimize drain to source leakage at higher voltage. For this

reason, STI technology is suitable for applications in power MOSFETs.

33

However, this structure prevents the current to flow vertically between the gate and drain.

In reality, current goes around the STI, forming a path into the bulk region with an angle to the

surface. At the bottom of the STI, current keeps going laterally towards the drain. This affects

the on-resistance because the current path is no longer confined to the surface. The on-resistance

therefore, can be divided into channel region resistance and bulk region resistance according to

whether the current is confined by the gate.

On-resistance of an n-LDMOS is estimated based on the on-resistance model for the

LDMOS devices. The on-resistance of an LDMOS device consists of active channel resistance

(RCH) in series with surface accumulation region resistance (RACC) and bulk resistance, also

known as drift resistance RD.[29] However, on-resistance will be discussed for low and high

gate voltage separately because the distributions are different under the two conditions.

At low gate voltage, the device is in weak inversion mode. Channel has just formed

between source and drain and is in low conductivity. The channel resistance is considered the

dominant resistance at this gate voltage. Here in Figure 3-2(a), we assume RCH as 100% in on-

resistance distribution. This is similar with logic n-MOSFET because on-resistance for logic n-

MOSFETs is mainly channel resistance. So it is expected that n-LDMOS at low gate bias will

act like n-MOSFET.

At rated high gate voltage, carriers conduct freely through the channel between source and

drain, indicating a low resistance in the channel. Accumulation layer exists at high gate voltage.

The bulk region resistances become substantial in this situation. According to device simulation

at high gate voltage, on-resistance is now comprised with the following percentages in four

components: 25% of channel resistance, 19% of accumulation resistance, and 56% of spreading

resistance and drift resistance in total. Because spreading resistance and drift resistance are not

34

under surface confinement, they are considered bulk resistance. Here at high gate voltage, on-

resistance of n-LDMOS is dominant by bulk region resistance since bulk region resistance

consists 56%. So it is expected that n-LDMOS at low gate bias will conduct more like n-type

bulk silicon.

Experimental Results

The linear drain current enhancements in Figure 3-3 are plotted according to experimental

drain currents versus stress along channels <110> and <100> under low and high gate overdrive,

respectively. Blue lines in Figure 3-3 show current enhancement data for <100> channel devices

while red lines are for <110> channel devices. For both channel devices, longitudinal and

transverse uniaxial stresses are applied. Longitudinal and transverse uniaxial stresses are

indicated with x’s or circles in the Figure. In this work, low gate overdrive is defined as a gate-

to-drain voltage of 0.3V above the corresponding threshold voltage of the power MOSFET

measured. This is described in the upper-left corner of Figure 3-3 (a) as “VGS-Vt=0.3V”. The

high gate overdrive is a rated gate to substrate voltage several voltages above the threshold

voltage, shown as “VGS= rated voltage” in Figure 3-3 (b).

From Figure 3-3, current enhances with uniaxial tensile stresses for both <100> and <110>

channel devices. The percentage of current enhancement increases linearly with tensile stresses.

Current enhancements due to the same amount of stress are lower under high gate overdrive than

low gate overdrive for N-LDMOS. Devices with <100> channel show the biggest linear current

enhancement at both low gate and high gate bias.

At low gate voltage, <100> channel devices bring the biggest current enhancement of 3.6%

per 100 MPa longitudinal tensile stress. <110> devices show enhancement of 2.5% per 100 MPa

longitudinal tensile stress. Transverse stresses are not as beneficial in this case because they

bring 1.9% and 1.5% enhancement in <110> and <100> channel devices, respectively. As

35

discussed in Chapter 2, π-coefficient is related to current enhancement due to stress. This can be

seen from the following equation derived from Equation (2-1):

D

D

II∆

−=σ

π 1 (3-1)

From Equation (3-1), π-coefficients at low gate overdrive for n-LDMOS can be calculated

from current enhancement mentioned above. For <110> channel devices, π-coefficients are -25

for longitudinal tensile stress and -19 for transverse tensile stress. For <100> channel devices, π-

coefficients are -36 for longitudinal tensile stress and -15 for transverse tensile stress. Previous

work in n-MOSFET shows π-coefficients of -32 and -15 for <110> channel devices with

longitudinal tensile stress and of -47 and -22 for <100> channel devices with transverse tensile

stress[6]. Comparison of n-LDMOS and n-MOSFET at low gate bias is given in Figure 3-4.

At high gate voltage, the biggest current enhancement is observed to be +2.0% in <100>

channel devices under 100 MPa longitudinal tensile stresses. <110> devices show enhancement

of 0.9% per 100 MPa longitudinal tensile stress. Transverse stresses are not as beneficial in this

case because they bring 0.6% and -0.9% enhancement in <110> and <100> channel devices,

respectively. π-coefficients at high gate overdrive for n-LDMOS can be calculated from current

enhancement mentioned above. For <110> channel devices, π-coefficients are -9 for

longitudinal tensile stress and -6 for transverse tensile stress. For <100> channel devices, π-

coefficients are -20 for longitudinal tensile stress and 9 for transverse tensile stress. Previous

work in n-type bulk silicon shows π-coefficients of -32 and -15 for <110> channel devices with

longitudinal tensile stress and of -82 and 35 for <100> channel devices with transverse tensile

stress.[15] Comparison of n-LDMOS and n-bulk silicon at high gate bias is given in Figure 3-5.

36

Note that for n-LDMOS, tensile stress in general enhances drain current. Longitudinal

stresses give the biggest current enhancement at both gate voltages. In other words, longitudinal

tensile stress is the advantageous stress for n-LDMOS.

On-Resistance Reduction

On-resistance and breakdown voltage are the two main parameters to characterize a power

MOSFET. In case of strained power MOSFETs, we are interested in how much performance

will be improved per unit advantageous stress. Performance improvements are quantified by on-

resistance reduction and breakdown voltage shift per unit advantageous stress. In this section,

on-resistance reduction will be calculated from π-coefficients measured from the linear drain

current experiments.

Reviewing the relation between on-resistance change due to stress and π-coefficient

discussed in Chapter 2, π-coefficient is simply the normalized on-resistance change divided by

stress, as seen in this equation:

0

1RR∆

=σ

π (3-2)

The numeric values of π-coefficients for <100> and <110> channel devices are discussed

in the previous section of “Experimental Results”. With advantageous stress, most π-coefficients

contain negative signs and advantageous stress for n-LDMOS, i.e. the uniaxial tensile stress, is

defined with a positive sign. From Equation (3-2), resistance change will be calculated to be

negative with a corresponding negative π-coefficient. This meets our expectations that on-

resistance will mainly be reduced with advantageous stress. On-resistance reduction will be

calculated below at low gate voltage and high gate voltage separately.

37

At low gate overdrive, π-coefficients are -25 for longitudinal stress and -19 for transverse

stress of <110> channel devices. For <100> channel devices, π-coefficients are -36 for

longitudinal tensile stress and -15 for transverse tensile stress. On-resistance reductions of

<110> channel devices will then be calculated to be 2.5% per 100 MPa longitudinal stress and

1.9% per 100 MPa transverse stress. On-resistance of <100> channel devices will reduce 3.6%

and 1.5% per 100 MPa longitudinal and transverse tensile stress, respectively. On-resistance

reductions calculated from previous work in n-MOSFET are 3.2% and 1.5% for <110> channel

devices with longitudinal tensile stress and 4.7% and 2.2% for <100> channel devices with

transverse tensile stress.

Comparison of on-resistance reduction in n-LDMOS and n-MOSFET at low gate bias is

given in Figure 3-4. For <110> and <100> channel n-LDMOS, similar trend for reduction of on-

resistance can be seen with the corresponding n-MOSFET under both longitudinal and transverse

stress. It can also be concluded that the percentages of on-resistance reduced are also similar for

two kinds of devices. This result agrees very well with our expectation drawn from the on-

resistance distribution for n-LDMOS at low gate bias.

At high gate voltage, π-coefficients are -9 for longitudinal stress and -6 for transverse

stress of <110> channel devices. For <100> channel devices, π-coefficients are -20 for

longitudinal tensile stress and 9 for transverse tensile stress. On-resistance reductions of <110>

channel devices will then be calculated to be 0.9% per 100 MPa longitudinal stress and 0.6% per

100 MPa transverse stress. On-resistance of <100> channel devices will reduce 2.0% but increse

1.5% per 100 MPa longitudinal and transverse tensile stress, respectively. On-resistance

reductions calculated from previous work in n-MOSFET are 3.2% and 1.5% for <110> channel

38

devices with longitudinal tension and 8.2% and -3.5% for <100> channel devices with transverse

tension.

In Figure 3-5, on-resistance reductions in n-LDMOS and n-bulk silicon at high gate bias

show big differences in value but the same trend under the same conditions of channel direction

and stress. Longitudinal unaxial stress improves on-resistance while transverse degrades devices

with <100> channel direction for both n-LDMOS and n-bulk silicon. This meets our expectation

that n-LDMOS operates like n-bulk silicon at high gate voltage drive. However, at high gate

voltage, n-LDMOS shows much less on-resistance reduction compared to n-bulk silicon. This is

due to unique resistance distribution in n-LDMOS. As discussed in the previous section, on-

resistance at high gate voltage is comprised with 25% of channel resistance, 19% of

accumulation resistance, and 56% of spreading resistance and drift resistance in total. Though

56% of resistance can be considered as “n-bulk like” resistance, there is still almost 50% of

surface resistance, or “n-MOSFET-like” resistance exists. So strictly speaking, n-LDMOS

should not follow the exact percentage changes in resistance as n-bulk silicon.

Because band structures are different in different directions inside silicon, electron

transportation properties vary with directions as well. Therefore, π-coefficients in bulk silicon

are dependent on current directions. While drift resistance RD is parallel to the device surface

due to the laterally-flown drift current, spreading resistance RSP presents an angle to the surface

for the reason that spreading current flows along the trench isolation into the deeper bulk region.

As a result, the need for calculating spreading π-coefficient and modeling the π-coefficient

distribution at high gate voltage are important to further understand and validate experimental

results.

39

Piezoresistance Coefficient Modeling

The piezoresistance coefficient of a laterally diffused power MOSFET is modeled based on

the on-resistance composition. For an n-LDMOS device, on-resistance has a unique distribution

of four components at rated high gate voltage. Therefore, π-coefficient should be sum of four

weighted π-coefficients for the four resistance components.

Simulations show that on-resistance at high gate voltage is comprised with 25% of channel

resistance, 19% of accumulation resistance, and 56% of spreading resistance and drift resistance

in total. Channel and accumulation resistances are in the thin layer of 2-dimensional surface area

under gate confinement. So π-coefficients for channel resistance and accumulation resistance

could be estimated by n-MOSFET π-coefficient (πMOSFET). The π-coefficient for drift resistance

can be expected to be the same value for n-bulk π-coefficient (πbulk) because drift resistance

comes from the current that flow parallel to the channel in the n-type bulk silicon. Spreading

resistance π-coefficient πSP, however, is more complicated because π-coefficient is a function of

current direction defined by the spreading angle. Assuming spreading resistance takes up a

distribution of x% of the total on-resistance, piezoresistance coefficient can be modeled to be:

π = 25%πMOSFET+ 19%πMOSFET+ (56-x)%πbulk+ x%πSP (3-3)

In order to accurately model piezoresistance coefficient from Equation (3-3), the unknown

parameter x and π-coefficient for spreading resistance need to be fitted. For materials with cubic

symmetry such as Si, the π-coefficient along any direction can be determined from the

piezoresistance tensor and direction cosines.[21, 30-31] The dependence of πSP on spread angle

for <110> n-channel device under longitudinal tensile stress is shown in Figure 3-6 (a). In this

plot, π-coefficients are negative with a spreading angle of less than 60 degrees while positive

from 60 to 90 degrees. From process simulation of the n-LDMOS we use in this work, spreading

40

angle at high gate voltage is known to be 80 degrees from surface direction. Reading from this

plot, the corresponding π-coefficient for spreading resistance is determined to be 34 of <100>

channel n-LDMOS devices on [001] substrate under longitudinal stress. Using this πSP=34 and

extrapolated π of -20 for <100> n-LDMOS with longitudinal tensile stress, parameter x is fitted

to be 21. So now we know spreading resistance makes 21% of the whole on-resistance and drift

resistance is calculated to be 35%.

Using the same technique in finding πSP for <100> with transverse tensile stress and <110>

with longitudinal and transverse tensile stress, Equation (3-3) gives -2, -26 and 10, respectively.

As discussed earlier, the π-coefficients extrapolated from experimental results are -6, -20 and 9,

which fit really well with π-coefficient calculated from modeling.

Also note from Figures 3-6 and 3-7 we can see that π-coefficients for spreading resistance

are all positive for spreading angle of 80. A simple rule of thumb, positive π-coefficients

increase resistance. While other components of on-resistance are improved (decreased) by

advantageous stress, spreading resistance is degraded (increased). This explains why we

observed a smaller enhancement in n-LDMOS than n-MOSFET with the same amount and types

of stress.

Breakdown Voltage

Breakdown voltage measurements show that breakdown voltage shifts due to stress is

small. According to Figure 3-8, there is a voltage shift of 0.08V with 60 MPa stress applied.

This extrapolates to a breakdown voltage shift of about 0.14V or 0.3% due to 100 MPa stress,

assuming a linearity between voltage shifts and stress. This shift is rather small compared to the

experimental uncertainty due to the nature of this kind of experiments. Oxide trapping charges

41

can well cause this amount of shift after being measured repeatedly. We can therefore conclude

that breakdown voltage does not vary significantly with stress.

N-LDMOS Results Summary

The structure of n-type lateral power MOSFET differs from that of n-MOSFET in that the

n-LDMOS employs a dielectric isolation of STI for higher drive current and voltage. The STI

between under the gate and drain area detours the current to flow around it, bringing in an angle

for the lateral current path. Therefore, it is important to understand the on-resistance

distributions of n-LDMOS. Piezoresistance coefficients are modeled accordingly for better

understanding of the experimental results. A positive π for the spreading resistance is found in

the modeling to account for less on-resistance reduction in n-LDMOS. This is verified in

calculation to match with measured data. Breakdown voltage shift is around 0.3% due to 100

MPa stress, which is rather small.

To sum up, the biggest reduction in on-resistance per 100 MPa stress is experimentally

measured to be 2.0%. This is achieved in n-LDMOS with <100> channel direction under

longitudinal tensile stress. Stress alters very little about breakdown voltages.

42

(a)

(b)

Figure 3-1. Cross-sections of (a)n-MOSFET and (b)n-LDMOS devices. Two types of devices share the similar lateral structures. The biggest difference in structure is the isolation structure called the “STI” in the n-LDMOS device. The STI introduces a spreading angle to the lateral current flow. This creates a big issue because this structure changes the on-resistance.

43

(a)

(b)

Figure 3-2. On-resistance distribution of n-LDMOS at (a) low gate voltage and (b) high gate voltage

44

(a)

(b)

Figure 3-3. Linear drain current enhancement versus stress for <110> and <100> channel N-LDMOS at (a) low gate overdrive and (b) rated gate overdrive

45

Table 3-1. On-resistance reduction per 100 MPa of stress for n-LDMOS and n-MOSFET at low gate voltage. Both types of devices have surfaces along (100) direction.

n-LDMOS longitudinal transverse

(100) <110> 2.5% 1.9%

(100) <100> 3.6% 1.5%

n-MOSFET longitudinal transverse

(100) <110> 3.2% 1.5%

(100) <100> 4.7% 2.2%

Figure 3-4. Comparison of on-resistance reduction per 100 MPa of stress for n-LDMOS and n-MOSFET at low gate voltage. The blue bars represent n-LDMOS and the orange bars represent n-MOSFET. On-resistance reductions are compared in these channel direction/stress type combinations: <100> transverse, <100> longitudinal, <110> transverse, and <110> longitudinal.

46

Table 3-2. On-resistance reduction per 100 MPa of stress for n-LDMOS and n-MOSFET at high gate voltage. Both types of devices have surfaces along (100) direction.

n-LDMOS longitudinal transverse

(100) <110> 0.9% 0.6%

(100) <100> 2.0% -0.9%

n-MOSFET longitudinal transverse

(100) <110> 3.2% 1.5%

(100) <100> 8.2% -3.5%

Figure 3-5. Comparison of on-resistance reduction per 100 MPa of stress for n-LDMOS and n-MOSFET at high gate voltage. The blue bars represent n-LDMOS and the green bars represent n-MOSFET. On-resistance reductions are compared in these channel direction/stress type combinations: <100> transverse, <100> longitudinal, <110> transverse, and <110> longitudinal.

47

(a)

(b)

Figure 3-6. The polar plot for π-coefficients of (a) <100> channel and (b) <110> channel n-LDMOS devices on [001] substrate under longitudinal stress.

48

(a)

(b)

Figure 3-7. The polar plot for π-coefficients of (a) <100> channel and (b) <110> channel n-LDMOS devices on [001] substrate under transverse stress.

49

Figure 3-8. Breakdown voltage shift due to stress is insignificant for n-LDMOS. There is 0.08V shift due to 60 MPa of stress in this Figure. This extrapolates to about 0.3% shift for 100 MPa of stress.

1E-10

1E-09

1E-08

1E-07

1E-06

36 36.4 36.8 37.2 37.6 38

1x10-6

1x10-7

1x10-8

1x10-9

1x10-10

∆VBD~80mV

VBD at ID=10nA

VD (V)

I D(A

)

0MPa

60MPa

50

CHAPTER 4 EFFECTS ON STRAINED P-TYPE DRAIN EXTENDED MOSFET

Drain-Extended MOSFET (DEMOS) is one type of LDMOS that employs a lightly doped

well to extend the area under the drain. This type of device has longer channel and thus allows

higher breakdown voltage. Previous work suggested that the thick depletion layer formed in the

lightly doped p-well at drain side absorbs about 70% of drain voltage drop at the drain extension

(lightly-doped p-well) under the gate region.[8] For this reasons, the thin gate oxide does not

experience a very high voltage drop even at a fairly high drain voltage. As a result, breakdown

voltages of up to 75V are made possible without the dielectric isolation structures inside channel

areas.

The p-type DEMOS structure is shown in Figure 4-1(b). Comparing to a p-type drain

extended logic MOSFET, shown in Figure 4-1(a), a p-DEMOS has a very similar structure

within the channel area except its channel is longer and an n-type back layer exists. Because of

the very similar device structures between the two, we will expect to see very similar behaviors

in both linear drain current enhancement and on-resistance reduction due to stress.

On-resistance of p-DEMOS is also estimated based on the on-resistance model for the

LDMOS devices mentioned in Chapter 3. The on-resistance of an LDMOS device consists of

active channel resistance (RCH) in series with surface accumulation region resistance (RACC) and

bulk resistance, also known as drift resistance RD.[29] However, here we use the drain-extended

p-type LDMOS, which employs an extended drain area instead of the STI to accommodate

higher voltage. On-resistance model for the p-DEMOS will only consists of channel resistance

in series with accumulation region resistance. Bulk resistance is excluded because current is

always confined at the surface with little spreading into the bulk region.

51

At low gate voltage, the device is in weak inversion mode. Channel has just formed

between source and drain and is in low conductivity. The channel resistance is considered the

only and thus dominant resistance at this gate voltage. Here in Figure 4-2(a), we assume RCH as

100% in on-resistance distribution. This is similar with logic p-MOSFET because on-resistance

for logic n-MOSFETs is mainly channel resistance. So it is expected that p-DEMOS at low gate

bias will act like p-MOSFET.

At rated high gate voltage, carriers conduct freely through the channel between source and

drain, indicating a low resistance in the channel. Accumulation layer barely exists at high gate

voltage. According to device simulation at high gate voltage, on-resistance is now comprised

with mostly channel resistance. This is again similar with logic p-MOSFET in that on-resistance

of logic p-MOSFETs is mainly channel resistance. So it is expected that p-DEMOS at high gate

bias will also act like p-MOSFET.

Experimental Results

The linear drain current enhancements in Figure 4-3 are plotted according to experimental

drain currents versus stress along channels <110> and <100> under low and high gate overdrive,

respectively. Blues lines in Figure 4-3 show current enhancement data for <100> channel

devices while red lines are for <110> channel devices. For both channel devices, longitudinal

and transverse uniaxial stresses are applied. Longitudinal and transverse uniaxial stresses are

indicated with arrows in the Figure. In this work, the low gate overdrive is defined as a gate-to-

drain voltage of 0.3V above the measured corresponding threshold voltage. This is described in

the upper-left corner of Figures (a) as “VGS-Vt=0.3V”. The high gate overdrive is a rated gate to

substrate voltage several volts above the threshold voltage (shown as “VGS= rated voltage” in

Figure (b)).

52

From Figure 4-3, current enhances with uniaxial compressive stresses for both <100> and

<110> channel devices. The percentage of current enhancement increases linearly with

compressive stresses. Current enhancements due to the same amount of stress are lower under

high gate overdrive than low gate overdrive for p-DEMOS. Devices with <110> channel show

the biggest linear current enhancement at both low gate and high gate bias.

At low gate voltage, <110> channel devices bring the biggest current enhancement of 5.2%

per 100 MPa longitudinal compressive stress. <100> devices show enhancement of 2.6% per

100 MPa longitudinal compressive stress. Longitudinal compressive for <100> are not as

beneficial in this case because it only bring 0.7% enhancement. Transverse compressive stress

degraded current of 3.2%for the <110> channel devices. π-coefficients at low gate overdrive for

p-DEMOS can be calculated from current enhancement mentioned above. For <110> channel

devices, π-coefficients are --52 for longitudinal compressive stress and 32 for transverse

compressive stress. For <100> channel devices, π-coefficients are -7 for longitudinal

compressive stress and -26 for transverse compressive stress. Previous work in p-MOSFET

shows π-coefficients of -71 and 32 for <110> channel devices with longitudinal compressive

stress and of 1 and -23.8 for <100> channel devices with transverse compressive stress[6].

At high gate voltage, the biggest current enhancement is observed to be +5.1% in <110>

channel devices under 100 MPa longitudinal compressive stresses. <110> devices show

enhancements of 1.1% and 1.9% per 100 MPa longitudinal and transverse compressive stress,

respectively. Transverse stresses are not as beneficial in this case because they degrade current

of 3.2% in <110> channel devices. π-coefficients at high gate overdrive for p-DEMOS can be

calculated from current enhancement mentioned above. For <110> channel devices, π-

coefficients are -51 for longitudinal compressive stress and 32 for transverse compressive stress.

53

For <100> channel devices, π-coefficients are -11 for longitudinal compressive stress and -19 for

transverse compressive stress. Comparison of p-DEMOS and p-MOSFET at low and high gate

bias is given in Figure 3-5.

Note that for p-DEMOS, compressive stress in general enhances drain current.

Longitudinal stresses give the biggest current enhancement at both gate voltages. In other words,

longitudinal compressive stress is the advantageous stress for p-DEMOS.

On-Resistance Reduction

As discussed in Chapter 3, on-resistance and breakdown voltage are the two main

parameters to characterize a power MOSFET. In this work, we quantify performance

improvement by calculating on-resistance reduction and breakdown voltage shift per unit

advantageous stress. On-resistance reduction will be calculated from π-coefficients measured

from the linear drain current experiments.

The numeric values of π-coefficients for <100> and <110> channel devices are discussed

in the previous section of “Experimental Results”. With advantageous stress, most π-coefficients

contain positive signs and advantageous stress for p-DEMOS, i.e. the uniaxial compressive

stress, is defined with a negative sign. From Equation (3-2), resistance change will be calculated

to be negative with a corresponding positive π-coefficient. This meets our expectations that on-

resistance will mainly be reduced with advantageous stress. On-resistance reduction will be

calculated below at low gate voltage and high gate voltage separately.

At low gate overdrive, π-coefficients are 52 for longitudinal stress and -32 for transverse

stress of <110> channel devices. For <100> channel devices, π-coefficients are 7 for

longitudinal compressive stress and 26 for transverse compressive stress. On-resistance of

<110> channel devices will then be calculated to be reduced 5.2% per 100 MPa longitudinal

54

stress and increased 3.2% per 100 MPa transverse stress. On-resistance of <100> channel

devices will reduce 0.7% and 2.6% per 100 MPa longitudinal and transverse compressive stress,

respectively.

At high gate voltage, π-coefficients are 51 for longitudinal compressive stress and -32 for

transverse compressive stress of <110> channel devices. For <100> channel devices, π-

coefficients are 11 for longitudinal compressive stress and 19 for transverse compressive stress.

On-resistance reductions of <110> channel devices will then be extrapolated to be 5.1% per 100

MPa longitudinal stress and -3.2% per 100 MPa transverse stress. On-resistance of <100>

channel devices will reduce 1.1% and 1.9% per 100 MPa longitudinal and transverse

compressive stress, respectively.

Comparison of on-resistance reduction for p-DEMOS at low and high gate bias is given in

Figure 4-4. The values for p-DEMOS at low and high gate voltages are almost identical to each

other. This is because in both cases channel resistance is the most dominant Figure. For p-

DEMOS of breakdown voltages less than 75V, long channels and extended drain are used to deal

with the high current and voltage. Channel resistance, therefore becomes very big, compared to

other resistance, due to the physical dimensions. For those with higher breakdown voltages, STI

is used for higher current and voltage. In these cases, on-resistance reduction needs to be

considered base on the distribution of its components. However, because the channel length is

so large that channel resistance dominates at all times, we only need to count channel resistance

reduction at high gate voltages. Therefore the on-resistance reductions are almost the same for

low gate and high gate.

On-resistance reductions calculated from previous work in p-MOSFET are 7.1% and -

3.2% for <110> channel devices with longitudinal compressive stress and -0.1% and 2.38% for

55

<100> channel devices with transverse compressive stress. These numbers are also close to

those for p-DEMOS as expected.

Piezoresistance Coefficient Modeling

The piezoresistance coefficient of p-DEMOS is sum of weighted π-coefficients for the

resistance components. For those p-DEMOS with STI structures, spreading resistance π-

coefficients πSP need to be considered. The πSP variation dependencies with spreading angles in

p-bulk silicon π-coefficients are shown in Figures 4-5 and 4-6. The values of spreading π-

coefficients at 80 degrees are read 0and 1 for <100> channel and <110> channel p-DEMOS

devices on [001] substrate under longitudinal stress, respectively. With transverse stress, same

values are also interpreted to be 0 and 1. Compared to π-coefficients of up to 51 in value,

changes in spreading resistance due to stress is negligible. This again explains why π-

coefficients are almost the same regardless of gate voltages.

Breakdown Voltage

Breakdown voltage measurements show that breakdown voltage shifts due to stress is

small. According to Figure 4-7, there is a voltage shift of 0.135V with 96 MPa stress applied.

This extrapolates to a breakdown voltage shift of about 0.5% due to 100 MPa stress, assuming

linearity between voltage shifts and stress. Experimental uncertainty that comes from oxide

charging can well cause this amount of shift after being measured repeatedly due to the nature of

this kind of experiments. We can therefore conclude that breakdown voltage due to stress is

insignificant.

P-DEMOS Results Summary

P-DEMOS employ extended drain and very large channel region in order to endure high

current and voltage, which makes the channel resistance to dominate the total on-resistance at all

56

times. Therefore the on-resistance reductions are almost the same for low gate and high gate due

to the same on-resistance distribution at all times. STI is used in p-DEMOS devices with

breakdown voltage greater than 75V to give extra margin for safe operations. However, values

of spreading π-coefficients at 80 degrees are almost 0, which means changes in spreading

resistance due to stress are negligible. On-resistance reductions calculated from previous work

in p-MOSFET are found close to the experimental results of p-DEMOS from this work.

Breakdown voltage shift is around 0.5% at 100 MPa, which is rather small.

To sum up, the biggest reduction in on-resistance per 100 MPa stress is experimentally

measured to be 5.1%. This is achieved in p-DEMOS with <110> channel direction under

longitudinal compressive stress. Breakdown voltage is concluded to be changed insignificantly

by stress.

57

(a)

(b)

Figure 4-1. Cross-section of a (a) p-MOSFET and (b) p-DEMOS device

58

(a)

(b)

Figure 4-2. On-resistance distribution of p-DEMOS at (a) low gate voltage and (b) high gate voltage

59

(a)

(b)

Figure 4-3. Linear drain current enhancement versus stress for <110> and <100> channel DEPMOS at (a) low gate overdrive and (b) high gate overdrive

60

Table 4-1. On-resistance reduction per 100 MPa of stress for p-DEMOS and p-MOSFET at both low and high gate voltage. Both types of devices have surfaces along (100) direction.

p-DEMOS longitudinal transverse

(100) <110> 5.2% | 5.1% -3.2% | -3.2%

(100) <100> 0.7% | 1.1% 2.6% | 1.9%

p-MOSFET longitudinal transverse

(100) <110> 7.1% -3.2%

(100) <100> -0.1% 2.38%

Figure 4-4. Comparison of on-resistance reduction per 100 MPa of stress for p-DEMOS at both low and high gate voltages and p-MOSFET. The blue bars represent p-DEMOS at low gate voltage, the orange bars represent p-DEMOS at high gate voltage, and the green bars represent p-MOSFET. On-resistance reductions are compared in these channel direction/stress type combinations: <100> transverse, <100> longitudinal, <110> transverse, and <110> longitudinal.

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(a)

(b) Figure 4-5. The polar plot for π-coefficients of (a) <100> channel and (b) <110> channel p-

DEMOS devices on [001] substrate under longitudinal stress.

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Figure 4-6. The polar plot for π-coefficients of (a) <100> channel and (b) <110> channel p-DEMOS devices on [001] substrate under transverse stress.

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Figure 4-7. Breakdown voltage shift due to stress is insignificant for p-DEMOS. There is about

0.135V due to 96 MPa of stress observed in this Figure. This extrapolates to about 0.5% shift for 100 MPa of stress.

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CHAPTER 5 SUMMARY

The work presented in this thesis is motivated by the fact that strained logic MOSFETs

have been widely adopted in commercial manufacturing to achieve better performance and

scaling in CMOS technologies. Power MOSFETs, however, are less studied and lag severely in

scaling to the CMOS logic devices. In this work, strain has been proven to significantly improve

performance of lateral power MOSFETs through experiments and π-coefficient modeling.

Piezoresistance coefficient is an effective parameter to estimate semiconductor device

performance under strain.[6] It is defined as normalized resistance change due to stress. So in

this work, π-coefficient measurements were performed in order to quantify on-resistance change.

The π-coefficients are measured by monitoring drain currents with stress while the devices are

operating at their linear region. The measured π-coefficients show that per 100 MPa

advantageous stresses, on-resistances reduce up to 2% and 5.1% in n-type LDMOS and p-type

DEMOS, respectively. On-resistance reduction is observed to be linear to current enhancement

at up to around 400 MPa stress (Figure 5-1).

Compared to strained logic silicon n-MOSFETs, strained lateral power MOSFETs show

similarities and differences in π-coefficients. At low gate bias, π-coefficients of both n-type and

p-type lateral power MOSFETs resemble those of their lateral logic counterparts. This is

because the most dominant on-resistance at low gate bias is channel resistance in both power

MOSFET and logic MOSFET and the changes of on-resistance due to stress are more or less the

same. At high gate voltage, experimental results for n-type power MOSFETs show reduced

enhancement with stress. This is explained by effect of vertical spreading of carriers into the

substrate. Experimental results for p-type power MOSFET at high gate voltage look like those

for p-MOSFET because on-resistance for p-DEMOS is mainly channel resistance at high gate

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voltage. Long channel length as in p-DEMOS greatly increases channel resistance to be much

larger than other resistance. STI is used in p-DEMOS with higher breakdown voltages.

However, because the channel length is large enough that channel resistance dominates at all

times. Therefore the on-resistance reductions are almost the same for p-LDMOS at both low

gate and high gate.

Breakdown voltage shifts, however, are observed to be stable with stress. Shifts of 0.3% to

0.5% is extrapolated due to 100 MPa stress to for both n-LDMOS and p-DEMOS. The amount

of shift is comparable to the voltage shift that comes from the unavoidable oxide charging

resulted in repeated experiments. Therefore we can conclude that breakdown voltage shift due to

stress is rather insignificant.

The above evidence demonstrates that advantageous stress breaks the on-resistance-

breakdown voltage tradeoff by enhancing on-resistance while maintaining breakdown voltage.

Therefore we can conclude that performance enhancements of lateral power MOSFET are made

possible by applying stress. The best performance enhancements are 2% and 5.1% in n-type

LDMOS and p-type DEMOS, respectively. These best enhancements are observed with the

most beneficial channel and uniaxial stress orientations of <100> longitudinal tensile stress and

<110> longitudinal compressive stress for n-type LDMOS and p-type DEMOS, respectively.

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Figure 5-1. Linear drain current enhancements under high stress.

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BIOGRAPHICAL SKETCH

Jingjing Michelle Liu was born in 1984 in Nanjing, China. She received her Bachelor of

Science degree in Applied Physics of Optic Information in 2006, from Nanjing University of

Science and Technology, China. Her undergraduate thesis is in real time image recognition

using C++ programming. In summer of 2007, she interned in Telemedicine Lab at University of

Texas Medical Branch as a graduate technical intern working on medical image optimization.

Her concentration for graduate study is in VLSI digital circuits design. She had several design

projects that involves low-power logic and memory design from schematic to layout. She is also

very interested in FPGA designs and computer architecture. Starting from May 2008, she joined

the advanced device research group of Dr. Scott Thompson and her research project is the strain

effects on lateral power MOSFETs. She received her Master of Science degree in electrical and

computer engineering at University of Florida in December 2009.