tf32a09read.pudn.com/downloads642/ebook/2600318/tf32a09...1.0 05/dec/2009 man liu initial draft...

TF32A09 Datasheet Rev. 1.0

Security SOC for High Speed Data Stream

and Special Keyboard

Copyright © 2009 TSINGHUA TONGFANG CO.,LTD Computer system business Group

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TSINGHUA TONGFANG CO.,LTD Computer system business Group

Revision History

Release Number Date Author Summary

1.0 05/Dec/2009 Man Liu Initial Draft

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Table of Contents

Section 1 Introduction ......................................................................................................... 10

1.1 Introduction ......................................................................................................... 10

1.2 Features ................................................................................................................ 10

1.3 Block Diagram ..................................................................................................... 15

Section 2 System Memory Map ......................................................................................... 17

2.1 Introduction ......................................................................................................... 17

2.2 Address Map ........................................................................................................ 17

Section 3 C*CORE CS320D Central Processor Unit (CPU) ........................................ 21

3.1 Introduction ......................................................................................................... 21

3.2 Features ................................................................................................................ 22

3.3 C*CORE Microarchitecture Summary ........................................................... 22

3.4 CS320D MPU Features ...................................................................................... 24

3.5 Programming Model .......................................................................................... 25

3.6 Data Format Summary ...................................................................................... 36

3.7 Operand Addressing Capabilities .................................................................. 37

3.8 Instruction Set Overview .................................................................................. 37

Section 4 Chip Configuration Module (CCM) ................................................................. 41

4.1 Introduction ......................................................................................................... 41

4.2 Features ................................................................................................................ 41

4.3 Modes of Operation ........................................................................................... 41

4.4 Application Field................................................................................................. 42

4.5 Signals Descriptions ......................................................................................... 43

4.6 Memory Map and Registers ............................................................................. 43

Section 5 Signal Description .............................................................................................. 49

5.1 Introduction ......................................................................................................... 49

5.2 Package Pinout Summary ................................................................................ 49

5.3 Signal Descriptions ........................................................................................... 62

Section 6 Reset Controller Module ................................................................................... 72

6.1 Overview ............................................................................................................... 72

6.2 Features ................................................................................................................ 72

6.3 Block Diagram ..................................................................................................... 73

6.4 Signals .................................................................................................................. 74


6.6 Functional Description ..................................................................................... 82

Section 7 Clock Module ....................................................................................................... 85

7.1 Overview ............................................................................................................... 85

7.2 Features ................................................................................................................ 85

7.3 Modes of Operation ........................................................................................... 85

7.4 Block Diagram ..................................................................................................... 87

7.5 Signal Descriptions ........................................................................................... 88


7.7 Function Description ......................................................................................... 98

7.8 Reset .................................................................................................................... 100

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7.9 Interrupts ............................................................................................................ 100

Section 8 Memory Integration Module ........................................................................... 101

8.1 Introduction ....................................................................................................... 101

8.2 Features .............................................................................................................. 101

8.3 Signal Description ............................................................................................ 102

8.4 Module Memory Map ....................................................................................... 103

8.5 Register Descriptions ..................................................................................... 104

8.6 Functional Description ................................................................................... 111

Section 9 Static Random Access Memory (SRAM) .................................................... 125

9.1 Introduction ....................................................................................................... 125

9.2 Modes of Operation ......................................................................................... 125

9.3 Low-Power Modes ............................................................................................ 125

9.4 Reset Operation ................................................................................................ 125

9.5 Interrupts ............................................................................................................ 125

Section 10 Interrupt Controller Module ................................................................... 126

10.1 Introduction ....................................................................................................... 126

10.2 Features .............................................................................................................. 126

10.3 Low-Power Mode Operation .......................................................................... 126

10.4 Block Diagram ................................................................................................... 127

10.5 External Signals ................................................................................................ 127

10.6 Memory Map and Registers ........................................................................... 128


Section 11 RSA/SM2 Accelerator Module ....................................................................... 145

11.1 Introduction ....................................................................................................... 145

11.2 Features .............................................................................................................. 145

11.3 Block Diagram ................................................................................................... 146

11.4 Memory Map ...................................................................................................... 147

11.5 RSA/SM2 Accelerator Module Operation ................................................... 166

Section 12 Watchdog Timer Module ......................................................................... 169

12.1 Introduction ....................................................................................................... 169


12.3 Block Diagram ................................................................................................... 170

12.4 Signals ................................................................................................................ 170


Section 13 Programmable Interrupt Timer Modules (PIT1/2) ............................. 177

13.1 Introduction ....................................................................................................... 177

13.2 Block Diagram ................................................................................................... 177


13.4 Signals ................................................................................................................ 178



13.7 Interrupt Operation .......................................................................................... 185

Section 14 Serial Communications Interface Modules (SCI1/2) ........................ 186

14.1 Introduction ....................................................................................................... 186

14.2 Features .............................................................................................................. 186

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14.3 Block Diagram ................................................................................................... 187





14.8 Data Format ....................................................................................................... 204

14.9 Baud Rate Generation ..................................................................................... 204

14.10 Transmitter ......................................................................................................... 206

14.11 Receiver .............................................................................................................. 211

14.12 Single-Wire Operation ..................................................................................... 221

14.13 Loop Operation ................................................................................................. 222

14.14 I/O Ports .............................................................................................................. 223

14.15 Reset .................................................................................................................... 223

14.16 Interrupts ............................................................................................................ 223

Section 15 DES .............................................................................................................. 225

15.1 Introduction ....................................................................................................... 225

15.2 Features .............................................................................................................. 225


15.4 Block Diagram ................................................................................................... 226

15.5 Module Memory Map and Register .............................................................. 226


15.7 Reset Operation ................................................................................................ 234

Section 16 Edge Port Module (EPORT) ................................................................... 235

16.1 Introduction ....................................................................................................... 235


16.3 Interrupt/General-Purpose I/O Pin Descriptions ...................................... 236


Section 17 SM1 .............................................................................................................. 242

17.1 Introduction ....................................................................................................... 242

17.2 Features .............................................................................................................. 242





Section 18 Universal Serial Interface Modules (USI1/2) ................................... 252

18.1 Introduction ....................................................................................................... 252

18.2 Features .............................................................................................................. 252

18.3 Block Diagram ................................................................................................... 253


18.5 Signal Descriptions ......................................................................................... 255


18.7 Function Descriptions ..................................................................................... 274

18.8 Interrupts ............................................................................................................ 278

Section 19 DMA Controller .......................................................................................... 281

19.1 Introduction ....................................................................................................... 281

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19.2 Features .............................................................................................................. 281


19.4 Block Diagram ................................................................................................... 282



Section 20 I2C ................................................................................................................ 290

20.1 Introduction ....................................................................................................... 290

20.2 Features .............................................................................................................. 290

20.3 System and Block Diagram ........................................................................... 291



Section 21 BCH .............................................................................................................. 303

21.1 Introduction ....................................................................................................... 303

21.2 Features .............................................................................................................. 303


21.4 Block Diagram ................................................................................................... 304




Section 22 On-Chip Emulation Module (OnCE) ..................................................... 314

22.1 Introduction ....................................................................................................... 314

22.2 Low-Level TAP (OnCE) Module .................................................................... 315

22.3 Signal Descriptions ......................................................................................... 317


Section 23 Pulse Width Modulator (PWM) .............................................................. 345

23.1 Introduction ....................................................................................................... 345

23.2 Features .............................................................................................................. 345

23.3 Block Diagram ................................................................................................... 346




23.7 Functional Descriptions ................................................................................. 356

Section 24 Serial Peripheral Interface Modules (SPI1/2) .................................. 358

24.1. Introduction ....................................................................................................... 358

24.2. Features .............................................................................................................. 358

24.3. Modes of Operation ......................................................................................... 359

24.4. Block Diagram ................................................................................................... 359




24.8 Reset .................................................................................................................... 385

24.9 Interrupts ............................................................................................................ 385

Section 25 Encryption Module Wrapper .................................................................. 387

25.1 Introduction ....................................................................................................... 387

25.2 Features .............................................................................................................. 387

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25.3 Block Diagram ................................................................................................... 388



25.6 Register Description ........................................................................................ 389

Section 26 KeyPad Port Module (KPP) .................................................................... 392

26.1 Introduction ....................................................................................................... 392


26.3 KPP Peripheral Pin Direction ........................................................................ 393


26.5 Keypad Operation ............................................................................................ 409

Section 27 FIFO Controller ......................................................................................... 414

27.1 Introduction ....................................................................................................... 414




Section 28 SMS4 ............................................................................................................ 426

28.1 Introduction ....................................................................................................... 426

28.2 Features .............................................................................................................. 426


28.4 Block Diagram ................................................................................................... 427




Section 29 Mini BCH ECC Controller ....................................................................... 437

29.1 Introduction ....................................................................................................... 437

29.2 Features .............................................................................................................. 437


29.4 Block Diagram ................................................................................................... 438


Section 30 USB2.0 OTG Controller Modules (USBCO1/2) .................................. 448

30.1 Introduction ....................................................................................................... 448

30.2 Features .............................................................................................................. 448


30.4 FUNCTION DESCRIPTION .............................................................................. 492

30.5 OPERATION ....................................................................................................... 495

Section 31 Ports Module.............................................................................................. 509

31.1 Introduction ....................................................................................................... 509

31.2 Signals ................................................................................................................ 509



31.5 Interrupts ............................................................................................................ 523

Section 32 True Random Number Generator (TRNG) .......................................... 524

32.1 Introduction ....................................................................................................... 524


32.3 Block Diagram ................................................................................................... 524

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Appendix A Preliminary Electrical Characteristic................................................... 529

A.1 General ................................................................................................................ 529

A.2 Absolute Maximum Ratings .......................................................................... 530

A.3 Electrostatic Discharge (ESD) Protection .................................................. 531

A.4 DC Electrical Specifications .......................................................................... 532

A.5 VD Electrical Specifications .......................................................................... 534

A.6 External Interface Timing Characteristics ................................................. 535

Appendix B Abbreviations And Terms ....................................................................... 536

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Section 1 Introduction

1.1 Introduction

TF32A09 is a multi-purpose MCU based on the C*CORE CS320 central processor unit (CPU). TF32A09 is designed to act as a controller for information security application.

The operating frequency has two domains: the domain of USB works at 60MHz, the domain of other parts works at 80MHz (up to 100MHz). The temperature range is of 0OC to 70OC.

Evaluation Chip package is:

• 176-pin QFP

Single-chip package is:

• 100-Pin QFP

• 80-Pin QFP

• 64-Pin QFP

• 48-Pin QFP

1.2 Features

Features of TF32A09:

• C*CORE C320 processor:

– 32-bit reduced instruction set computer (RISC) architecture

– Low power and high performance

– Followings are the secure features of CS320 compared to C310:

Integrate the MPU (memory protection unit) module with the CS320.

The MPU providing eight superuser programmable regions with flexible access attribute, data and address encryption features, as well as two fixed regions.

Support memory or peripheral access control.

It can be enabled or closed by the superuser.

• OnCE debug support

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• On-chip, 20K bytes of static random-access memory (SRAM):

– Single cycle byte, half-word (16-bit), and word (32-bit) reads and writes

• On-chip, 64K bytes of static read only memory (ROM):

– Single cycle byte, half-word (16-bit), and word (32-bit) read access.

• Interrupt controller:

– Up to 40 interrupt sources

– 32 unique programmable priority levels for each interrupt source

– Independent enable/disable of pending interrupts based on priority level

– Normal or fast interrupt request for each priority level

– Fast interrupt requests always have priority over normal interrupts

– Ability to mask interrupts at and below a defined priority level

– Ability to select between autovectored or vectored interrupt requests

– Vectored interrupts generated based on priority level

– Ability to generate a separate vector number for normal and fast interrupts

– Ability for software to self-schedule interrupts

– Software visibility of pending interrupts and interrupt signals to core

– Asynchronous operation to support wakeup from low-power modes

• External interrupts supported (EPORT):

– Rising/falling edge select

– Low-level sensitive

– Ability for software generation of external interrupt event

– Interrupt pins configurable as general-purpose I/O

• Two periodic interval timer:

– 16-bit counter with modulus "initial count" register

– Selectable as free running or count down – 16 selectable prescalers — 20 to 215

• Watchdog timer:

– 16-bit counter with modulus "initial count" register

– Pause option for low-power mode

• Reset :

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– Separate reset in and reset out signals

– Five sources of reset:

Power-on reset

Software reset

Watchdog timer

Power Attack Detect Reset (Low and High Voltage Detect Reset)

– Status flag indicates source of last reset

• Memory Integration Module:

– Three Chip Select channel, three for external SRAM, ROM, NORFLASH, NANDFLASH and memory mapped peripherals (Only for evaluation mode)

– Support for swap and bootload modes

– Bidirectional data bus with wide 32-bit and narrow 16-bit modes

– 26-bits address bus

– Bus monitor

• Two OTG USB Controllers:

– USB 2.0 Compliant with on-chip integrated PHY module

– Certified for High Speed (480MHz) USB and Full Speed (12MHz) USB

– UTMI+ Level 2 transceiver interface

– USBC1 Supports six transmit/receive endpoints

– USBC2 Supports three transmit/receive endpoints

• BCH controller:

– Hocquenghem, Bose, Chaudury (BCH) Algorithm

– Hardware "On the fly" Encoding/Decoding

– Supports 528 bytes and 540 bytes flash memory

– 14 bytes ECC codes for 528 type flash

– 26 bytes ECC codes for 540 type flash

– Can correct up to 8 bits data per page (512 data + 14 bytes ECC code).

– Can correct up to 14 bits data per page (512 data + 26 bytes ECC code).

– Decoding parallel working with key equation solver and error location searching.

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– Automatic error correction by hardware.

• DMA Controller:

– One fully programmable channel

– Dual-address transfer support with 8-, 16-, and 32-bit data capability

– Source/destination address pointers that can increment or remain constant

• Two serial communications interfaces (SCI):

– Full-duplex operation

– Standard mark/space non-return-to-zero (NRZ) format

– 13-bit baud rate prescaler

– Programmable 8-bit or 9-bit data format

– Separately enabled transmitter and receiver

– Separate receiver and transmitter CPU interrupt requests

– Two receiver wakeup methods (idle line and address mark)

– Receiver framing error detection

– Hardware parity checking

– 1/16 bit-time noise detection

– General-purpose I/O capability

• Two ISO7816 card interfaces (configuration to set Host or Device) :

– Can be configured as SCI

– Half-duplex operation

– Baud-rate selection refer to external card clock

– 9-bit guard time counter (GTCNT)

– 24 bits waiting time counter (WTCNT)

– Programmable transmitter output polarity

– Auto-character repetition on error signal detection in transmit mode

– Auto-error signal generation on parity error detection in receive mode

• Two serial peripheral interfaces (SPI) :

– Master mode and slave mode configurable

– Slave select output

– Mode fault error flag with CPU interrupt capability

– Double-buffered receiver

– Serial clock with programmable polarity and phase

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– Support once interrupt every 8, 16 or 32 bit transfer

– Control of SPI operation during wait mode

• One inter integrated circuit controller

– Compatible with I2C bus specification version 2.1

– Programmable Master/Slave Operation

– Start and stop signal generation detection

– Repeat START signal generation

– Acknowledge bit generation/detection

– Bus-busy detection

– Interrupt-driven or software-poll byte-by- byte data transfer

– Arbitration lost interrupt generation with automatic mode switch from master to slave

• Secure features

– Internal power on reset

– Voltage detector

– Data encryption

– Clock and reset pulse filtration

– Safe optimized routing

• RSA/SM2 Accelerator module

– Large operand size 192/256/512 bits integer arithmetic

– Programmable scalar or modulo operation

Y = A + B

Y = A - B

Y = A * B

Y = (A + B) mod M

Y = (A - B) mod M

Y = (A * B) mod M

Y = (1/A) mod M

Y = (AE) mod M

– Discrete "sea-of-gates" implementation to protection against SPA and probing attacks

– High performance N-bit ALU

1 to 3 clock cycles for modular addition/subtraction

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2N to 5N clock cycles for modular multiplication

Around 8N2 clock cycles (or less) for modular exponentiation/inversion

– Additional ’general purpose’ operations

Register Copy

Register Swap

Register Clear

Find First One

Montgomery Residue Conversion

Montgomery Product

Shift Right

Shift Left

• DES coprocessor

– Support DES and Triple-DES encryption and decryption algorithm

– Support DES algorithm with 64(56) bits key

– Support Triple-DES algorithm with 128(112) bits or 192(168) bits key

– Support ECB mode and CBC mode

– Support MLBBUS Interface with CS320D CPU

– Data process speed up to 27.83MBps@80MHz for DES

– Data process speed up to 11.64MBps@80MHz for Triple-DES

• TRNG (random number generator)

– Rate: 2.5MBps

• Voltage Detector

1.3 Block Diagram

Figure 1-1 is a block diagram of the system.

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12KBSRAM

64KBROM

USB2

USB1

IP Interface

INTCSM1

3DES

Cryption Control

WDT

PIT2PIT1

TRNG

Edge Port

SCI1 SCI2 USI1 USI2 I2C SPI2

SM2/RSA

OSC

POR

C*CORE(C320D)

DMAC

TEST&CCM

OnCE

Reset

PLL

Port

s

ECC

JTA

G T

AP

Mm

emor

y In

tegr

atio

n M

odul

e w

ith N

FC

INT[7:0]

DP

DM

XTALI

XTALO

Clock GenCLKOUT

PW

Mo

RX

D1

ISO

CLK

11IS

OD

AT1

ISO

RS

T1

SDA

SC

L

SPI1

MIS

O1

MO

SI1

SS1

SC

LK1

MIS

O2

MO

SI2

SS2

SC

LK2

ISO

CLK

12IS

OD

AT2

ISO

RS

T2

TXD

2

RX

D2

DP

DM

D[31:0]

A[25:0]

R/W

CS[1:0]

EB[3:0]

OE

FCE[3:0]

FWE

FALE

FCLE

FWP

TCLK

TMS

TDI

TDO

DE

TRST

RSTOUTPOR

TEST

MO

DE[

3:0]

PWM

TXD

1

8KBSRAM

SMS4

Figure 1- 1 Block Diagram

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Section 2 System Memory Map

2.1 Introduction

The address map, shown in 2.2, includes:

• 64K bytes of internal read only memory (ROM)

• 20K bytes of internal static random-access memory (SRAM)

– 12K (0x0080_2000 to 0x0080_4FFFF) for system

– 8K (0x0080_0000 to 0x0080_1FFFF) for USB or other data buffer

• Internal memory mapped registers

• 64M byte External Norflash address space and its shadow space

• 64M byte External SRAM address space

2.2 Address Map

REGISTERS

0x0000_0000

0x00C0_0000

0x00DF_FFFF

0xFFFF_FFFF

INTERNAL ROM

INTERNAL SRAM0x0080_4FFF

0x8000_0000

NORFLASH SHADOW

0x8400_0000

0x0080_0000

NORFLASH

0x8800_0000

0x8BFF_FFFF

EXTERNAL SRAM

NORFLASH

0x8000_FFFF0x8080_0000

Figure 2- 1 Debug Master Mode Address Map

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REGISTERS

0x0000_0000

0x00C0_0000

0x00DF_FFFF

0xFFFF_FFFF

0x0000_FFFFINTERNAL ROM

INTERNAL SRAM0x0080_4FFF

0x8000_0000

NORFLASH

0x8400_0000

0x0080_0000

NORFLASH

0x8800_0000

0x8BFF_FFFF

EXTERNAL SRAM

Figure 2- 2 Normal Master Mode Address Map

Table 2-1 Register Address Location Map1

1See module sections for details of how much of each block is being decoded. Accesses to

addresses outside the module memory maps (and also the reserved area 0x00d1_0000-0x7ffff_ffff)

will not be responded to and will result in a bus monitor transfer error exception.

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Address Maximum Size Usage

0x00c0_0000 64K byte PORTS

0x00c1_0000 64K byte Chip configuration (CCM)

0x00c2_0000 64K byte Memory Integration Module

0x00c3_0000 64K byte Clock Controller

0x00c4_0000 64K byte Reset (RESET)

0x00c5_0000 64K byte Interrupt controller (INTC)

0x00c6_0000 64K byte RSA Engine (RSA)

0x00c7_0000 64K byte Watchdog timer (WDT)

0x00c8_0000 64K byte Programmable interrupt timer 1 (PIT1)

0x00c9_0000 64K byte Programmable interrupt timer 2 (PIT2)

0x00ca_0000 64K byte SCI1

0x00cb_0000 64K byte SCI2

0x00cc_0000 64K byte Data Encryption Standard Module (DES)

0x00cd_0000 64K byte True Random Number Generator (TRNG)

0x00ce_0000 64K byte Edge Port (EPORT)

0x00cf_0000 64K byte SM1

0x00d0_0000 64K byte ISO7816_1

0x00d1_0000 64K byte ISO7816_2

0x00d2_0000 64K byte DMAC (CLB master)

0x00d3_0000 64K byte I2C

0x00d4_0000 64K byte BCH

0x00d5_0000 64K byte NFC IO Channel

0x00d6_0000 64K byte PWM

0x00d7_0000 64K byte SPI1

0x00d8_0000 64K byte SPI2

0x00d9_0000 64K byte FIFO_IF

0x00da_0000 64K byte ENCR_Wrapper

0x00db_0000 64K byte SMALL_BCH

0x00dc_0000 64K byte KPP

0x00dd_0000 64K byte Reversed

0x00de_0000 64K byte SMS4

0x00df_0000 64K byte Reversed

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0x00e0_0000 64K byte USBCO1 (OTG Interface)

0x00e1_0000 64K byte USBCO2 (OTG Interface)

Table 2- 1

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Section 3 C*CORE CS320D Central Processor Unit (CPU)

3.1 Introduction

The CS320D is a 32-bit RISC core designed specifically for secure applications. The CS320D is a member of the C*CoreTM 32-bit RISC core family. In addition to providing all the C310 core features, the CS320D includes a memory protection unit (MPU) integrated with the core. The MPU module provides additional security features to the CS320D core, which include flexible and powerful access protection modes, data encryption/decryption and address scrambling, etc. It further enhances protection against unauthorized access to sensitive data by providing two fixed and eight superuser programmable memory regions.

The C*CORE C3XX central processor unit (CPU) architecture is one of the most compact, full 32-bit core implementations available. The pipelined reduced instruction set computer (RISC) execution unit uses 16-bit instructions to achieve maximum speed and code efficiency, while conserving on-chip memory resources. The instruction set is designed to support high-level language implementation. A non-intrusive resident debugging system supports product development and in-situ testing.

Total system power consumption is determined by all the system components, rather than the CPU alone. In particular, memory power consumption (both on-chip and external) is a dominant factor in total power consumption of the CPU plus memory subsystem. With this in mind, the CPU instruction set architecture trades absolute performance capability for reduced total energy consumption. This is accomplished while maintaining a high level of performance at a given clock frequency.

A strictly defined load/store architecture minimizes control complexity. Use of a fixed, 16-bit instruction encoding significantly lowers the memory bandwidth needed to sustain a high rate of instruction execution, and careful selection of the instruction set allows the code density and overall memory efficiency of the CPU architecture to surpass those of complex instruction set computer (CISC) architectures.

These factors reduce system energy consumption significantly, and the fully static CPU design uses other techniques to reduce power consumption even more. The CPU uses dynamic clock management to automatically power-down internal functions that are not in use on a clock-by-clock basis. It also incorporates three power-conservation operating modes, which are invoked via dedicated instructions.

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3.2 Features

The main features of the CPU are:

32-bit load/store RISC architecture

Fixed 16-bit instruction length

13 entry, 32-bit control register file

16 entry, 32-bit general-purpose register file

Efficient 4-stage execution pipeline

Single-cycle execution for most instructions, 2-cycle branches and memory accesses

Support for byte/half-word/word memory access

Fast interrupt support

Availability of alternate general purpose register file

Vectored and autovectored interrupt support

On-chip emulation support (OnCE)

Full static design for minimal power consumption

Powerful security features

- Memory Protection Unit

- Data Encryption

- Address Scrambling

3.3 C*CORE Microarchitecture Summary

Figure 3-1 is a block diagram of the C*CORE processor. The processor utilizes a 4-stage pipeline for instruction execution. The instruction fetch, instruction decode/register file read, execute, and register file writeback stages operate in an overlapped fashion, allowing single clock instruction execution for most instructions.

The execution unit consists of a 32-bit arithmetic/logic unit (ALU), a 32-bit barrel shifter, a find-first-one unit, result feed-forward hardware, support hardware for multiplication and division, and multiple-register load and store instructions.

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Figure 3- 1 C*CORE Processor Block Diagram

Arithmetic and logical operations are executed in a single cycle. Multiplication is implemented with 16x32 hardware multiplier unit, allowing single-cycle operation for signed 16x16 and unsigned 16x32 products, and two-cycle operation for 32x32 products. Divide is implemented with a 1-bit per clock early-in algorithm. The find-first-one unit operates in one clock cycle.

The program counter unit incorporates a dedicated branch address adder to minimize delays during change of flow operations. Branch target addresses are calculated in parallel with branch instruction decode. Taken branches and jumps require only two clocks; branches which are not taken execute in one clock cycle.

Memory load and store operations are provided for 8-bit (byte), 16-bit (halfword), and 32-bit (word) data, with automatic zero extension for byte and half-word load operations. Due to the pipelined bus architecture, these instructions can execute in a single clock cycle when performing back-to-back accesses, or two clock cycles when mixed with other instructions (one cycle for address generation, one cycle for data transfer). Load and store multiple register instructions allow low overhead context save and restore operations. These instructions can execute in (N+1) clock cycles, where N is the number of registers to transfer.

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A condition code/carry (C) bit is provided for condition testing or for use in implementing arithmetic and logical operations with operands/results greater than 32 bits. The C bit is typically set by explicit test/comparison operations, not as a side-effect of normal instruction operation. Exceptions to this rule occur for specialized operations where it is desirable to combine condition setting with actual computation.

The processor uses autovectors for both normal and fast interrupt requests. Fast interrupts take precedence over normal interrupts. Both types have dedicated exception shadow registers. For service requests of either kind, an automatic vector is generated when the request is made.

3.4 CS320D MPU Features

A Memory Encryption Unit (MEU) is provided to protect sensitive data from attack. The MPU/MEU features can only be enabled/disabled by superuser. There are one superuser access region for Exception Vector Table and Operating System (OS), and eight superuser programmable regions. The programmable regions can be explicitly enabled/disabled by the superuser. The Exception Vector Table/OS and MPU Control Space regions are always protected.

Eight superuser programmable regions

- Variable region size: 1K byte to 4G byte

- Can be based anywhere in the 4G byte memory map

- Region base address automatically aligned to the region size

- Programmable data and address encryption/decryption

- Flexible access permissions:

- Superuser/user access

- Read/write access

- Execute (instruction fetch) access

Regions allowed to overlap (strictest access permissions enforced for overlapped regions)

One superuser access region for Exception Vector Table and Operating System (OS)

Fixed size: 4K byte

- Fixed location: 0x00000000

- Data and address encryption

- Fixed access permission

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- Superuser read/write/ execute access only

One superuser access region for the MPU Control Space

- Fixed size: 64K byte

- Fixed location: 0xFFFF0000

- Fixed access permission

- Superuser read/write access only

Programmable 32-bit data/address encryption key

Status register contains attribute and region details of access violations

3.5 Programming Model

Figure 3-2 shows the C*CORE processor programming model. The model is defined differently for supervisor and user privilege modes. By convention, in both modes R15 serves as the link register for subroutine calls. R0 is typically used as the stack pointer.

Figure 3- 2 Programming Model

The user programming model consists of 16 general-purpose 32-bit registers (R0–R15), the 32-bit PC, and the C bit. The C bit is implemented as bit 0 of the

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Processor Status Register (PSR) and is the only portion of the PSR accessible in the user model.

The supervisor programming model consists of the user model plus 16 additional 32-bit general-purpose registers (R0–R15), called the alternate file and a set of status/control registers (CR0–CR12) which includes the entire PSR. Setting the S bit in the PSR enables supervisor mode operation.

The alternate file allows very low overhead context switching for real-time event handling. While the alternate file is enabled, general-purpose registers are accessed from it.

The Vector Base Register (VBR) function is disabled in the CS320D for security reasons, and always reads zero. Exception shadow registers EPC and EPSR are used to save the states of the program counter and PSR, respectively, when an exception occurs. Shadow registers FPC and FPSR save the states of the program counter and PSR, respectively, when a fast interrupt exception occurs.

Five scratch registers (SS0–SS4) are used to handle exception events.

The global control (GCR) and status (GSR) registers can be used for a variety of system monitoring tasks at the discretion of the compiler used. They serve no specific function by or for the CPU.

3.5.1 MPU Programming Model

The following sections describe the MPU Programming Model, Memory Map and Registers.

3.5.1.1 MPU Defined C*CORE Memory Map

The MPU occupies a 64K byte block of memory within the C*Core memory map as illustrated in the following table. (see Table 3-1 CS320D Memory Map)

Table 3-1 CS320D Memory Map

Logical Address Range Purpose Supervisor Access User Access

0x00000000 - 0x000001FF Exception Vector

Table Read/Write/Execute Access Error

0x00000200 - 0x00000FFF Operating System

Routines Read/Write/Execute Access Error

0x00001000 - 0xFFFEFFFF User/supervisor Address Space

Selective Selective

27


0xFFFF0000 - 0xFFFFFFFF MPU Control Space Read/Write Access Error

Table 3- 1

NOTE: This is the logical address range, which is related but not equal to the physical address range. For example, due to the address encryption, the exception vectors are physically located not in the lowest 512 byte block, but scattered throughout the first 1K byte block, mixed in with the Operating System routines.

The Supervisor can access all of the address space (unless programmed otherwise), while the address space potentially available for user accesses is a mapped segment of nearly 4G bytes, located from address 0x00001000 to 0xFFFEFFFF. User accesses outside of this range result in an access error.

While the access of the entire 4G byte address range is programmable via the MPU’s partition registers, the exception vector table and (part of) the operating system, as well as the control and status registers of the MPU module occupy fixed regions of the memory map. In effect, there are ten memory regions, eight fully programmable via the MPU and two hardwired to have properties as listed in the following table. (see Table 3-2 MPU Regions Definitions).

Table 3-2 MPU Regions Definitions Region 0-7 8 9

Purpose Software Programmable Vector Table

and OS MPU Control Space

Base Address 0x00000000 - 0xFFFFFC00 Fixed:

0x00000000 Fixed: 0xFFFF0000

Size 1K byte - 4G byte 4K byte 64K byte

Access Supervisor/User

Read/Write/Execute

Supervisor Read/Write/Exec

ute

Supervisor Read/Write

Enabled Programmable On/Off Always Always

Encryption YES YES NO

The lower half of the first 1K byte block of the address range (0x00000000 - 0x000001FF) is reserved for the 128 Entry (encrypted) Exception Vector Table, and is programmed to be supervisor read/write/execute-only.

The second lowest block of the address range (0x00000200 - 0x00000FFF) is also programmed to be supervisor read/write/execute-only and is intended to be used to store (encrypted) Operating System routines.

28


It is not assumed that the Operating System will necessarily be limited to 3.5K byte. Rather, the first 3.5K byte is intended to store initialization routines which securely (re-)configure the MPU to provide whatever additional space is required for the full Operating System.

3.5.2 MPU Registers

The MPU registers memory map are listed in the following table: (see Table 3-3 MPU Registers Address Map)

Table 3-3 MPU Registers Address Map

Address Register Description

0xFFFF_0000 MPUCSR MPU Control and Status Register

0xFFFF_0004 MPUEKR MPU Encryption Key Register

0xFFFF_0008 MPURR0 MPU Region Configuration Register 0

0xFFFF_000C MPURR1 MPU Region Configuration Register 1




0xFFFF_001C MPURR5 MPU Region Configuration Register 5



3.5.2.1 MPU Control and Status Register

The MPUCSR serves two purposes. One, it provides an enable function for the MPU, and two, it stores status information of the last Memory Access Violation. The MPUCSR is detailed in the following table.

Address: 0xFFFF_0000 and 0xFFFF_0001

Bit 15 14 13 12 11 10 9 Bit 8

Read R9V R8V R7V R6V R5V R4V R3V R2V

Write

Reset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 Bit 0

Read R1V R0V TC2 TC1 TC0 RW RSVD EN

Write

29


Reset 0 0 0 0 0 0 0 0

Table 3- 2 MPU Control and Status Register

RnV — Region n Violation 1= An access violation has occurred in region n. 0= No access violation has occurred in region n

NOTE: Bit R8V corresponds to the pre-defined Exception Vector and OS Region (address 0x00000000 to 0x00000FFF) and bit R9V corresponds to the pre-defined MPU Control Space Region (address 0xFFFF0000 to 0xFFFFFFFF).

TC [2:0] — Transfer Code The TC bits store the value of the Transfer Code signal (rce_tc[2:0] - similar to p_tc[2:0] but internal to the core) associated with the last transaction which caused an access violation.

RW — Read/Write The RW bit stores the Read/Write strobe (rce_rw_b - similar to p_rw_b but internal to the core) associated with the last transaction which caused an access violation.

EN — MPU Enable 1= The MPU programmable regions are enabled. 0= The MPU programmable regions are disabled.

NOTE:

The MPU Enable bit only enables/disables the Programmable Regions 0-7. The pre-defined Exception Vector and OS Region and the MPU Control Space Region are always enabled.

3.5.2.2 MPU Encryption Key Register

The Encryption Key Register is used to store a 32-bit encryption key, which is used to encrypt/decrypt the external data output/input bus and encrypt the address bus for any of the eight Programmable Regions if the corresponding encryption bit is enabled.

The data bus encryption works at the byte-level, i.e. each byte of a halfword or word access is encrypted separately. The address bus encryption works on 1K byte blocks and is word-aligned, i.e. the most significant 22 bits and the least significant two bits of the address are not scrambled.

Address:0xFFFF_0004 and 0xFFFF_0007

Bit31 30 . . . . . . 1 Bit 0

30


R EK[31:0]

W

RESET: 0 Reset Dependant

= Writes have no effect and terminate without transfer error exception

Table 3- 3 MPU Encryption Key Register

EK[31:0] — Encryption Key Value

NOTE:

Region eight (Exception Vector Table and OS) uses a fixed (hard-coded) encryption key. Region nine (MPU Control Space) does not have an encryption feature.

3.5.2.3 MPU Region Configuration Registers 0-7

The MPU Region Configuration Registers (MPURRn) define the size and attributes of the eight Programmable Regions. The ninth region (Vector Table and OS) and tenth region (MPU Control Space) are hardwired and do not have a configuration register.

Address: 0xFFFF_0024 to 0xFFFF_0027 Address: 0xFFFF_0020 to 0xFFFF_0023 Address: 0xFFFF_001C to 0xFFFF_001F Address: 0xFFFF_0018 to 0xFFFF_001B Address: 0xFFFF_0014 to 0xFFFF_0017 Address: 0xFFFF_0010 to 0xFFFF_0013 Address: 0xFFFF_000C to 0xFFFF_000F Address: 0xFFFF_0008 to 0xFFFF_000B

31


Bit 31 30 29 28 27 26 25 Bit 24

Read ADDRESS[31:24]

Write

Reset 0 0 0 0 0 0 0 0

Bit 23 22 21 20 19 18 17 Bit 16

Read ADDRESS[23:16]

Write

Reset 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 Bit 8

Read ADDRESS[15:10] SIZE[4:3]

Write

Reset 0 0 0 1 0 0 0 1

Bit 7 6 5 4 3 2 1 Bit 0

Read SIZE[2:0] EE AP[3:0]

Write

Reset 0 0 1 1 0 0 0 0

Table 3- 4 MPU Region Configuration Registers MPURR0-MPPURR7

ADDRESS — Region Base Address The base address of the region. Note that the address comparison will be automatically aligned with the size of the region as defined in the SIZE field.

SIZE[4:0] — Region Size The size of the region, as defined in Table 3-4:

Table 3-4 Region Size Encoding SIZE[4:0] Value Region Size

00000-01000 Reserved (1K byte)

01001 1K byte

01010 2K byte

01011 4K byte

01100 8K byte

32


01101 16K byte

01110 32K byte

01111 64K byte

10000 128K byte

10001 256K byte

10010 512K byte

10011 1M byte

10100 2M byte

10101 4M byte

10110 8M byte

10111 16M byte

11000 32M byte

11001 64M byte

11010 128M byte

11011 256M byte

11100 512M byte

11101 1G byte

11110 2G byte

11111 4G byte

EE — Region Encryption Enable 1= Address will be encrypted and data will be encrypted/decrypted in this region using the key in the MPUEKR. 0= Address and data will not be encrypted in this region.

AP [3:0] — Region Access Permissions The Access Permissions determine the level of access protection for a region.

Table 3-5 Region Access Permissions AP[3:0] User Access Supervisor Access

0000 R W X R W X

0001 R --- X R W X

0010 R --- -- R W X

0011 -- --- X R W X

0100 -- --- -- R W X

33


0101 -- --- -- R --- X

0110 -- --- -- R --- --

0111 -- --- -- -- --- X

1000 R --- X R --- X

1001 R --- -- R --- --

1010 -- --- X -- --- X

1011 -- --- -- -- --- --

1100 R W -- R W --

1101 -- --- -- R W --

1110-1111 (Reserved) -- --- -- -- --- --

NOTE: R = Read, W = Write, X = Execute (Instruction Fetch)

3.5.3 MPU Usage Scenarios

The following sections contain Usage Scenarios which further explain the (possible) operation of the MPU. Some of these scenarios are intended only as examples of how to use the MPU in a system.

3.5.3.1 Access Violation Mechanism

1. When the core attempts to make a memory (or peripheral) access via the C*CORE Local Bus (CLB), the MPU will compare the address (bit-wise) against the base addresses of the ten regions, eight programmable (n=0..7) and two (n=8,9) fixed regions.

2. The results of these address comparisons are then masked based on the sizes of the memory regions (automatic alignment), i.e. only the size-aligned portions of the access address and region base addresses are effectively compared. This event is called Region Address Match (RAMn). There may be ten possible of these events for any access (n=0..9).

3. In parallel with the address matches, the transfer code and read/write signals are compared against the access permissions of each of the ten regions. When there is a mismatch with the permissions, an event Region Permission Violation (RPVn) is generated. There may be ten possible of these events for any access (n=0..9).

4. When there are one or more cases of both RAMn and RPVn matches for a region n, an access violation will occur. The address and control signals are immediately gated off and an internal TEA signal is generated. The data output is gated off in the next cycle.

34


5. Finally, if there is an access but none of the RAMn (n=0..9) events are true/one, an access violation is also generated.

3.5.3.2 Storing the Transfer Attributes

The transfer attributes (TC[2:0] and RW) are stored in the MPUCSR every time a violation occurs. If for some reason there are multiple violations in a row (e.g. there is an access violation and the subsequent access violation exception vector fetch also causes a violation), only the transfer attributes of the last violation will be stored in the MPUCSR. Note that under normal circumstances, in case of the occurrence of two access violations in a row, the core will attempt to execute the unrecoverable error exception routine (rather than access violation). If this also fails (i.e. there is yet another access violation), the behavior of the core is undefined. The likely result will be that the system halts.

3.5.3.3 Storing the Region Violation Bits

The Region Violation bits (RnV) in the MPUCSR are updated for every access as follows:

1. When both the RAMn and RPVn events are true for any region n, the corresponding RnV bit in the MPUCSR is set.

2. When either of the RAMn and RPVn events are false for any region n, the corresponding RnV bit in the MPUCSR is cleared. Note that it is possible to have a violation while all the RnV bits are cleared. (see 3.5.3.1 Access Violation Mechanism)

3.5.3.4 Locking the MPU

It is possible to lock the MPU (keep it in its current state), for example by programming a supervisor read-only region on top of the MPU Control Space region and then enabling the MPU. Only a system reset can unlock the MPU again.

It is also possible to block access to the entire C*Core memory map (as part of a tamper protection strategy), for example by enabling a 4G byte region with access permission PA[3:0]=4b1011.

3.5.3.5 Secure System Initialization

To enable the use of the MPU to provide maximum security in a system application, the ninth region is hard-wired to define an encrypted 4K byte supervisor read/write/execute-only region located at address 0x00000000.

35


The system initialization starts with the fetching of the reset vector, which should point to somewhere in between the logical addresses 0x00000200 and 0x00000FFF. The reset exception routine should start by enabling the MPU (write a one to the MPUCSR at address 0xFFFF0000), after suitable values have been written to the MPUEKR and MPURR0-MPURR7. One or more of the regions 0-7 could be used to store additional (encrypted) operating system routines. These regions can all have different encryption keys, which would be programmed through routines stored in the Exception Vector and OS region.

Note that great care should be taken when changing the encryption key ’on the fly’ from within an encrypted region (other than the fixed 4K byte Exception Vector and OS region), since this will alter both the data and the address encryption within the region, which could lead to unexpected results.

The safest option is to only re-program the MPU from within the fixed Exception Vector and OS region, however, if the encryption key is indeed changed ’on the fly’ from within regions 0-7, it is imperative to immediately follow the encryption key change with a jump to a different (encrypted) region. In this case, the instruction pre-fetch buffering should ensure in most cases that the change in data/address encryption does not cause unexpected results.

Note that great care should also be taken when defining overlapping regions. When there is overlap between an encrypted region and a non-encrypted regions, accesses from the overlap area will be encrypted.

3.5.3.6 Determining the Violation Type

The determination of what type of violation occurred and in which region(s) the violation happened should be made in software. For this purpose, the MPU provides information in the MPUCSR about the last access violation. The RnV bits indicate the region(s) involved and the TC[5:3] and RW[2] bits show what type of access was attempted. The access violation exception routine should poll the Region Configuration Registers MPURRn for those regions which have the RnV bit set.

When the permissions in the AP[3:0] bits of the MPURRn are compared against the saved attributes of the attempted access, it is possible to determine the type of violation.

This violation type information can, for example, be used to update a ’tamper counter’ which could block out or render inoperative the system after a certain number of illegal accesses.

If there is a violation but none of the RnV bits are set, it is clear that an access was attempted from outside any defined region.

36


3.6 Data Format Summary

The operand data formats supported by the integer unit are standard two’s-complement data formats. The operand size for each instruction is either explicitly encoded in the instruction (load/store instructions) or implicitly defined by the instruction operation (index operations, byte extraction). Typically, instructions operate on all 32 bits of the source operand(s) and generate a 32-bit result.

Memory is viewed from a big-endian byte ordering perspective. The most significant byte (byte 0) of word 0 is located at address 0. Bits are numbered within a word starting with bit 31 as the most significant bit.

Table 3- 5 Data Organization in Memory

Table 3- 6 Data Organization in Registers

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3.7 Operand Addressing Capabilities

The C*CORE processor accesses all memory operands through load and store instructions, transferring data between the general-purpose registers and memory. Register-plus-four-bit scaled displacement addressing mode is used for load and store instructions addressing byte, half-word, and word data.

Load-and-store-multiple instructions allow a subset of the 16 general-purpose registers to be transferred to or from a base address pointed to by register R0 (the default stack pointer by convention).

Load and store register quadrant instructions use register indirect addressing to transfer a register quadrant to or from memory.

3.8 Instruction Set Overview

The instruction set is tailored to support high-level languages and is optimized for those instructions most commonly executed. A standard set of arithmetic and logical instructions is provided, as well as instruction support for bit operations, byte extraction, data movement, control flow modification, and a small set of conditionally executed instructions which can be useful in eliminating short conditional branches.

Table 3-6 is an alphabetized listing of the C*CORE instruction set. Note that the execution times in this table are for a zero wait state system. For multiple wait state systems, the execution of various instructions depends on bus access times. Refer to the C*CORE Reference Manual for more details on instruction operation.

Table 3-6 C*CORE Instruction Set

Mnemonic Description Execution Time

(Cycles)

ABS

ADDC

ADDI

ADDU

AND

ANDI

ANDN

ASR

ASRC

Absolute Value

Add with C Bit

Add Immediate

Add Unsigned

Logical AND

Logical AND Immediate

AND NOT

Arithmetic Shift Right

Arithmetic Shift Right, Update C Bit

1

1

1

1

1

1

1

1

1

38


BCLRI

BF

BGENI

BGENR

BKPT

BMASKI

BR

BREV

BSETI

BSR

BT

BTSTI

Bit Clear Immediate

Branch on Condition False

Bit Generate Immediate

Bit Generate Register

Breakpoint

Bit Mask Immediate

Branch

Bit Reverse

Bit Set Immediate

Branch to Subroutine

Branch on Condition True

Bit Test Immediate

1

1 not taken 2 taken 1

1

4 1

2

1

1

2 1 not taken 2 taken

1

CLRF

CLRT

CMPHS

CMPLT

CMPLTI

CMPNE

CMPNEI

Clear Register on Condition False

Clear Register on Condition True

Compare Higher or Same

Compare Less Than

Compare Less Than Immediate

Compare Not Equal

Compare Not Equal Immediate

1

1

1

1

1

1

1

DECF

DECGT

DECLT

DECNE

DECT

DIVS

DIVU

DOZE

Decrement on Condition False

Decrement Register and Set Condition if Result Greater Than Zero

Decrement Register and Set Condition if Result Less Than Zero

Decrement Register and Set Condition if Result Not Equal to Zero

Decrement on Condition True

Divide Signed Integer

Divide Unsigned Integer

Doze

1

1

1

1

1

3–38 3–38

1

FF1 Find First One 1

IDLY4

INCF

INCT

IXH

IXW

Delay Interrupt Recognition

Increment on Condition False

Increment on Condition True

Index Half-Word

Index Word

1

1

1

1

1

JAVASW

JMP

JMPI

JSR

JSRI

Java Interpreter Switch

Jump

Jump Indirect

Jump to Subroutine

Jump to Subroutine Indirect

2

2

3

2

3

39


LD.[BHW]

LDM

LDQ

LRW

LSL, LSR

LSLC, LSRC

LSLI, LSRI

Load

Load Multiple Registers (n=actual number of registers moved)

Load Register Quadrant

Load Relative Word

Logical Shift Left and Right

Logical Shift Left and Right, Update C Bit

Logical Shift Left and Right by Immediate

2

n+1 5

1

1

1

1

MFCR

MOV

MOVI

MOVF

MOVT

MTCR

MULSH

MULT

MVC

MVCV

Move from Control Register

Move

Move Immediate

Move on Condition False

Move on Condition True

Move to Control Register

Multiply Signed Halfwords

Multiply

Move C Bit to Register

Move Inverted C Bit to Register

1

1

1

1

1

1

1

1 (16x32) 2 (32x32) 1

1

NOT Logical Complement 1

OR Logical Inclusive-OR 1

PSRCLR

PSRSET

Clear selected PSR bits

Set selected PSR bits

1

1

ROTLI

RSUB

RSUBI

RTE

RFI

Rotate Left by Immediate

Reverse Subtract

Reverse Subtract Immediate

Return from Exception

Return from Fast Interrupt

1

1

1

3

3

SEXTB

SEXTH

ST.[BHW]

STM

STQ

STOP

SUBC

SUBU

SUBI

SYNC

Sign-Extend byte

Sign-Extend Half-Word

Store

Store Multiple Registers (n=actual number of registers moved)

Store Register Quadrant

Stop

Subtract with C Bit

Subtract

Subtract Immediate

Synchronize

1

1

2

n+1 5

1 1

1

1

1

TRAP

TST

TSTNBZ

Trap

Test Operands

Test for No byte Equal Zero

4

1

1

WAIT Wait 1

40


XOR

XSR

XTRB0

XTRB1

XTRB2

XTRB3

Exclusive OR

Extended Shift Right

Extract byte 0

Extract byte 1

Extract byte 2

Extract byte 3

1

1

1

1

1

1

ZEXTB

ZEXTH

Zero-Extend byte

Zero-Extend Half-Word

1

1

41


Section 4 Chip Configuration Module (CCM)

4.1 Introduction

The chip configuration module (CCM) controls the chip configuration and mode of operation.

4.2 Features

The CCM performs these operations.

Selects the chip operating mode

- Normal Master mode

- Debug Master mode

- Factory access slave test (FAST) mode for factory test only

- Special test modes for analog IPs’ tests only

Selects application field (Boot indicator)

Selects boot device

USB configuration

Chip pad configuration

Selects bus monitor configuration

4.3 Modes of Operation

The CCM configures the chip for following modes of operation:

Normal Master mode

Debug Master mode

FAST mode for factory test only

Test mode for 3rd part IPs

The operating mode is determined at reset and cannot be changed thereafter.

42


4.3.1 Debug Master Mode

In debug master mode, the boot device is also external memories. The external bus consists of a 16-bit data bus and 26 address lines during booting. Available bus control signals include R/W, OE and EB[3:0]. Up to 2 chip selects can be programmed to select and control external devices and to provide bus cycle termination.

4.3.2 Normal Master Mode

In normal master mode, the boot device is internal ROM.

4.3.3 Factory Access Slave Test (FAST) Mode

FAST mode is for factory test only.

4.3.4 Special IP Test Mode

For special IPs’ test only. For example, the PLL, SM1 and TRNG are supplied by the 3rd IP vendors. In special IP Test Mode, the test patterns can be sent to the IPs directly by the chip’s external pin.

4.4 Application Field

In normal master mode, the chip has three boot application: USB Keyboard, Real-time cypto and Normal boot. And Mode[3:2] determine the chip application. More detail see "TF32A09芯片Boot概要设计说明书" and "TF32A09芯片Boot详细设计说明书.

4.4.1 USB Keyboard

In this mode, the chip will run USB keyboard firmware. More detail see "TF32A09芯片USB键盘概要设计说明书" and "TF32A09芯片USB键盘详细设计

说明书".

4.4.2 Real-time Crypto

In this mode, the chip will run real-time crypto firmware. More detail see "加密

装置概要设计说明书" and "加密装置详细设计说明书".

4.4.3 Force Load Code

In this mode, the chip will run force load code mode firmware. More detail see "TF32A09芯片Boot概要设计说明书" and "TF32A09芯片Boot详细设计说明书".

43


4.4.4 Normal Boot Mode

In this mode, the chip will run normal boot mode firmware. More detail see "TF32A09芯片Boot概要设计说明书" and "TF32A09芯片Boot详细设计说明书".

4.5 Signals Descriptions

Table 4-1 provides an overview of the CCM signals. For more detailed information, refer to Section 5 Signal Description.

Table 4-1 Signal Properties

Name Function Reset State

MODE[1:0] Modes Selects Internal weak pullup device

MODE[3:2] Boot Indicator Internal weak pullup device

TEST Modes Selects Internal weak pulldown device

Table 4- 1

4.6 Memory Map and Registers

This subsection provides a description of the memory map and registers.

4.6.1 Programming Model

The CCM programming model consists of the following registers:

CCR — chip configuration register: controls chip configuration. (See 4.6.3.1 CCR — Chip Configuration Register).

CIR — chip identification register: contains a unique part number. (See 4.6.3.2 CIR — Chip Identification Register)

Some control register bits are implemented as write-once bits. These bits are always readable, but once the bit has been written, additional writes have no effect, except during debug and test operations.

Some write-once bits and test bits can be read and written while in debug mode or test mode. When debug or test mode is exited, the chip configuration module resumes operation based on the current register values. If the first write to a write-once register bit occurs while in debug or test mode, the register bit remains writable on exit from debug or test mode. Table 4-2 shows the accessibility of write-once bits.

44


Table 4-2 Write-Once Bits Read/Write Accessibility

Configuration Read/Write Access

All configurations Read-always

Debug operation (all modes) Write-always

Test operation (all modes) Write-always

Master mode Write-once

FAST mode Write-once

4.6.2 Memory Map

Table 4-3 CCM Memory Map

Address 31:16 15:0 Access1

0x00c1_0000 CCR — chip configuration register Reserved2 S

0x00c1_0004 Reserved2 CIR — chip identification register S

0x00c1_0008 CTR — chip test register Reserved2 S

NOTE:

1. S = supervisor-only access. User mode accesses to supervisor only address locations have no

effect and result in a cycle termination transfer error.

2. Writing to reserved addresses has no effect; reading returns zeros.

45


4.6.3 Register Descriptions

4.6.3.1 CCR — Chip Configuration Register

Address : 0x00c1_0000 and 0x00c1_0001

Bit15 14 13 12 11 10 9 Bit8

Read: USB1DIS USB2DIS USI2PEN

JTAGDIS MODE3 MODE2 MODE1 MODE0

Write:

RESET: 0 0 0 0 Note2 Note1 Note1 Note1

Bit7 6 5 4 3 2 1 Bit0

Read: USBENDI

AN KPPEN SHINT BME BMD BMT

Write:

RESET: 0 0 0 1 0 0 0

= Writes have no effect and the access terminates without a transfer error exception.

Figure 4- 1 CCR — Chip Configuration Register

USB1DIS — USB 1 Disable Bit 1= USB 1 is disabled 0= USB 1 is enabled

USB2DIS— USB 2 Disable Bit 1= USB 2 is disabled 0= USB 2 is enabled

JTAGDIS— JTAG Disable Status The bit reflects the JTAG whether is enabled or disable. When the address 0x60 of internal ROM is 0x55a5aa5a, the JTAG is disabled.

1= JTAG is disabled 0= JTAG is enabled

MODE[1:0] — Chip Configuration Mode Field This read-only field reflects the chip configuration mode as shown in Table 4-4(See 4.3 Modes of Operation).

2Reset Value is determined by PIN status.

46


Table 4-4 Chip Configuration Mode Selection

MODE[1:0] Chip Configuration Mode

00 FAST mode

01 Special IP Test Mode

10 Debug Master Mode

11 Normal Master Mode

Mode[3:2] — Boot Indicator This read-only field is the indicator of Boot as shown in Table 4-5.

Table 4-5 Boot Indicator Selection MODE[3:2] Application

00 USB Keyboard mode

01 Real Time Encryption application mode

10 Force load code mode

11 Normal boot mode

SHINT — Show Interrupt Bit The SHINT bit allows visibility to any active interrupt request to the processor. If the SHINT bit is set, the RSTOUT pin is the OR of the fast and normal interrupt signals.

1= Internal requests reflected on RSTOUT pin 0= Normal RSTOUT pin function

NOTE: The FRCRSTOUT function in the reset controller has a higher priority than the SHINT function.

USBENDIAN — USBCO Endian Select The USBENDIAN bit allows USBCO’ register to select big-endian or little-endian operation.

1= Big-Endian is selected. 0= Little-Endian is selected.

USI2PEN — USI2 Port Enable The USI2 bit is used to enable USI2 pad Table 4-6 USI Pin Functions).

1= USI2 pad is enable. 0= USI2 pad port is disable.

47


Table 4-6 USI Pin Functions

Pin Primary Function USI Pin

INT[3] INT[3](USI2PEN=0) ISORST2(USI2PEN=1)

INT[4] INT[4](USI2PEN=0) ISOCLK2(USI2PEN=1)

INT[5] INT[5](USI2PEN=0) ISODAT2(USI2PEN=1)

KPPEN[1:0] — Key Pad Port Enable The KPPEN bit is used to enable KPP pad(See Table 4-7 KPP Pin Functions).

1= Key pad port enable. 0= Key pad port disable.

Table 4-7 KPP Pin Functions Pin Primary Function KPP Pin

D[15:0] D[15] (KPPEN[0]=0) KR[15:0](KPPEN[0]=1)

EB[3:2] EB[3:2](KPPEN[0]=0) KR[17:16](KPPEN[0]=1)

FWP FWP(KPPEN[0]=0) KC[0](KPPEN[0]=1)

FALE FWP(KPPEN[0]=0) KC[1](KPPEN[0]=1)

FCLE FCLE(KPPEN[0]=0) KC[2](KPPEN[0]=1)

FWE FWE(KPPEN[0]=0) KC[3](KPPEN[0]=1)

FRE FRE(KPPEN[0]=0) KC[4](KPPEN[0]=1)

FCE[3:0] FCE[3:0](KPPEN[0]=0) KC[8:5](KPPEN[0]=1)

ISORST1 ISORST1(KPPEN[1]=0) KC[9](KPPEN[1]=1)

ISODAT1 ISODAT1(KPPEN[1]=0) KR[19](KPPEN[1]=1)

ISOCLK1 ISOCLK1(KPPEN[1]=0) KR[18](KPPEN[1]=1)

4.6.3.2 CIR — Chip Identification Register

The CIR register is a read-only register; writing to CIR has no effect. The chip’s ID and Revision number can be read in this register.

48


Address : 0x00c1_0006 and 0x00c1_0007

Bit15 14 13 12 11 10 9 Bit8

Read: PIN

Write:

RESET: 0 0 0 1 1 1 0 0

Bit7 6 5 4 3 2 1 Bit0

Read: PRN

Write:

RESET: 0 0 0 0 0 0 0 0


Figure 4- 2 CIR — Chip Identification Register

PIN[7:0] — Part Identification Number Field This read-only field contains a unique version identification number for the chip.

PRN[7:0] — Part Revision Number Field This read-only field contains the full-layer mask revision number. This number is increased by one for each new full-layer mask set of this part. The revision numbers are assigned in chronological order.

49


Section 5 Signal Description

5.1 Introduction

The TF32A09 is available in four types of package:

176-pin quad flat pack (QFP)



64-pin quad flat pack (LQFP)


5.2 Package Pinout Summary

Refer to:

Table 5-1 is a summary of the pinouts for the 176/100/80/64/48-pin QFP packages.

Figure 5-1 is a pinout diagram of the system.

Table 5-2 is a brief description of each signal. Table 5-1 176/100/80/64/48-pin Package Pinouts

Pin Number

Pad Name

Pin Number

Pad Name 176pin 100pin 80pin

64pi

n

48pi

n 176pin 100pin 80pin

64pi

n

48pi

n

1 100 1 64 48 ss1 90 50 Sub 33 Sub USBVSS2

2 vss 91 51 34 DP2

3 vss 92 52 35 DM2

4 vddh 93 53 41 36 26 USBVDD2

5 vddh 94 54 37 RREF2

6 1 2 1 1 int1 95 55 38 USBCAP2

7 2 3 fcle 96 56 39 VBUS2

8 vss 97 57 40 ID2

9 vddh 98 vss

50


10 3 4 2 fce3 99 58 42 41 27 mode3

11 trst 100 vss

12 4 5 3 2 int0 101 vddh

13 5 6 fale 102 txd2

14 de 103 rxd2

15 6 7 4 3 vss 104 59 43 d7

16 7 8 5 4 vddh 105 60 44 42 28 mode2

17 vdd 106 61 45 d6

18 8 9 6 fce2 107 test

19 tms 108 62 46 43 29 vss

20 9 10 fre 109 vss

21 tclk 110 63 47 44 30 vddh

22 10 11 7 fce1 111 vddh

23 11 vss 112 vdd

24 12 vddh 113 64 48 d5

25 13 12 8 5 fce0 114 eb1

26 tdo 115 65 49 d4

27 14 13 fwe 116 66 50 45 31 mode1

28 tdi 117 67 51 d3

29 15 a25 118 eb0

30 a0 119 68 52 d2

31 16 a24 120 69 53 46 32 clkout

32 vss 121 70 54

vss

33 vddh 122 vss

34 17 a23 123 71 55

vddh

35 vss 124 vddh

36 18 14 9 6 ID1 125 72 56 d1

37 19 15 10 7 VBUS1 126 73 57 47 33 mode0

38 20 16 11 8 USBCAP1 127 74 58 d0

39 21 17 12 9 RREF1 128 75 59 48 34 porout

51


40 22 18 13 10 USBVDD1 129 vss

41 23 19 14 11 DM1 130 vddh

42 24 20 15 12 DP1 131 76 60 49 35 por

43 25 21 16 13 USBVSS1 132 77 61 50 36 pllvddcap

44 26 a22 133 78 62 51 37 vss

45 27 22 17 14 sda 134 79 63 52 38 vddh

46 a1 135 80 64 53 39 vddcap

47 18 ss2 136 a16

48 28 a21 137 81 65 d15

49 cs0 138 a15

50 29 eb3 139 54 miso2

51 30 23 19 15 vss 140 a14

52 31 24 vddh 141 a13

53 32 25 20 16 sc1 142 82 66 d14

54 oe 143 83 67 55 40 rstout

55 d16 144 84 68 56 41 extal

56 33 26 isodat1 145 85 69 57 42 xtal

57 d24 146 a12

58 d17 147 86 70 58 43 miso1

59 34 27 21 17 int2 148 a11

60 d25 149 59 sck2

61 35 28 isoclk1 150 a10

62 d18 151 87 71 d13

63 22 mosi2 152 a9

64 d26 153 rw

65 36 29 23 18 int3 154 int6

66 d19 155 88 72 60 44 vddh

67 d27 156 89 73 61 45 vss

68 37 30 24 19 vss 157 90 74 d12

69 38 31 25 20 vddh 158 int7

52


70 d20 159 a18

71 d28 160 91 75 d11

72 39 32 26 21 int4 161 a8

73 d21 162 92 a19

74 40 33 isorst1 163 a7

75 d29 164 93 76 62 46 mosi1

76 41 eb2 165 a6

77 d22 166 94 77 d10

78 42 34 27 22 int5 167 vss

79 d30 168 95 vddh

80 43 cs1 169 a5

81 d23 170 96 78 d9

82 44 35 fwp 171 97 a20

83 d31 172 a4

84 45 36 28 23 vss 173 98 79 63 47 sck1

85 46 37 29 24 vddh 174 a3

86 a17 175 99 80 d8

87 47 38 30 txd1 176 a2

88 48 39 31 rxd1

89 49 40 32 25 pwmo

53


vssvss

vddhvddh

int1fclevss

vddhfce3trstint0falede

vssvddh

vddfce2tmsfre

tclkfce1vss

vddhfce0tdofwe

tdia25

a0a24vss

vddha23vssID1

VBUS1USBCAP1

RREF1USBVDD1

DM1DP1

vddhvssporoutd0mode0d1vddhvddhvssvssclkoutd2eb0d3mode1d4eb1d5vddvddhvddhvssvsstestd6mode2d7rxd2txd2vddhvssmode3vssID2VBUS2USBCAP2RREF2USBVDD2DM2DP2

a2 d8 a3 sck1

a4 a20

d9 a5 vddh

vss

d10

a6 mos

i1a7 a1

9a8 d1

1a1

8in

t7d1

2vs

svd

dhin

t6rw a9 d1

3a1

0sc

k2a1

1m

iso1

a12

xtal

exta

lrs

tout

d14

a13

a14

mis

o2a1

5d1

5a1

6vd

dcap

vddh

vss

USBVSS1 USBVSS2

por

sda a1 ss2

a21

cs0

eb3

vss

vddh sc

loe d16

isod

at1

d24

d17

int2

d25

isoc

lk1

d18

mos

i2d2

6in

t3d1

9d2

7vs

svd

dh d20

d28

int4

d2‘1

isor

st1

d29

eb2

d22

int5

d30

cs1

d23

fwp

d31

vss

vddh a17

txd1

rxd1

ss123456789

10111213141516171819202122232425262728293031323334353637383940414243

1

a22 44

46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 8745 88

pwmo

pllvddcap131130129128127126125124123122121120119118117116115114113112111110109108107106105104103102101100

99989796959493929190

132

89

175

174

173

172

171

170

169

168

167

166

165

164

163

162

161

160

159

158

157

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

176

133

vssvddhUSBVDDvdd (only for VR 1.8V test)

TF32A09

Figure 5- 1 176-Pin QFP Assignments

54


int1fcle

fce3int0falevss

vddhfce2

frefce1vss

vddhfce0fwea25a24a23ID1

VBUS1USBCAP1

RREF1USBVDD1

DM1DP1

poroutd0mode0d1vddhvssclkoutd2d3mode1d4d5vddhvssd6mode2d7mode3ID2VBUS2USBCARREF2USBVDD2DM2DP2

ss1

d8 sck1

a20

d9 vddh

d10

mos

i1a1

9d1

1d1

2vs

svd

dh

mis

o1xt

alex

tal

rsto

utd1

4d1

5vd

dcap

vddh

vss

USBVSS1

sda

a21

eb3

vss

vddh sc

lis

odat

1in

t2is

oclk

1in

t3vs

svd

dh int4

isor

st1

eb2

int5

cs1

fwp

vss

vddh

txd1

rxd1

pwm

o

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 4827 49

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78

vssvddhUSBVDD

a22

26

US

BV

SS

250

d13

por

pllv

ddca

p77 76

TF32A09


55


int1fcle

fce3int0

fale

vssvddh

fce2fre

fce1

fce0fwe

ID1

VBUS1USBCAP1

RREF1USBVDD1

DM1

DP1

porout

d0

mode0d1

vddhvss

clkout

d2d3

mode1d4

d5

vddhvss

d6mode2

d7

mode3USBVDD2

d8 sck1

d9 d10

mos

i1

d11

d12

vss

vddh

miso

1

xtal

exta

l

rsto

ut

d14

d15

vddc

ap

vddh

vss

sda

vss

vddh sc

l

isod

at1

int2

isocl

k1 int3 vss

vddh int4

isors

t1

int5

fwp

vss

vddh

txd1

rxd1

pwm

o

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 3922 40

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62

vssvddhUSBVDD

USBV

SS1

21

d13

pllv

ddca

p61

ss1 1 por

TF32A09


56


int1

fce3

int0

vss

vddh

fce2

fce1

fce0

ID1

VBUS1

USBCAP1

RREF1

USBVDD1

DM1

DP1

porout

mode0

clkout

vddh

vss

mode1

mode2

mode3

ID2

VBUS2

USBCAP2

RREF2

DM2

DP2

USBVDD2

ss1

sck1

mos

i1

vss

vddh

mis

o

xtal

exta

l

rsto

ut

mis

o2

vddc

ap

vddh

vss

sda

vss

scl

int2

mos

i2

int3

vss

vddh int4

int5

vss

vddh

txd1

rxd1

pwm

o

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

19 20 21 22 23 24 25 26 27 28 29 30 3118 32

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

64 63 62 61 60 59 58 57 56 55 54 53 52 51

vssvddhUSBVDD

17

sck2

pllv

ddca

p

49

1

USBVSS1

ss2

USBVSS250

por

TF32A09

Figure 5- 4 64-Pin LQFP Assignments

57


int1

int0

vss

vddh

fce0

ID1

VBUS1

USBCAP1

RREF1

USBVDD1

DM1

DP1

porout

mode0

clkout

vddh

vss

mode1

mode2

mode3

USBVDD2

ss1

sck1

mos

i1

vss

vddh

mis

o1

xtal

exta

l

rsto

ut

vddc

ap

vddh

vss

sda

vss

scl

int2

int3

vss

vddh int4

int5

vss

vddh

2

3

4

5

6

7

8

9

10

11

12

15 16 17 18 19 20 21 22 23 24

35

34

33

32

31

30

29

28

27

26

48 47 46 45 44 43 42 41 40 39 38 37

vssvddhUSBVDD

14

1

por

13U

SB

VS

S1

pwmo25

pllvddcap36

TF32A09


58


5.2.1 Signal Properties Summary

Table 5-2 Signal Description

Name3 Alternate Qty. Dir. Input

Sync.4 Pullup

5,6 Output Drive (ST/OD/SP)

7

Reset(3)

por – 1 I N Pullup -

poro – 1 O N - -

rstout – 1 O N - -

PLL and Clock(3)

extal – 1 I N SP

xtal – 1 O - SP

clkout – 1 O - ST

External Memory Interface, KPP and Ports(75)

d[31:24] PORTD[7:0] 8 I/O Y Pullup ST

d[23:16] PORTE[7:0] 8 I/O Y Pullup ST

d[15:0] KR[15:0] 16 I/O Y Pullup ST

rw PORTF[7] 1 O Y - ST

a[25] PORTF[4] 2 O Y - ST

a[24] PORTF[3] 2 O Y - ST

a[23:16] PORTA[7:0] 8 O Y - ST

a[15:8] PORTB[7:0] 8 O Y - ST

a[7:0] PORTC[7:0] 8 O Y - ST

3Shaded signals are for optional bond-out for more pin count package. 4Synchronized input used only if signal configured as a digital I/O. RESET signal is always

synchronized, except in low power stop mode. 5All pullups are disconnected when the signal is programmed as an output. 6All Not-Single-Chip I/O pins will be put into input mode and be connected to pullups. 7Output driver type: ST = standard, SP = special, OD = standard driver with open-drain pulldown

option selected.

59


eb[3:2] KR[17:16] 2 I/O Y - ST

eb[1:0] PORTF[6:5] 2 I/O Y - ST

cs[1:0] PORTF[1:0] 2 I/O Y - ST

oe PORTF[2] 1 O - - ST

fwp KC[0] 1 O Y Pullup OD

fale KC[1] 1 O Y Pullup ST

fcle KC[2] 1 O Y Pullup ST

fwe KC[3] 1 O Y Pullup ST

fre KC[4] 1 O - Pullup ST

fce[3:0] KC[8:5] 4 I/O Y Pullup ST

Serial Peripheral Interface(SPI1)(4)

mosi1 - 1 I/O Y Pullup ST/OD

miso1 - 1 I/O Y Pullup ST/OD

sck1 - 1 I/O Y Pullup ST/OD

ss1 - 1 I/O Y Pullup ST/OD

Serial Peripheral Interface 1 (SPI2)(4)

mosi2 - 1 I/O Y Pullup ST/OD

miso2 - 1 I/O Y Pullup ST/OD

sck2 - 1 I/O Y Pullup ST/OD

ss2 - 1 I/O Y Pullup ST/OD

Serial Communication Interface 1 (SCI1) (2)

txd1 - 1 I/O Y Pullup ST/OD


Serial Communication Interface 2 (SCI2) (2)


rxd2 - 1 I/O Y Pullup ST/OD

ISO-7816 Interface 1 (USI1) (4)

isoclk1 KR[18] 1 I/O Y Pullup ST/OD

60


isodat1 KR[19] 1 I/O Y Pullup ST/OD

isorst1 KC[9] 1 I/O Y Pullup ST/OD

Edge Port (EPORT), ISO-7816 Interface 2 (USI2) (8)

int[0] - 1 I/O N Pullup -



int[3] ISORST2 1 I/O N Pullup -

int[4] ISOCLK2 1 I/O N Pullup -

int[5] ISODAT2 1 I/O N Pullup -

int[6] NRFRESET 1 I/O N Pullup -

int[7] NRFRDBY 1 I/O N Pullup -

I2C (2)

sda - 1 I/O N Pullup ST/OD

scl - 1 I/O N Pullup ST/OD

PWM (1)

pwmo - 1 - N - ST

Universal Serial Bus 1 (USB 1) (8)

RREF1 - 1 - N - SP

DM1 - 1 I/O N - SP

DP1 - 1 I/O N - SP

ID1 - 1 - N - SP

VBUS1 - 1 I/O N - SP

USBVSS1 - 1 I/O N - SP

USBVDD1 - SP

USBVDDCAP1 - SP

Universal Serial Bus 2 (USB 2) (8)

RREF2 - 1 - N - SP

61


DM2 - 1 I/O N - SP

DP2 - 1 I/O N - SP

ID2 - 1 - N - SP

VBUS2 - 1 I/O N - SP

USBVSS2 - 1 I/O N - SP

USBVDD2 1 SP

USBVDDCAP2 1 SP

Debug Port (6)

trst - 1 I N Pullup -

tclk - 1 I N Pullup -

tms - 1 I N Pullup -

tdi - 1 I N Pullup -

tdo - 1 O - - ST

de - 1 I/O N Pullup OD

Test and Chip Configuration (5)

test - 1 I - Pulldown -

mode[3:0] - 4 I - Pullup -

Power Supply

vddh - - - - - SP

vss - - - - - -

vdd - - - - - -

vddcap - - - - - -

pllvddcap - - - - - -

62


5.3 Signal Descriptions

This subsection provides a brief description of the signals. For more detailed information, reference the specific module section.

5.3.1 Reset Signals

These signals are used to either reset the chip or as a reset indication.

5.3.1.1 Power-On Reset Output (poro)

This active-low signal is the output on internal the power on reset circuit.

5.3.1.2 Power-On Reset In ( por)

This active-low input signal is used as the external power-on reset. Power-on reset places the CPU in supervisor mode with default settings for all register bits.

5.3.1.3 Reset Out (rstout)

This active-low output signal is an indication that the internal reset controller has reset the chip.

63


5.3.2 Clock Signals

These signals are used to support the on-chip clock generation circuitry.

5.3.2.1 External Clock In (extal)

These signals are used to support the on-chip clock generation circuitry.

5.3.2.2 Crystal (xtal)

This output signal is used as a connection to drive an external crystal when the internal oscillator circuit is used.

xtal should be pull-downed by 50KΩ resistance when Using an external clock input on extal.

5.3.2.3 Clock Out (clkout)

This output signal reflects the internal system clock.

5.3.3 External Memory Interface, KPP and PORTS module Signals

5.3.3.1 Data Bus (d[31:16])

These signals provide the general-purpose data path between the microcontroller unit (MCU) and all other devices. They also work as PORTD and PORTE.

5.3.3.2 Data Bus (d[15:0])

These signals provide the general-purpose data path between the microcontroller unit (MCU) and all other devices. They also work as KR[15:0].

5.3.3.3 Read/Write (rw)

This output signal indicates the direction of the data transfer on the bus. A logic 1 indicates a read from a slave device and a logic 0 indicates a write to a slave device. It also works as PORTF[7].

5.3.3.4 Address Bus (a[25:0])

These output signals provide the address for the current bus transfer. a[25:0] also works as PORTF[4:3], PORTA, PORTB and PORTC.

64


5.3.3.5 Enable byte (eb[3:0])

These output signals indicate which byte of data is valid during external cycles. eb[1:0] is also used as PORTF[6:5] and eb[3:2] is also used as KR[3:2].

5.3.3.6 Chip Select (cs[1:0])

These output signals select external devices for external bus transactions and is used as PORTF[1:0].

5.3.3.7 Output Enable (oe)

This output signal indicates when an external device can drive data during external read cycles and is used as PORTF[2].

5.3.3.8 NANDFLASH Command Latch Enable (fcle)

This output signal is NANDFLASH Command Latch Enable and is used as KC[2].

5.3.3.9 NANDFLASH Address Latch Enable (fale)

This output signal is NANDFLASH Address Latch Enable and is used as KC[1].

5.3.3.10 NANDFLASH Write Enable (fwe)

This output signal is NANDFLASH Write Enable and is used as KC[3].

5.3.3.11 NANDFLASH Read Enable (fre)

This output signal is NANDFLASH Read Enable and is used as KC[4].

5.3.3.12 NANDFLASH Write Protect Enable (fwp)

This output signal is NANDFLASH Write Protect and is used as KC[0].

5.3.3.13 NANDFLASH Chip Select Enable (fce[3:0])

This GPIO signal woks as NANDFLASH Chip Select Enable and FCE[3:0] is also used as KC[8:5].

65


5.3.4 Edge Port Signals

5.3.4.1 int[7:0]

These bidirectional signals function as either external interrupt sources or GPIO. Also INT[7:6] woks as NORFLASH’s RDBY and RESET and INT[5:3] works as ISODAT3, ISOCLK2 and ISORST2.

5.3.5 Debug and Emulation Support Signals

These signals are used as the interface to the on-chip JTAG (Joint Test Action Group) controller and also to interface to the OnCE logic.

5.3.5.1 Test Reset (trst)

This active-low input signal is used to initialize the JTAG and OnCE logic asynchronously.

5.3.5.2 Test Clock (tclk)

This input signal is the test clock used to synchronize the JTAG and OnCE logic.

5.3.5.3 Test Mode Select (tms)

This input signal is used to sequence the JTAG state machine. tms is sampled on the rising edge of tclk.

5.3.5.4 Test Data Input (tdi)

This input signal is the serial input for test instructions and data. tdi is sampled on the rising edge of tclk.

5.3.5.5 Test Data Output (tdo)

This output signal is the serial output for test instructions and data. tdo is three-stateable and is actively driven in the shift-IR and shift-DR controller states. tdo changes on the falling edge of tclk.

5.3.5.6 Debug Event (de)

This is a bidirectional, active-low signal. As an output, this signal will be asserted for three system clocks, synchronous to the rising CLKOUT edge, to acknowledge that the CPU has entered debug mode as a result of a debug

66


request or a breakpoint condition. As an input, this signal provides multiple functions.

5.3.6 USB1 Signals

5.3.6.1 External reference (RREF1)

Connect 10Kohm External Reference resistor, with 1% tolerance to USBVSS33.

5.3.6.2 DP1

USB Data pin Data+

5.3.6.3 DM1

USB Data pin Data+

5.3.6.4 ID1

The ID signal is indicating the state of ID pin on the USB mini receptacle. This pin tie "0" means the PHY is HOST, tie "1" means the PHY is DEVICE.

5.3.6.5 VBUS1

VBUS pin on USB connector.

5.3.6.6 USBVDD1

Analog 3.3V Power.

5.3.6.7 USBVDDCAP1

It should be tie to a 4.7uF capacitor to USBVSS1

5.3.6.8 USBVSS1

Analog Ground.

67


5.3.7 Universal Serial Bus 2 (USB2) Signals

5.3.7.1 External reference (RREF2)

Connect 10Kohm External Reference resistor, with 1% tolerance to USBVSS33.

5.3.7.2 DP2

USB Data pin Data+

5.3.7.3 DM2

USB Data pin Data+

5.3.7.4 VBUS2

VBUS pin on USB connector.

5.3.7.5 ID2

The ID signal is indicating the state of ID pin on the USB mini receptacle. This pin tie "0" means the PHY is HOST, tie "1" means the PHY is DEVICE.

5.3.7.6 USBVDD2

Analog 3.3V Power.

5.3.7.7 USBVDDCAP2

It should be tie to a 4.7uF capacitor to USBVSS2.

5.3.7.8 USBVSS2

Analog Ground.

5.3.8 USI1 Signals

5.3.8.1 Smart Card Data Input/Output (isodat1)

This signal is used for Smart Card Interface data input/output and is also available for GPIO when not configured for UART mode. And it woks as KR[19].

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5.3.8.2 Smart Card Clock Signal (isoclk1)

This signal is used for Smart Card clock signal. It can also be selected as an system clock source. And it woks as KR[18].

5.3.8.3 Smart Card Reset Signal (isorst1)

This signal is used for Smart Card reset signal and is also available for GPIO. And it woks as KC[9].

5.3.9 Serial Peripheral Interface Module 1 (SPI1)

These signals are used by the SPI modules and may also be configured to be discrete I/O signals.

5.3.9.1 Master Out/Slave In (mosi1)

This signal is the serial data output from the SPI in master mode and the serial data input in slave mode.

5.3.9.2 Master In/Slave Out (miso1)

This signal is the serial data input to the SPI in master mode and the serial data output in slave mode.

5.3.9.3 Serial Clock (sck1)

The serial clock synchronizes data transmissions between master and slave devices. SCK is an output if the SPI is configured as a master. sck1 is an input if the SPI is configured as a slave.

5.3.9.4 Slave Select (ss1)

This I/O signal is the peripheral chip select signal in master mode and is an active-low slave select in slave mode.

5.3.10 Serial Peripheral Interface Module 2 Signals (SPI2)

These signals are used by the SPI modules and may also be configured to be discrete I/O signals.

5.3.10.1 Master Out/Slave In (mosi2)

This signal is the serial data output from the SPI in master mode and the serial data input in slave mode.

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5.3.10.2 Master In/Slave Out (miso2)

This signal is the serial data input to the SPI in master mode and the serial data output in slave mode.

5.3.10.3 Serial Clock (sck2)

The serial clock synchronizes data transmissions between master and slave devices. sck2 is an output if the SPI is configured as a master. sck2 is an input if the SPI is configured as a slave.

5.3.10.4 Slave Select (ss2)

This I/O signal is the peripheral chip select signal in master mode and is an active-low slave select in slave mode.

5.3.11 Serial Communications Interface 1 Module Signals (SCI1)

These signals are used by the SCI module.

5.3.11.1 Receive Data (rxd1)

This signal is used for the SCI receiver data input and is also available for GPIO when not configured for receiver operation.

5.3.11.2 Transmit Data (txd1)

This signal is used for the SCI transmitter data output and is also available for GPIO when not configured for transmitter operation.

5.3.12 Serial Communications Interface 2 (SCI2) Module Signals

These signals are used by the SCI module.

5.3.12.1 Receive Data (rxd2)

This signal is used for the SCI receiver data input and is also available for GPIO when not configured for receiver operation.

5.3.12.2 Transmit Data (txd2)

This signal is used for the SCI transmitter data output and is also available for GPIO when not configured for transmitter operation.

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5.3.13 Inter-Integrated Circuit Bus (I2C) Signals

These signals are used by I2C module.

5.3.13.1 sda

I2C data line.

5.3.13.2 scl

I2C clock line.

5.3.14 Pulse Width Modulator

5.3.14.1 pwmo

This signal is PWM output.

5.3.15 Test and Chip Configuration Signals

5.3.15.1 test

5.3.15.2 mode[3:0]

These signals are used for selecting the chip’s mode during reset configuration.

5.3.16 Power and Ground Signals

These signals provide system power and ground to the chip. Multiple signals are provided for adequate current capability. All power supply signals must have adequate bypass capacitance for high-frequency noise suppression.

5.3.16.1 vddh

This signal supplies 3.3V positive power to the I/O pads and Voltage Regulator (VR).

5.3.16.2 vss

This signal is the negative supply (ground) to the I/O pads and the core logic.

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5.3.16.3 vdd

This signal is output supply of 1.8V.

5.3.16.4 pllvddcap

PLL VR output signals. 4.7uF ceramic bypass capacitor is required to externally connect between PLLCAP and GND.

5.3.16.5 vddcap

VDD VR output signals. 4.7uF ceramic bypass capacitor is required to externally connect between PLLCAP and GND.

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Section 6 Reset Controller Module

6.1 Overview

The reset controller is provided to determine the cause of reset, assert the appropriate reset signals to the system, and then to keep a history of what caused the reset. The low-voltage detect (LVD) and high-voltage detect (HVD) control and status bits are implemented in the reset module.

6.2 Features

Module features include:

Five sources of reset:

- Power on reset

- Software

- Watchdog Timer Reset

- Low Voltage Detect Reset

- High Voltage Detect Reset

Software-assertable RSTOUT pin independent of chip reset state

Software-readable status flags indicating the cause of the last reset

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6.3 Block Diagram

Figure 6-1 illustrates the reset controller.

Reset

Controller

External External

POR

WDT Timeout

SOFTWARE RESET

RSTOUT

To INTERNAL RESETS

POR

Voltage Detect RESET

On Chip

To VD Signals

To PMM Signals

PORO

Figure 6- 1 Reset Controller Block Diagram

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6.4 Signals

Table 6-1 provides a summary of the reset controller signal properties. The signals are described in the following paragraphs.

Table 6-1 Reset Controller Signal Properties

Name Direction Input Hysteresis

Input Synchronization

PORO pin O — —

POR pin I Y N

RSTOUT pin O — —

6.4.1 PORO

The output of the internal power on reset circuit.

6.4.2 POR

Asserting the external POR pin will causes the system to reset immediately.

6.4.3 RSTOUT

This active-low output signal is driven low when the internal reset controller module resets the chip. When RSTOUT is active, the user can drive override options on the data bus.

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The reset controller programming model consists of these registers:

Reset Control Register (RCR) Selects reset controller functions

Reset Status Register (RSR) Reflects the state of the last reset source

See Table 6-2 for the address map and the following paragraphs for a description of the registers.

Table 6-2 Reset Controller Address Map

Address Bit [7:0] Access 8

0x00c4_0000

RCRH—Reset Control Register S/U

0x00c4_0001 RCRL—Reset Control Register S/U

0x00c4_0002 RSR—Reset Status Register S/U

0x00c4_0003 RTR—Reset Test Register S/U

8S/U = supervisor or user mode access.

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6.5.1 Reset Control Register

The Reset Control Register (RCR) allows software control for requesting a reset, for independently asserting the external RSTOUT pin, and for controlling voltage detect (VD) functions.

Address : 0x00c4_0000

15 14 13 12 11 10 9 8

R SOFTRST

FRCRSTO

UT LVCTR[1:0] LVDF LVDIE LVDRE LVDE

W

RESET: 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

R 0 0 HVCTR[1:0] HVDF HVDIE HVDRE HVDE

W

RESET: 0 0 0 0 0 0 0 0


Figure 6- 2 Reset Control Register (RCR)

NOTE:

Only Power-On Reset can reset LVCTR[1:0], HVCTR[1:0], LVDRE, LVDE, HVDRE, HVDE bits.

SOFTRST — Software Reset Request The SOFTRST bit allows software to request a reset. The reset caused by setting this bit clears this bit.

1= Software reset request. 0= No software reset request.

FRCRSTOUT— Force RSTOUT Pin The FRCRSTOUT bit allows software to assert or negate the external RSTOUT pin.

1= Assert RSTOUT pin 0= Negate RSTOUT pin

LVCTR[1:0] — Low-Voltage Detect Triming Bits

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HVCTR[1:0] — High-Voltage Detect Trimming Bits

The trigger points and trimming bits relations are given in Table 6-3 and Table 6-4.

LVDF — LVD Flag The LVDF bit indicates the low-voltage detect status if LVDE is set. Write a 1 to clear the LVDF bit.

1= Low voltage has been detected. 0= Low voltage has not been detected.

NOTE:

The setting of this flag causes an LVD interrupt if LVDE and LVDIE bits are set and LVDRE is cleared when the analog supply voltage AVDD drops below VDD

(minimum).

LVDIE — LVD Interrupt Enable The LVDIE bit controls the LVD interrupt if LVDE is set. This bit has no effect if the LVDE bit is a logic 0.

1= LVD interrupt enabled 0= LVD interrupt disabled

Table 6-3 LVD Trimming Bits and Trigger Point Relationship

lvctr[1:0] Trigger Point Recover Point

00 2.35 ?

01 2.49 ?

00 2.65 ?

01 2.83 ?

Table 6-4 HVD Trimming Bits and Trigger Point Relationship

hvctr[1:0] Trigger Point Recover Point

00 4.09 ?

01 3.90 ?

00 3.72 ?

01 3.56 ?

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LVDRE — LVD Reset Enable The LVDRE bit controls the LVD reset if LVDE is set. This bit has no effect if the LVDE bit is a logic 0. LVD reset has priority over LVD interrupt, if both are enabled.

1= LVD reset enabled 0= LVD reset disabled

LVDE — LVD Enable The LVDE bit controls whether the LVD is enabled.

1= LVD is enabled 0= LVD is disabled

HVDF — HVD Flag The HVDF bit indicates the high-voltage detect status if HVDE is set. Write a 1 to clear the HVDF bit.

1= High voltage has been detected. 0= High voltage has not been detected.

NOTE:

The setting of this flag causes an HVD interrupt if HVDE and HVDIE bits are set and HVDRE is cleared when the analog supply voltage AVDD rise above VDD (maximum).

HVDIE — HVD Interrupt Enable The HVDIE bit controls the HVD interrupt if HVDE is set. This bit has no effect if the HVDE bit is a logic 0.

1= HVD interrupt enabled 0= HVD interrupt disabled

HVDRE — HVD Reset Enable The HVDRE bit controls the HVD reset if HVDE is set. This bit has no effect if the HVDE bit is a logic 0. HVD reset has priority over HVD interrupt., if both are enabled.

1= HVD reset enabled 0= HVD reset disabled

HVDE — HVD Enable The HVDE bit controls whether the HVD is enabled.

1= HVD is enabled 0= HVD is disabled

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6.5.2 Reset Status Register

The Reset Status Register (RSR) contains a status bit for every reset source. When reset is entered, the cause of the reset condition is latched along with a value of 0 for the other reset sources that were not pending at the time of the reset condition. These values are then reflected in RSR. One or more status bits may be set at the same time. The cause of any subsequent reset is also recorded in the register, overwriting status from the previous reset condition.

RSR can be read at any time. Writing to RSR has no effect.

Address: 0x00c4_0002

7 6 5 4 3 2 1 0

R 0 VD SOFT WDR POR EXT 0 0

W

RESET: 0 Reset Dependant


Figure 6- 3 Reset Status Register (RSR)

VD — Voltage Detect This bit indicates that the last reset state was caused by an VD reset.

1= Last reset state was caused by an VD reset 0= Last reset state was not caused by an VD reset

SOFT — Software Reset Flag This bit indicates that the last reset state was caused by software.

1= Last reset state was caused by software. 0= Last reset state was not caused by software.

WDR — Watchdog Timer Reset Flag This bit indicates that the last reset state was caused by a watchdog timer time-out.

1= Last reset state was caused by watchdog timer time-out. 0= Last reset state was not caused by watchdog timer time-out.

POR — External Power-On Reset Flag

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This bit indicates that the last reset state was caused by a external power-on reset.

1= Last reset state was caused by power-on reset. 0= Last reset state was not caused by power-on reset.

EXT — External Reset Flag This bit indicates that the last reset state was caused by an external device asserting the external LRESET pin.

1= Last reset state was caused by external reset. 0= Last reset state was not caused by external reset.

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6.5.3 Reset Test Register

The Reset Test Register (RTR) is only for factory testing and is read-only when not in test mode.


7 6 5 4 3 2 1 0

R FPOR

0 0 0 VDBGE LVDTME HVDTME

0

W

RESET: 0 0 0 0 1 0 0 0


Figure 6- 4 Reset Test Register (RTR)

FPOR — Force Power On Reset Write the bit will result in stem power on reset.

VDBGE — VD Bandage Enabled The VDBGE bit enables VD comparator. LVDE and HVDE should not be set until the comparator has been enabled for 30us.

1= VD Bandage Enabled. 0= VD Bandage Disabled.

LVDTME — Low-Voltage Detect Test Mode Enabled The LVDTME bit enable LVD test mode.

1= LVD in test mode. 0= LVD in normal mode.

HVDTME — High-Voltage Detect Test Mode Enabled The HVDTME bit enable HVD test mode.

1= HVD in test mode. 0= HVD in normal mode.

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6.6 Functional Description

6.6.1 Reset Sources

Table 6-5 defines the sources of reset and the signals driven by the reset controller.

Table 6-5 Reset Source Summary

Source Type

POR pin Asynchronous

Watchdog timer Synchronous

Software Synchronous

HVD Aynchronous

LVD Aynchronous

Table 6- 1

To protect data integrity, a synchronous reset source is not acted upon by the reset control logic until the end of the current bus cycle. Reset is then asserted on the next rising edge of the system clock after the cycle is terminated. Whenever the reset control logic must synchronize reset to the end of the bus cycle, the internal bus monitor is automatically enabled regardless of the BME bit state in the chip configuration module CCR register. Then, if the current bus cycle is not terminated normally the bus monitor terminates the cycle based on the length of time programmed in the BMT field of the CCR register.

Internal single- byte, half-word, or word writes are guaranteed to complete without data corruption when a synchronous reset occurs. External writes, including word writes to 16-bit ports, are also guaranteed to complete.

Asynchronous reset sources usually indicate a catastrophic failure. Therefore, the reset control logic does not wait for the current bus cycle to complete. Reset is asserted immediately to the system.

6.6.1.1 Power-On Reset (POR pin)

At power up, the reset controller asserts RSTOUT. RSTOUT continues to be asserted until POR has reached a minimum acceptable level. Then after approximately another 8192 cycles, RSTOUT is negated and the part begins operation.

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6.6.1.2 Watchdog Timer Reset

A watchdog timer timeout causes timer reset request to be recognized and latched. The bus monitor is enabled and the current busy cycle is completed. If the LRESET pin is negated, the reset controller asserts RSTOUT for approximately 8192 cycles. Then the part exits reset and begins operation.

6.6.1.3 Software Reset

A software reset occurs when the SOFTRST bit is set. If the RESET pin is negated, the reset controller asserts RSTOUT for approximately 8192 cycles. Then the part exits reset and resumes operation.

6.6.1.4 Voltage Detect Reset

A voltage detect reset occurs when the VDD exceeds the VD module allowed range. VD module can be disabled by clearing LVDE and HVDE bits.

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6.6.2 Reset Control Flow

The reset logic control flow is shown in Figure 6-5. All cycle counts given are approximate.

NEGATE RSTOUT

N

ENABLE BUS MONITOR

ASSERT RSTOUT ANDLATCH RESET STATUS

ASSERT RSTOUT ANDLATCH RESET STATUS

POR or LVD

N

Y

RESET NEGATED?N

WAIT 8192 CLKOUT CYCLES

Y

Y

Y

N

BUS CYCLECOMPLETE?

RCON ASSERTED ? WAIT 8192 CLKOUT CYCLES

WDT TIMEOUTor SW RESET?

Figure 6- 5 Reset Control Flow

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Section 7 Clock Module

7.1 Overview

The clock module contains:

Crystal oscillator (OSC)

Phase-lock loop (PLL)

Divide two frequency circuit

Status and control registers

Control logic

To improve noise immunity, the PLL has its own power supply pins. All other circuits are powered by the normal external supply pins.

7.2 Features

Features of the clock module include:

Only clock sources selectable

- external 12MHz crystal

Support for low-power mode

Separate clock out signal

Modules can be separately stopped by setting MSCR


The clock module can be operated in PLL mode or external clock mode.

7.3.1 Normal PLL Mode

In normal PLL mode, system clock is provided by the PLL clock which will be divided by two and the PLL is fully programmable. It can synthesize frequencies at the listed ratio (in Table 7-8) of the reference frequency. The PLL reference can be either a crystal oscillator or an external clock.

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7.3.2 External Clock Mode

In external clock mode, the PLL is bypassed and system clock is provided by EXTAL which will be divided by two.

7.3.3 Low-Power Options

7.3.3.1 Wait and Doze Modes

In wait and doze modes, the system clocks to the peripherals and embedded-flash are enabled, the clocks to the CPU, ROM, SRAM are stopped. Each module can disable the module clocks locally at the module level or by setting MSCR.

7.3.3.2 Stop Mode

In stop mode, all system clocks are disabled. The PLL can be disabled in stop mode. If so, at the moment of entering stop mode, the system clock will be switched to bypass clock. After wakeup, it requires a recovery period to switch the system clock from bypass clock to PLL clock. The recovery period equals bypass clock period multiplies 214.

In external clock mode, there are no recovery periods for PLL lock.

CAUTION: Don’t program or erase TSMC flash during stop mode. (Nonsense to SMIC Version)

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7.4 Block Diagram

EXTALXTAL

Oscillator Pins PLL

CLKOUT

/(1+k)

VDDA VSSA RSTOUT

System Clock

PLL Clock OutPLL Clock In

PLLEN

MD[1:0]

ND[4:0]

OD[1:0]

Internal Clock2DIV2

Figure 7-1 Clock Module Block Diagram

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The clock module signals are summarized in Table 7-1 and a brief description follows.


Name Function

EXTAL Oscillator or clock input

XTAL Oscillator output

CLKOUT System clock output

7.5.1 EXTAL

This input is driven by an external clock.

7.5.2 XTAL

This output is an internal oscillator connection to the external crystal.

7.5.3 CLKOUT

This output reflects the internal system clock.

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The clock programming model consists of these registers:

Synthesizer control register (SYNCR) — Defines clock operation

Synthesizer status register (SYNSR) — Defines clock status

Synthesizer test register (SYNTR) — Used for factory test

Module stop control register (MSCR) — Controls the modules’ clock separately

7.6.1 Module Memory Map

Clock Module Memory Map Address Bits 15-8 Bits 7-0 Access

0x00c3_0000 Synthesizer Control Register High (SYNCRH) S

0x00c3_0002 Synthesizer Control Register Low (SYNCRL) S

0x00c3_0004 Synthesizer Status Register (SYNSR) Synthesizer Test Register (SYNTR) S

0x00c3_0006 Reserved S

0x00c3_0008 Module Stop Control Register (MSCRH) S

0x00c3_000A Module Stop Control Register (MSCRL) S

S = CPU supervisor mode access only.

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7.6.2 Register Description

This subsection provides a description of the clock module registers.

7.6.2.1 Synthesizer Control Register

The synthesizer control register (SYNCR) is read/write always.

Register address : 0x00c3_0000 and 0x00c3_0003

31 30 29 28 27 26 25 24

R OD[3:0]

0 0 0 MFD[8]

W

RESET: 0 0 1 1 0 0 0 0

23 22 21 20 19 18 17 16

R MFD[7:0]

W

RESET: 0 0 1 0 0 1 1 0

15 14 13 12 11 10 9 8

R 0 0 0 RFD[4:0]

W

RESET: 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

R USBSTPE

N DISCLK

0 0 STPMD[1:0]

0 PLLEN

W

RESET: 0 0 0 0 0 0 0 0


Figure 7-2 Synthesizer Control Register (SYNCR)

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NOTE:

OD[3:0], MFD[8:0] , RFD[4:0] and PLLSEL, PLLEN bits can only be reset by Power-On Reset.

MFD [8:0] — Multiplication Factor Divider Field MFD[4:0] contain the binary value of the divider in the PLL loop. The MFD[8:0] value is the multiplication factor applied to the reference frequency. When the MFD value is changed or PLL is disabled in stop mode, the PLL loses lock. In external clock mode, the MFD[8:0] bits have no effect.

RFD[4:0] — Reduced Frequency Divider Field The binary value written to RFD[4:0] is the reference frequency divider pre-loop. It is the reduced frequency factor applied to the reference frequency. When RFD[4:0] are changed, the PLL loses lock. In external clock mode, the RFD[4:0] bits have no effect.

OD[3:0] — Output Divider Field OD[3:0] are the output divider control bits. When OD[3:0] are changed, the PLL loses lock. In external clock mode, the OD[3:0] bits have no effect.

DISCLK — Disable CLKOUT Bit The DISCLK bit determines whether CLKOUT is driven. Setting the DISCLK bit holds CLKOUT low.

1= CLKOUT disable 0= CLKOUT enable

USBSTPEN — USB Stop Mode Enable The USBSTPEN bit determines whether USB enter low power mode in stop mode if SUSPEN status is asserted.

1= USB will enter low power mode in stop mode if SUSPEN status is asserted.

0= USB will not enter low power mode in stop mode

STPMD[1:0] — Stop Mode Bits STPMD[1:0] control PLL and CLKOUT operation in stop mode as shown in Table 7-3.

Table 7-3 STPMD[1:0] Operation in Stop Mode

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STPMD[1:0] Operation During Stop Mode

System Clocks

PLL OSC CLKOUT

00 Disabled Enabled Enabled Enable

01 Disabled Enabled Enabled Disabled

10 Disabled Disabled Enabled Disabled

11 Disabled Disabled Disabled Disabled

PLLEN — PLL Enable Bit The PLLEN bit is used to select the clock mode. Table 1-4 shows the system clock source in the different modes. When PLLEN is set, the internal PLL and the loss-of-lock counter is enabled. And when the PLL is locked, the clock source will be changed to internal PLL clock out. When PLLEN is cleared, the PLL will enter low-power mode and loss lock.

1= PLL clock mode 0= External clock mode

Table 7-4 System Clock Source PLLEN Clock Source

0 From Bypass Clock EXTAL

1 From Internal PLL

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7.6.2.2 Synthesizer Status Register

The synthesizer status register (SYNSR) is a read-only register that can be read at any time. Writing to the SYNSR has no effect and terminates the cycle normally.


Bit 7 6 5 4 3 2 1 Bit 0

Read 0 0 0 0 LOCK 0 0 0

Write

Reset 0 0 0 0 09 0 0 0


Figure 7-3 Synthesizer Status Register (SYNSR)

LOCK — PLL LOCK Flag The LOCK flag is set when the PLL is locked. The lock sequence is controlled by an internal counter. If operating in external clock mode, LOCK remains cleared after reset.

1= PLL locked 0= PLL not locked

9Only be reset by Power-On Reset.

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7.6.2.3 Synthesizer Test Register

The synthesizer test register (SYNTR) is only for factory testing. When not in test mode, SYNTR is read-only.


Bit 7 6 5 4 3 2 1 Bit 0

Read PLLTM

0 0 0 0 0 0 STMS[0]

Write

Reset 0 0 0 0 0 0 0 0


Figure 7-4 Synthesize Test Register (SYNTR)

Table 7-5 Clock Module Test Modes

No.

Test Item PLLTM STMS[0] Description

0 CLKGEN Test 1 0

(1) When PLLEN is set, the behavior of CLKGEN Test mode is as same as normal pll mode except pll_clk source. (2) pll_clk is muxed to ipp_ind_tclk (3) lock_cntr is cutted to 4bits counter to shorten relock time. (4) The test is focused on clkgen’s muxb and muxg blocks. (5) In this mode, pll is disabled.

1 SMIC PLL

Test 1 1

(1) clkout pin is muxed to pll fout. (2) The pll reference clock is from ipp_ind_sdclk

Table 7-6 SMIC PLL Test Items

No. Test Items Action

1 PLL Frequency Test Test clkout frequency with changing ipp_ind_sdclk frequency, mfd,rfd values and od value.

2 Jitter Test Test clkout jitter

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3 Power Dissipation Test Test power dissipation (through check PLLVDD33 and PLLVSS) with setting the pll clk_out to a high frequency

4 PLL_A power dissipation in

power down mode

(1) The xin is still from ipp_ind_sdclk, but don’t add clock to sdclk. (2) pll_pd is set to 1(set pll_en to 0) (3) Read Idd from PLLVDD33 to PLLVSS.

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7.6.2.4 Module Stop Control Register

The Module Stop Control Register (MSCR) is read/write always.

Address : 0x00c3_0008 through 0x00c3_000b

31 30 29 28 27 26 25 24

R MS[31] MS[30] MS[29] MS[28] MS[27] MS[26] MS[25] MS[24]

W

RESET: 0 0 0 0 0 0 0 0

23 22 21 20 19 18 17 16


W

RESET: 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8


W

RESET: 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0


W

RESET: 0 0 0 0 0 0 0 0


Figure 7-5 Module Stop Control Register (MSCR)

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MS[31:0] — Module Stop Bits The MS[31:0] bits disable the modules’ clocks in the top level. (see Table 7-7 MS[31:0] Bits Corresponding Modules).

1= Module Clock Disabled 0= Module Clock Enabled

Table 7-7 MS[31:0] Bits Corresponding Modules MS Bit Corresponding Module

0 SCI1

1 SCI2

2 SPI1

3 SPI2

4 ISO7816_1

5 ISO7816_2

6 USBC1

7 USBC2

8 WDT

9 RSA

10 DES

11 SM1

12 I2C

13 PWM

14 PORTS

15 ECC

16 EPORT

17 ENCR

18 SMS4

19 DMAC

20 PIT1

21 PIT2

22 FIFOW

23 TRNG

24 KPP

25~31 reserved

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7.7 Function Description

This subsection provides a functional description of the clock module.

7.7.1 System Clock Generation

The system clock source is determined by PLLEN bit. Whenever PLLEN is changed, an immediate loss of lock condition occurs.

Table 7-8 shows the clock-out frequency to clock-in frequency relationships for possible clock modes.

Table 7-8 Clock-Out and Clock-In Relationships

Clock Mode PLL Operation1,2,3,4

Normal PLL clock mode fsys=(fref*NF)/(NR*NO)

External clock mode fsys=fref

1. fref = input reference frequency fsys = CLKOUT frequency

2. NF = 256*MFD[8] + 128*MFD[7] + 64*MFD[6] + 32*MFD[5] + 16*MFD[4] + 8*MFD[3] + 4*MFD[2] +

2*MFD[1] + MFD[0] + 2

3. NR = 16*RFD[4] + 8*RFD[3] + 4*RFD[2] + 2*RFD[1] + RFD[0] + 2

4. See Table 1-9 for NO value calculation.

Table 7-9 Output Divider Value (NO) OD[3] OD[2] OD[1] OD[0] NO

0 0 0 0 1

0 0 0 1 2

0 0 1 0 2

0 0 1 1 4

0 1 0 0 2

0 1 0 1 4

0 1 1 0 4

0 1 1 1 8

1 0 0 0 2

1 0 0 1 4

1 0 1 0 4

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1 0 1 1 8

1 1 0 0 4

1 1 0 1 8

1 1 1 0 8

1 1 1 1 16

NOTE:

When OD[3] = 1 ,OD[2] = 1 or OD[1:0] = 11, PLL clock out would have around 50% duty-cycle (Preferred).

CAUTION: The following constrains must be followed in PLL clock mode.

800KHz < fref/(NR*2) < 8MHz

3.2MHz < fref < 150MHz

200MHz < fvco < 500MHz, fvco > 250MHz is preferred. Where

fvco = (fref*NF)/(NR)

NOTE:

Keep the maximum system clock frequency below the limit given in the Appendix A Preliminary Electrical Characteristic.

7.7.2 PLL Relock Counter

PLL relock counter is a 14-bit counter Using bypass clock source (EXTAL). It will be reset when a loss of lock condition occurs. (see 7.7.2.1 PLL Loss of Lock Conditions) and then start counting. When the counter count-down to zero, the LOCK flag will be set. The count-down period will ensure the relock time for PLL.

In external clock mode, the PLL is disabled and the PLL Relock Counter doesn’t operate.

7.7.2.1 PLL Loss of Lock Conditions

Once the PLL relock counter count-down to zero after PLLEN bit is set, the LOCK flag is set.

If the MFD, RFD or OD are changed, the LOCK flag is negated. While the PLL is in the non-locked condition, the system clocks are to be sourced from the by-pass clock as the PLL attempts to relock.

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If the PLL is intentionally disabled during stop mode, the LOCK flag is negated and the Relock Counter operates after exit from stop mode.

7.8 Reset

Reset initializes the clock module registers to a known startup state as described in 7.7 Function Description.

7.9 Interrupts

The clock modules does not generate interrupt requests.

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Section 8 Memory Integration Module

8.1 Introduction

The memory integration module is responsible for controlling the transfer of the information between the internal C*CORE local bus and the internal or external asynchronous memory or memory-mapped modules. Up to three asynchronous chip select channels are available, two select signals (CS0, CS1) for the external memory, one (NFCS) for the external NANDFLASH.

8.2 Features

Features of the memory integration module include:

Reduced system complexity — No external glue logic required for typical systems if chip selects are used.

Three programmable asynchronous active-low chip selects can be independently programmed with various features.

Control for external boot device — CS0 can be selected as an external 16bit boot device when in master mode.

Fixed base addresses with 64M byte block sizes.

Support for 8-bit 16-bit and 32-bit devices — The port size can be programmed to be 8,16 or 32 bits.

Programmable write protection — Each chip select address range can be designated for read access only.

Programmable access protection — Each chip select address range can be designated for supervisor access only.

Write-enable selection — The enable byte pins (EB[3:0]) can be configured as byte enables (assert on both external read and write accesses) or write enables (only assert on external write accesses).

Bus cycle termination — The chip select logic to terminate the bus cycle.

Programmable wait states — To interface with various devices, up to seven wait states can be programmed before the access is terminated.

Programmable extra wait state for write accesses — One wait state can be added to write accesses to allow writing to memories that require additional data setup time.

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8.3 Signal Description

Table 8-1 provides an overview of the signals described here.


Port Name Function Pullup

D[31:16]/FIO[15:0] Data bus —

D[15:0]/FIO[31:16] Data bus —

R/W Read/Write Active

A[25:0] Address bus Active

EB[3:0] Enable byte Active

CS[1:0] Chip selects Active

OE Output enable —

FWE NANDFLASH Write Enable —

FRE NANDFLASH Read Enable —

FALE NANDFLASH Address Latch Enable —

FCLE NANDFLASH Command Latch Enable —

NOTE: NANDFLASH R/B signal can be connected to EPORT.

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8.4 Module Memory Map

Table 8-2 shows the MIM register memory map.

Table 8-2 Register Memory Map

Address Bits 31-16 Bits 15-0 Access10,11

0x00c2_0000

CSCR0 — Chip Select Control Register 0 S

0x00c2_0004 CSCR1 — Chip Select Control Register 1 S

0x00c2_0008 NFCSCR — NANDFLASH Chip Select Control Register S

0x00c2_000c NPCR — NANDFLASH Ports Control Register S

10S = CPU supervisor mode access only.

11User mode accesses to supervisor-only address locations have no effect and result in a cycle

termination transfer error.

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8.5 Register Descriptions

8.5.1 Chip Select Control Registers

The chip programming model consists of following Chip Select Control Registers: CSCR0, CSCR1, NCSCR. CSCR0 and CSCR1 define the conditions for asserting the chip select signals of external memory. NCSCR defines the condition for asserting the external NANDFLASH signals.

The reset value of PS[1:0] is "10", which means when CS0 is enabled at reset to emulate the internal memory, only the 16-bit port size external boot device will be allowed.


31 30 29 28 27 26 25 24

R 0 WATS[2:0]

0 WNTS[2:0]

W

RESET: 0 0 0 0 0 0 0 0

23 22 21 20 19 18 17 16

R 0 RATS[2:0]

0 0 0 0

W

RESET: 0 0 0 1 0 0 0 0

15 14 13 12 11 10 9 8

R SO RO PS[1:0] WS3 WS2 WS1 WS0

W

RESET: 0 0 1 0 0 1 1 1

7 6 5 4 3 2 1 0

R 0 0 0 0 0 WE WWS CSEN

W

RESET: 0 0 0 0 0 0 1 See note12


Figure 8-1 Chip Select Control Register 0(CSCR0)

12Reset state determined during reset configuration.

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31 30 29 28 27 26 25 24

R 0 WATS[2:0]

0 WNTS[2:0]

W

RESET: 0 0 0 1 0 0 0 1

23 22 21 20 19 18 17 16

R 0 RATS[2:0]

0 0 0 0

W

RESET: 0 0 0 1 0 0 0 0

15 14 13 12 11 10 9 8

R SO RO PS[1:0] WS3 WS2 WS1 WS0

W

RESET: 0 0 1 0 0 1 1 1

7 6 5 4 3 2 1 0

R 0 0 0 0 0 WE WWS CSEN

W

RESET: 0 0 0 0 0 1 1 0


Figure 8-2 Chip Select Control Register 1(CSCR1)

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Register address : 0x00c2_0008 and 0x00c2_000b

31 30 29 28 27 26 25 24

R 0 WATS[2:0]

0 WNTS[2:0]

W

RESET: 0 0 0 1 0 0 0 1

23 22 21 20 19 18 17 16

R 0 RATS[2:0]

0 0 0 RINV

W

RESET: 0 0 0 1 0 0 0 0

15 14 13 12 11 10 9 8

R SO

0 PS[1:0] WS3 WS2 WS1 WS0

W

RESET: 0 0 0 1 0 1 1 1

7 6 5 4 3 2 1 0

R PULLUPEN[3:0] ENDIAN

0 WWS CSEN

W

RESET: 0 0 0 0 0 0 1 0


Figure 8-3 NANDFLASH Chip Select Control Register (NFCSCR)

WATS[2:0] — Write Signal Assert Timing Select These bits select the assertion timing of EFWE, FWE, EB when the operation is "write". See functional description for details.

WNTS[2:0] — Write Signal Negate Timing Select These bits select the negation timing of EFWE, FWE, EB when the operation is "write". See functional description for details.

RATS[2:0] — Read Assert Timing Select These bits select the assertion timing of EFOE, EB, OE, FRE when the operation is "read". See functional description for details.

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RINV— Inversed Waveform of FRE The bit selects the inversed waveform of FRE when the operation is "read". See functional description for details.

FRE waveform is not inversed. FRE waveform is inversed.

PULLUPEN[3:0] — Pull Up Enable Bit These bits enable D[31:0] pull up status.

Table 8-3 D[31:0] Pull Up Enable Enable Bit Pull Up byte

PULLUPEN[0] = 1 D[31:24]

PULLUPEN[1] = 1 D[23:16]

PULLUPEN[2] = 1 D[15:8]

PULLUPEN[3] = 1 D[7:0]

ENDIAN — IO Endian Select Bit These bits select the endian of IO.

1= IO is little endian. 0= IO is big endian.

SO — Supervisor-Only Bit The SO bit restricts user mode access to the address range defined by the corresponding chip select. If the SO bit is 1, only supervisor mode access is permitted. If the SO bit is 0, both supervisor and user level accesses are permitted.

1= Only supervisor mode accesses allowed; user mode accesses ignored by chip select logic.

0= Supervisor and user mode accesses allowed.

RO — Read-Only Bit The RO bit restricts write accesses to the address range defined by the corresponding chip select. If the RO bit is 1, only read access is permitted. if the RO bit is 0, both read and write accesses are permitted.

1= Only read accesses allowed: write accesses ignored by the chip select logic.

0= Read and write accesses allowed.

PS[1:0] — Port Size Bits

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The PS bit defines the width of the external data port size supported by the chip.

00= 32 bit port 10= 16 bit port 01= 8 bit port 11= Not supported, will lead to an unpredictable error

WE — Write Enable Bit When EB[3:0] bits are asserted, WE bit assert write or byte enable.

EB[3:0] configured as write enables EB[3:0] configured as byte enables

NOTE: The WE bit has no effect on the EB[3:0] pin function if the chip select is not active. If the chip select is not active, the EB[3:0] pin function is byte enable by default.

WS[3:0] — Wait States Field The WS field determines the number of wait states for the chip select logic to insert before asserting the internal cycle termination signal. One wait state is equal to one system clock cycle. If WS is configured for zero wait states, then the internal cycle termination signal is asserted in the clock cycle following the start of the cycle access, resulting in one-clock transfers. A WS configured for one wait state means that the internal cycle termination signal is asserted two clock cycles after the start of the cycle access. Since the internal cycle termination signal is asserted internally after the programmed number of wait states, software can adjust the bus timing to accommodate the access speed of the external device. With up to seven possible wait states, even slow devices can be interfaced with the MCU.

Table 8-4 Chip Select Wait States Encoding

WS[3:0]

Number of Wait States

WWS = 0 WWS = 1

Read Access Write Access Read Access Write Access

0000 0 0 0 1

0001 1 1 1 2

0010 2 2 2 3

0011 3 3 3 4

0100 4 4 4 5

0101 5 5 5 6

0110 6 6 6 7

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0111 7 7 7 8

1000 8 8 8 9

1001 9 9 9 10

1010 10 10 10 11

1011 11 11 11 12

1100 12 12 12 13

1101 13 13 13 14

1110 14 14 14 15

1111 15 15 15 16

WWS — Write Wait State Bit The WWS bit determines if an additional wait state is required for write cycles. WWS does not affect read cycles.

1= One additional wait state added for write cycles. 0= No additional wait state added for write cycles.

CSEN — Chip Select Enable Bit The CSEN bit enables the chip select logic. When the chip select function is disabled, the CSx signal is negated high.

1= Chip select function enabled. 0= Chip select function disabled.

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8.5.2 NANDFLASH Ports Control Register

Register address : 0x00c2_000c and 0x00c2_000f

31 30 29 28 27 26 25 24

R 0 0 0 0 0 0 0 FWPDIR

W

RESET: 0 0 0 0 0 0 0 0

23 22 21 20 19 18 17 16

R 0 0 0 0 0 0 0 FWP

W

RESET: 0 0 0 0 0 0 0 1

15 14 13 12 11 10 9 8

R 0 0 0 0 FCEDIR[3:0]

W

RESET: 1 1 1 1 1 1 1 1

7 6 5 4 3 2 1 0

R 0 0 0 0 FCE[3:0]

W

RESET: 1 1 1 1 1 1 1 1


Figure 8-4 NANDFLASH Ports Control Register (NPCR)

FWPDIR — FWP Pin’s Direction FWPDIR bit determines the direction of FWP pins.

1= FWP is output 0= FWP is input

FWP — NANDFLASH Write-Protect

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FWP bit determines the output data of FWP pin. Reading this bit reflects the status of FWP pin. When NANDFLASH is write-protected, writing to NANDFLASH’s channels will result a transfer-error exception.

1= FWP is "1" , Write-Protect disabeld 0= FWP is "0" , Write-Protect enabled

FCEDIR[3:0] — FCE Pin’s Direction FCEDIR bits determine the direction of FCE pins.

1= FCE is output 0= FCE is input

FCE[3:0] — FCE Port Register FCE bits determine the output data of FCE[7:0] pin. Reading these bits reflects the status of FCE[7:0] pins.


8.6.1 Write Signal Timing

Write Enable ( FWE EB) provides a write enable signal for updating memory content. And the assert and negate timing can be configured flexibly.

Table 8-6 Write Assert and Negate Timing (Unit : system cycle) WATS[2:0] Assert Time (Twass) WNTS[2:0] Negate Time (Twneg)

000 1/2 000 1/2

001 2/2 001 2/2

010 3/2 010 3/2

011 4/2 011 4/2

100 5/2 100 5/2

101 6/2 101 6/2

110 7/2 110 7/2

111 8/2 111 8/2

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Twass Twneg

Write Wait State

FWE EB EFWE

Figure 8-5 Write Signal Diagram

8.6.2 Read Signal Timing

Read Enable (EB,OE and FRE) provides a write enable signal for updating memory content. And the assert and negate timing can be configured flexibly.

Table 8-6 Read Assert Timing (Unit : system cycle) RATS[2:0] Assert time (Ttas)

000 1/2

001 2/2

010 3/2

011 4/2

100 5/2

101 6/2

110 7/2

111 8/2

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Trass

Read Wait State

EB,OE,FRE

Figure 8-6 Read Assert Timing Diagram without being inversed (RINV=1)

Trass

Read Wait State

EB,OE,FRE

Figure 8-7 Read Assert Timing Diagram with being inversed (RINV=1)

8.6.3 EBI Functional Description

8.6.3.1 Chip Selects

Each chip select can provide a chip enable signal for an memory device and assert the internal bus cycle termination signal.

Setting the CSEN bit in CSCR enables the chip select to provide an memory chip enable signal.

Both the chip select pin assertion and the bus cycle termination function depend on an initial address/option match for activation. During the matching

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process, the fixed base address of each chip select is compared to the corresponding address for the bus cycle to determine whether an address match has occurred. This match is further qualified.

By comparing the internal read/write indication and access type with the programmed values in CSCR of each chip select. When the address and option information match the current cycle, the chip select is activated. If no chip select matches the bus cycle information for the current access, the chip select logic does not respond in any way.

Only one chip select can be active for a given bus cycle. The configuration of the active chip select, determined by the wait state (WS/WWS) field, the port size (PS) field, and the write enable (WE) field, is used for the access.

NOTE: Chip select logic does not decode internal address bits A[31:29] A[27:24].

Table 8-7 Chip Select Address Range Encoding

Chip Select Block Size Normal Mode Address

Range13

Address Bits Compared

(A[31:21])14

CS0 in normal master mode

64MB 0x8000_0000-0x83ff_ffff 1xxx_00xx_xxxx


CS0 in debug master mode

64MB 0x0000_0000-0x007f_ffff 0x8080_0000-0x83ff_ffff

0xxx_0000_0xxx 1xxx_00xx_xxxx&

~(1xxx_0000_0xxxx)


CS1 64MB 0x8800_0000-0x8bff_ffff 1xxx_10xx_xxxx

8.6.3.2 Operand Transfer

The possible operand accesses for the internal C*CORE bus are:

byte

Aligned upper half-word

13The base addresses are dependent on the different modes.

14The chip selects do not decode A[31:29] and A[27:24]. Thus the total 1M byte block size is

repeated/mirrored in external memory space.

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Aligned lower half-word

Aligned word

No misaligned transfers are supported. The EBI controls the byte, half-word, or word operand transfers between the C*CORE bus and a 8-bit, 16-bit or 32-bit port. "Port" refers to the width of the data path that an external device uses during a data transfer. Each port is assigned to particular bits of the data bus. For CS0 and CS1, a 8-bit port is assigned to pins D[31:24], a 16-bit port is assigned to pins D[31:16] and a 32-bit port is assigned to pins D[31:0].

Table 8-8 to Table 8-10 shows each possible transfer size, alignment, and port width of CS0 and CS1. The data bytes shown in the table represent external data pins. This data is multiplexed and driven to the external data bus as shown. The bytes labeled with a dash are not required; the C*CORE will ignore them on read transfers, and driven them with undefined data on write transfers.

Table 8-8 8-bit Port Data Transfer of CS0 and CS1

Transfer Size

Port Width

Internal Addr External Pins Data Bus Transfer

Bit1 Bit0 A1 A0

byte 8

0 0 0 0 D[31:24]

0 1 0 1 D[31:24]

1 0 1 0 D[31:24]

1 1 1 1 D[31:24]

Half-word 8

0 0 0 0 D[31:24]

0 1 D[31:24]

1 0 1 0 D[31:24]

1 1 D[31:24]

Word 8 0 0

0 0 D[31:24]

0 1 D[31:24]

1 0 D[31:24]

1 1 D[31:24]

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Transfer Size

Port Width


Bit1 Bit0 A1 A0

byte 16

0 0 0 0 D[31:24]

0 1 0 1 D[23:16]

1 0 1 0 D[31:24]

1 1 1 1 D[23:16]

Half-word 16 0 0 0 0 D[31:24] D[23:16]

1 0 1 0 D[31:24] D[23:16]

Word 1615 0 0 0 0 D[31:24] D[23:16]

1 0 D[31:24] D[23:16]


Transfer Size

Port Width


Bit1 Bit0 A1 A0

byte 32

0 0 0 0 D[31:24]

0 1 0 1 D[23:16]

1 0 1 0 D[15:8]

1 1 1 1 D[7:0]

Half-word 32 0 0 0 0 D[31:24] D[23:16]

1 0 1 0 D[15:8] D[7:0]

Word 32 0 0 0 0 D[31:24] D[23:16] D[15:8] D[7:0]

8.6.3.3 Enable byte Pins (EB[3:0])

The enable byte pins (EB[3:0]) are configured as byte enables for read and write cycles, or as write enables for write cycles only. The default function is byte enable unless there is an active chip-select match with the WE bit set. In all external cycles when one or more EB pins are asserted, the encoding

15The EBI runs two cycles for word accesses to 16-bit ports. The table shows the data placement for

both bus cycles.

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corresponds to the external data pins to be used for the transfer as outlined in Table 8-11.

Table 8-11 EB[3:0] Assertion Encoding

EB Pin External Data Pins

EB0 D[31:24]

EB1 D[23:16]

EB2 D[15:8]

EB3 D[7:0]

8.6.4 NANDFLASH Operation

8.6.4.1 NANDFLASH Chip Access Channels

Table 8-12 NANDFLASH Chip Access Channels Channel Name Size Channels Address Range

Command Channel Word 0x00d5_0000

Address Channel Word 0x00d5_0004

Non-ECC Data Channel Word 0x00d5_0008

ECC Data Channel Word 0x00d5_000C

Dummy ECC Data Channel Word 0x00d5_0010

8.6.4.2 Operand Transfer

The possible operands accesses for the internal C*CORE bus are:

byte

Aligned upper half-word

Aligned lower half-word

Aligned word

No misaligned transfers are supported. The NFCS controls the byte, half-word, or word operand transfers between the C*CORE bus and a 8-bit, 16-bit or 32-bit port. "Port" refers to the width of the data path that an external device

118


uses during a data transfer. Each port is assigned to particular bits of the data bus.

Table 8-13 to Table 8-18 shows each possible transfer size, alignment, and port width of NFCS. The data bytes shown in the table represent external data pins. This data is multiplexed and driven to the external data bus as shown. The bytes labeled with a dash are not required; the C*CORE will ignore them on read transfers, and driven them with undefined data on write transfers.

Table 8-13 8-bit Port Data Transfer of NFCS (ENDIAN=1)

Transfer Size

Port Width


Bit1 Bit0 A1 A0

byte 8

0 0 0 0 D[7:0]

0 1 0 1 D[7:0]

1 0 1 0 D[7:0]

1 1 1 1 D[7:0]

Half-word 8

0 0 0 0 D[7:0]

0 1 D[7:0]

1 0 1 0 D[7:0]

1 1 D[7:0]

Word 8 0 0

0 0 D[7:0]

0 1 D[7:0]

1 0 D[7:0]

1 1 D[7:0]


Transfer Size

Port Width


Bit1 Bit0 A1 A0

Byte 16 Invalid access

Half-word 16 0 0 0 0 D[7:0] D[15:8]

1 0 1 0 D[7:0] D[15:8]

Word 16 0 0 0 0 D[7:0] D[15:8]

1 0 D[7:0] D[15:8]

NOTE: The EBI runs two cycles for word accesses to 16-bit ports. The table shows the data

placement for both bus cycles.

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Transfer Size

Port Width


Bit1 Bit0 A1 A0

byte 32 Invalid access

Half-word 32 Invalid access

Word 32 0 0 0 0 D[7:0] D[15:8] D[23:16] D[31:24]


Transfer Size

Port Width


Bit1 Bit0 A1 A0

byte 8

0 0 0 0 D[31:24]

0 1 0 1 D[31:24]

1 0 1 0 D[31:24]

1 1 1 1 D[31:24]

Half-word 8

0 0 0 0 D[31:24]

0 1 D[31:24]

1 0 1 0 D[31:24]

1 1 D[31:24]

Word 8 0 0

0 0 D[31:24]

0 1 D[31:24]

1 0 D[31:24]

1 1 D[31:24]


Transfer Size

Port Width


Bit1 Bit0 A1 A0


Half-word 16 0 0 0 0 D[31:24] D[23:16]

1 0 1 0 D[31:24] D[23:16]

Word 16 0 0 0 0 D[31:24] D[23:16]

1 0 D[31:24] D[23:16]

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Transfer Size

Port Width


Bit1 Bit0 A1 A0


Half-word 32 Invalid access

Word 32 0 0 0 0 D[31:24] D[23:16] D[15:0] D[7:0]

8.6.4.3 NANDFLASH Interface Example

NOTE: ALE, CLE, WE, RE, R/B signals are shared by all the NANDFLASH chips. Except WE, the other signals are omitted in the connection diagrams.

When four 8bit or two 16bit NANDFLASH are connected in parallel mode, the NANDFLASH channel’s port size is 32bit.

The following actions are forbidden except to dummy ECC data channel:

8bit access to 16bit port

8bit or 16bit access to 32bit port

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1. 8-bit NANDFLASH without parallel connection

IO[7:0]

CE

WE

D[7:0]

GPIO

FWE

IO[7:0]

CE

WE

GPIO

Figure 8-8 8-bit NANDFLASH serial connection

2. 8-bit NANDFLASH with parallel connection

IO[7:0]

CE

WE

D[7:0]

GPIO

FWE

IO[7:0]

CE

WE

D[15:8]

Figure 8-9 Two 8-bit NANDFLASH parallel connection

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3. 16-bit NANDFLASH without parallel connection

IO[15:0]

CE

WE

D[15:0]

GPIO

FWE

IO[15:0]

CE

WE

GPIO

Figure 8-10 16-bit NANDFLASH serial connection

4. 16-bit NANDFLASH with parallel connection

IO[15:0]

CE

WE

D[15:0]

GPIO

FWE

IO[15:0]

CE

WE

D[15:0]

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8.6.5 External Bus Master Timing Diagrams

The following timing diagrams show the timing of accesses to memory or a peripheral.

NOTE: The access to NANDFLASH channels will not assert EBI control signals. In the same way, the access to CS0 and CS1 will not assert NFC signals.

CLKOUT

addr v1A[19:0]

CS

R/W

FOE/

EB(WE=0)

FWE/ No Assertion

D[31:0] v1

S1 S2 W1 S1 S2

ALE/CLE

EB (WE=1)

OE

No Assertion

Figure 8-11 Read Access Timing Diagram

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CLKOUT

addr v1A[20:0]

CS

R/W

FWE/EB

FOE/OE No Assertion

D[31:0] v1

S1 S2 W1 S1 S2

ALE/CLE

Figure 8-12 Write Access Timing Diagram

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Section 9 Static Random Access Memory (SRAM)

9.1 Introduction

Features of the static random access memory (SRAM) include:

On-chip 20K byte SRAM

Fixed address space

byte, half-word (16-bit), or word (32-bit) read/write accesses

One clock per access (including bytes, half-words, and words)

Supervisor or user mode access


Access to the SRAM is not restricted in any way. The array can be accessed in supervisor and user modes.

9.3 Low-Power Modes

In wait, doze and stop mode, clocks to the SRAM are disabled. No recovery time is required when exiting these modes.

9.4 Reset Operation

The SRAM contents are undefined immediately following a power-on reset. SRAM contents are unaffected by system reset. If a synchronous reset occurs during a read or write access, then the access completes normally and any pipelined access in progress is stopped without corruption of the SRAM contents.

9.5 Interrupts

The SRAM module does not generate interrupt requests.

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Section 10 Interrupt Controller Module

10.1 Introduction

The interrupt controller collects requests from multiple interrupt sources and provides an interface to the CPU interrupt logic.

10.2 Features

Features of the interrupt controller module include:

Up to 40 interrupt sources

32 unique programmable priority levels for each interrupt source

Independent enable/disable of pending interrupts based on priority level

Select normal or fast interrupt request for each priority level

Fast interrupt requests always have priority over normal interrupts

Ability to mask interrupts at and below a defined priority level

Ability to select between autovectored or vectored interrupt requests

Vectored interrupts generated based on priority level

Ability to generate a separate vector number for normal and fast interrupts

Ability for software to self-schedule interrupts

Software visibility of pending interrupt and interrupt signals to core

Asynchronous operation to support wakeup from low-power modes

10.3 Low-Power Mode Operation

The interrupt controller is not affected by any low-power modes. All logic between the input sources and generating the raw interrupt to the CPU is combinational. This allows the CPU to wake up during low-power stop mode when all system clocks are stopped.

127


10.4 Block Diagram

Figure 10-1 Interrupt Controller Block Diagram

10.5 External Signals

No interrupt controller signals connect off-chip.

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This subsection describes the memory map (see Table 10-1) and registers.

10.6.1 Memory Map

Table 10-1 Interrupt Controller Module Memory Map

Address Bits 31-24 Bits 23-16 Bits 15-8 Bits 7-0 Access1

0x00c5_0000 Interrupt control register (ICR) Interrupt status register (ISR) S/U

0x00c5_0004 Reserved S/U

0x00c5_0008 Reserved S/U

0x00c5_000c Interrupt Pending Register (IPR) S/U

0x00c5_0010 Normal Interrupt Enable Register (NIER) S/U

0x00c5_0014 Normal Interrupt Pending Register (NIPR) S/U

0x00c5_0018 Fast Interrupt Enable Register (FIER) S/U

0x00c5_001c Fast Interrupt Pending Register (FIPR) S/U

0x00c5_0020

through

0x00c5_003c

Unimplemented2 —

Priority level select registers (PLSR0-PLSR39)

0x00c5_0040 PLSR0 PLSR1 PLSR2 PLSR3 S



0x00c5_004c PLSR12 PLSR13 PLSR14 PLSR15 S




0x00c5_005c PLSR28 PLSR29 PLSR30 PLSR31 S



0x00c5_0068

through

0x00c5_007c

Unimplemented(2) —

NOTE:

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1．S = CPU supervisor mode access only. S/U = CPU supervisor or user mode access. User mode

accesses to supervisor only addresses have no effect and result in a cycle termination transfer

error.

2．Accesses to unimplemented address locations have no effect and result in a cycle termination

transfer error

10.6.2 Registers

This subsection contains a description of the interrupt controller module registers.

10.6.2.1 Interrupt Control Register

The 16-bit interrupt control register (ICR) selects whether interrupt requests are autovectored or vectored, and if vectored, whether fast interrupts generate a different vector number than normal interrupts. This register also controls the masking functions.

Address : 0x00c5_0000 and 0x00c5_0001

15 14 13 12 11 10 9 8

R AE FVE ME MFI

0 0 0 0

W

RESET: 1 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

R 0 0 0 MASK4 MASK3 MASK2 MASK1 MASK0

W

RESET: 0 0 0 0 0 0 0 0


Figure 10-2 Interrupt Control Register (ICR)

AE — Autovector Enable Bit

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The read/write AE bit enables autovectored interrupt requests. Reset sets AE.

1= Autovectored interrupt requests. 0= Vectored interrupt requests.

FVE — Fast Vector Enable Bit The read/write FVE bit enables fast vectored interrupt requests to have vector numbers separate from normal vectored interrupt requests. Reset clears FVE.

1= Unique vector numbers for fast vectored interrupt requests 0= Same vector number for fast and normal vectored interrupt requests

ME — Mask Enable Bit The read/write ME bit enables interrupt masking. Reset clears ME.

1= Interrupt masking enabled 0= Interrupt masking disabled

MFI — Mask Fast Interrupts Bit The read/write MFI bit enables masking of fast interrupt requests. Reset clears MFI.

1= Fast interrupt requests masked by MASK value. All normal interrupt requests are masked.

0= Fast interrupt requests are not masked regardless of the MASK value. The MASK only applies to normal interrupts. Reset clears MFI.

MASK[4:0] — Interrupt Mask Field The read/write MASK[4:0] field determines which interrupt priority levels are masked. When the ME bit is set, all pending interrupt requests at priority levels at and below the current MASK value are masked. To mask all normal interrupts without masking any fast interrupts, set the MASK value to 31 with the MFI bit cleared. See Table 10-2. Reset clears MASK[4:0].

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Table 10-2 MASK Encoding MASK[4:0] Masked Priority

Levels Decimal Binary

0 00000 0

1 00001 1-0

2 00010 2-0

3 00011 3-0

• • •

• • •

• • •

31 11111 31-0

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10.6.2.2 Interrupt Status Register

The 16-bit, read-only Interrupt Status Register (ISR) reflects the state of the interrupt controller outputs to the CPU. Writes to this register have no effect and are terminated normally.

Address : 0x00c5_0002 and 0x00c5_0003

15 14 13 12 11 10 9 8

R 0 0 0 0 0 0 INT FINT

W

RESET: 1 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

R 0 VEC6 VEC5 VEC4 VEC3 VEC2 VEC1 VEC0

W

RESET: 0 0 0 0 0 0 0 0


Figure 10-3 Interrupt Status Register (ISR)

INT — Normal Interrupt Request Flag The read-only INT flag indicates whether the normal interrupt request signal to the CPU is asserted or negated. Reset clears INT.

1= Normal interrupt request asserted 0= Normal interrupt request negated

FINT — Fast Interrupt Request Flag The read-only FINT flag indicates whether the fast interrupt request signal to the CPU is asserted or negated. Reset clears FINT.

1= Fast interrupt request asserted 0= Fast interrupt request negated

VEC[6:0] — Interrupt Vector Number Field The read-only VEC[6:0] field contains the 7-bit interrupt vector number (see 5). Reset clears VEC[6:0].

133


10.6.2.3 Interrupt Pending Register

The 32-bit, read-only Interrupt Pending Register (IPR) reflects any currently pending interrupts which are assigned to each priority level. Writes to this register have no effect and are terminated normally.

Address : 0x00c5_000c through 0x00c5_000f

31 30 29 28 27 26 25 24

R IP31 IP30 IP29 IP28 IP27 IP26 IP25 IP24

W

RESET: 0 0 0 0 0 0 0 0

23 22 21 20 19 18 17 16


W

RESET: 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8


W

RESET: 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0


W

RESET: 0 0 0 0 0 0 0 0


Figure 10-4 Interrupt Pending Register (IPR)

IP[31:0] — Interrupt Pending Field A read-only IPx bit is set when at least one interrupt request is asserted at priority level x. Reset clears IP[31:0].

1= At least one interrupt request asserted at priority level x 0= All interrupt requests at level x negated

134


10.6.2.4 Normal Interrupt Enable Register

The read/write, 32-bit Normal Interrupt Enable Register (NIER) individually enables any current pending interrupts which are assigned to each priority level as a normal interrupt source. Enabling an interrupt source which has an asserted request causes that request to become pending, and a request to the CPU is asserted if not already outstanding.

Address : 0x00c5_0010 through 0x00c5_0013

31 30 29 28 27 26 25 24

R NIE31 NIE30 NIE29 NIE28 NIE27 NIE26 NIE25 NIE24

W

RESET: 0 0 0 0 0 0 0 0

23 22 21 20 19 18 17 16


W

RESET: 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8


W

RESET: 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0


W

RESET: 0 0 0 0 0 0 0 0


Figure 10-5 Normal Interrupt Enable Register (NIER)

NIE[31:0] — Normal Interrupt Enable Field The read/write NIE[31:0] field enables interrupt requests from sources at the corresponding priority level as normal interrupt requests. Reset clears NIE[31:0].

1= Normal interrupt request enabled 0= Normal interrupt request disabled

135


10.6.2.5 Normal Interrupt Pending Register

The read-only, 32-bit Normal Interrupt Pending Register (NIPR) reflects any currently pending normal interrupts which are assigned to each priority level. Writes to this register have no effect and are terminated normally.


31 30 29 28 27 26 25 24

R NIP31 NIP30 NIP29 NIP28 NIP27 NIP26 NIP25 NIP24

W

RESET: 0 0 0 0 0 0 0 0

23 22 21 20 19 18 17 16


W

RESET: 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8


W

RESET: 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0


W

RESET: 0 0 0 0 0 0 0 0


Figure 10-1 Normal Interrupt Pending Register (NIPR)

NIP[31:0] — Normal Interrupt Pending Field A read-only NIPx bit is set when at least one normal interrupt request is asserted at priority level x. Reset clears NIP[31:0].

1= At least one normal interrupt request asserted at priority level x 0= All normal interrupt requests at priority level x negated

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10.6.2.6 Fast Interrupt Enable Register

The read/write, 32-bit Fast Interrupt Enable Register (FIER) individually enables any current pending interrupts which are assigned to each priority level as a fast interrupt source. Enabling an interrupt source which has an asserted request causes that request to become pending, and a request to the CPU is asserted if not already outstanding.


31 30 29 28 27 26 25 24

R FIE31 FIE30 FIE29 FIE28 FIE27 FIE26 FIE25 FIE24

W

RESET: 0 0 0 0 0 0 0 0

23 22 21 20 19 18 17 16


W

RESET: 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8


W

RESET: 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0


W

RESET: 0 0 0 0 0 0 0 0


Figure 10-7 Fast Interrupt Enable Register (FIER)

FIE[31:0] — Fast Interrupt Enable Field The read/write FIE[31:0] field enables interrupt requests from sources at the corresponding priority level as fast interrupt requests. Reset clears FIE[31:0].

1= Fast interrupt request enabled 0= Fast interrupt request disabled

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10.6.2.7 Fast Interrupt Pending Register

The read-only, 32-bit Fast Interrupt Pending Register (FIPR) reflects any currently pending fast interrupts which are assigned to each priority level. Writes to this register have no effect and are terminated fast.


31 30 29 28 27 26 25 24

R FIP31 FIP30 FIP29 FIP28 FIP27 FIP26 FIP25 FIP24

W

RESET: 0 0 0 0 0 0 0 0

23 22 21 20 19 18 17 16


W

RESET: 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8


W

RESET: 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0


W

RESET: 0 0 0 0 0 0 0 0


Figure 10-8 Fast Interrupt Pending Register (FIPR)

FIP[31:0] — Fast Interrupt Pending Field A read-only FIPx bit is set when at least one fast interrupt request is asserted at priority level x. Reset clears FIP[31:0].

1= At least one fast interrupt request asserted at priority level x 0= All fast interrupt requests at priority level x negated

138


10.6.2.8 Priority Level Select Registers

The read/write 8-bit Priority Level Select Registers (PLSRx) are 40 read/write, 8-bit priority level select registers PLSR0–PLSR39, one for each of the interrupt source. The PLSRx register assigns a priority level to interrupt source x.


7 6 5 4 3 2 1 0

R 0 0 0 PLS4 PLS3 PLS2 PLS1 PLS0

W

RESET: 0 0 0 0 0 0 0 0


Figure 10-9 Priority Level Select Registers (PLSR0-PLSR39)

PLS[4:0] — Priority Level Select Field The PLS[4:0] field assigns a priority level from 0 to 31 to the corresponding interrupt source. Reset clears PLS[4:0].

Table 10-3 Priority Select Encoding PLS[4:0] Priority Level Vector Number

00000 0 (lowest) 00000

00001-11110 1-30 00001-11110

11111 31 (highest) 11111

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The interrupt controller collects interrupt requests from multiple interrupt sources and provides an interface to the CPU interrupt logic. Interrupt controller functions include:

Interrupt source prioritization

Fast and normal interrupt requests

Autovectored and vectored interrupt requests

Interrupt configuration

10.7.1 Interrupt Sources and Prioritization

Each interrupt source in the system sends a unique signal to the interrupt controller. Up to 40 interrupt sources are supported. Each interrupt source can be programmed to one of 32 priority levels by programming the PLS bits of the PLSR in the interrupt controller. The highest priority level is 31 and lowest priority level is 0. By default, each interrupt source is assigned to the priority level 0. Each interrupt source is associated with a 5-bit priority level select value that selects one of 32 priority levels. The interrupt controller uses the priority levels as the basis for the generation of all interrupt signals to the CPU.

10.7.2 Fast and Normal Interrupt Requests

FIER allows individual enabling or masking of pending fast interrupt requests. FIER is logically ANDed with IPR, and the result is stored in FIPR. FIPR bits are bit-wise ORed together and inverted to form the fast interrupt signal routed to the CPU (see Table 10-1). The FIPR allows software to quickly determine the highest priority pending fast interrupt. The output of FIPR also feeds into a 32-to-5 priority encoder to generate the vector number to present to the CPU if vectored interrupts are required.

NIER allows individual enabling or masking of pending normal interrupt requests. NIER is logically ANDed with IPR, and the result is stored in NIPR. NIPR bits are bit-wise ORed together and inverted to form the normal interrupt signal routed to the CPU. The normal interrupt signal is only asserted if the fast interrupt signal is negated. The NIPR allows software to quickly determine the highest priority pending normal interrupt. The output of NIPR also feeds into a 32-to-5 priority encoder to generate the vector number to present to the CPU if vectored interrupts are required. If the fast interrupt signal is asserted, then the vector number is determined by the highest priority fast interrupt.

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If an interrupt is pending at a given priority level and both the corresponding FIER and NIER bits are set, then both the corresponding FIPR and NIPR bits are set, assuming these bits are not masked.

Fast interrupt requests always have priority over normal interrupt requests, even if the normal interrupt request is at a higher priority level than the highest fast interrupt request.

If the fast interrupt signal is asserted when the normal interrupt signal is already asserted, then the normal interrupt signal is negated.

IPR, NIPR, and FIPR are read-only. To clear a pending interrupt, the interrupt must be cleared at the source using a special clearing sequence defined by each source. All interrupt sources to the interrupt controller are to be held until recognized and cleared by the interrupt service routine. The interrupt controller does not have any edge-detect logic. Edge-triggered interrupt sources are handled at the source module.

In ICR, the MASK[4:0] bits can mask interrupt sources at and below a selected priority level. The MFI bit determines whether the mask applies only to normal interrupts or to fast interrupts with all normal interrupts being masked. The ME bit enables interrupt masking.

ISR reflects the current vector number and the states of the signals to the CPU.

The vector number and fast/normal interrupt sources are synchronized before being sent to the CPU. Thus, the interrupt controller adds one clock of latency to the interrupt sequence. The fast and normal interrupt raw sources are not synchronized and are used to wake up the CPU during stop mode.

10.7.3 Autovectored and Vectored Interrupt Requests

The AE bit in ICR enables autovectored interrupt requests to the CPU. AE is set by default, and all interrupt requests are autovectored. An interrupt handler may read FIPR or NIPR to determine the priority of the interrupt source. If multiple interrupt sources share the same priority level, then it is up to the interrupt service routine to determine the correct source of the interrupt.

If the AE bit is 0, then each interrupt request is presented with a vector number. The low five bits of the vector number (4–0) are determined based on the highest pending priority, with active fast interrupts having priority over active normal interrupts. The remaining two bits (vector bits 5 and 6) are determined based on whether the interrupt request is a fast interrupt and the setting of the FVE bit. If FVE is set, then a fast interrupt request has a vector number different from that of a normal interrupt request as shown in Table 10-4.

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Table 10-4 Fast Interrupt Vector Number

Fast Interrupt FVE Interrupt Vector

Bits 6:5

No X 01

X 0 01

Yes 1 10

If FVE is 0, both normal and fast interrupts have the same vector and requests assigned to priority levels 0–31 are mapped to vector numbers 32–63 in the vector table.

If FVE is 1, normal interrupt requests assigned to priority levels 0–31 are mapped to vector numbers 32–63 and fast interrupt requests assigned to priority levels 0–31 are mapped to vector numbers 64–95 in the vector table. See Table 10-5.

Table 10-5 Vector Table Mapping Vector

Number Usage

Interrupt Vector Bits 6:5

0-31 Fixed exceptions (including autovectors) 00

32-63 Vectored interrupts 32 = lowest priority 63 = highest priority

01

64-95 Vectored interrupts 64 = lowest priority 95 = highest priority

10

96-127 Vectored interrupts (not used) 11

10.7.4 Interrupt Configuration

After reset, all interrupts are disabled by default. To properly configure the system to handle interrupt requests, configuration must be performed at three levels:

CPU

Interrupt controller

Local interrupt sources

Configure the CPU first, the interrupt controller second, and the local interrupt sources last.

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10.7.4.1 CPU Configuration

For fast interrupts, set the FIE[x] bit in FIER in the CPU. For normal interrupts, set the NIE[x] bit. Both FIE and NIE are cleared at reset.

NOTE:

To allow long latency, multicycle instructions to be interrupted before completion, set the IC bit in the PSR.

VBR in the CPU defines the base address of the exception vector table. If autovectors are to be used, then initialize the INT and FINT autovectors (vector numbers 10 and 11, respectively). If vectored interrupts are to be used, then initialize the vectored interrupts (vector numbers 32–63 and/or 64–95). Whether 32 or 64 vectors are required depends on whether the fast interrupts share vectors with the normal interrupt sources based on the FVE bit in the interrupt controller ICR.

For each vector number, create an interrupt service routine to service the interrupt, clear the local interrupt flag, and return from the interrupt routine.

10.7.4.2 Interrupt Controller Configuration

By default, each interrupt source to the interrupt controller is assigned a priority level of 0 and disabled. Each interrupt source can be programmed to one of 32 priority levels and enabled as either a fast or normal interrupt source. Also, the FVE and AE bits in ICR can be programmed to select autovectored/vectored interrupts and also determine if the fast interrupt vector number is to be separate from the normal interrupt vector.

10.7.4.3 Interrupt Source Configuration

Each module that is capable of generating an interrupt request has an interrupt request enable/disable bit. To allow the interrupt source to be asserted, set the local interrupt enable bit.

Once an interrupt request is asserted, the module keeps the source asserted until the interrupt service routine performs a special sequence to clear the interrupt flag. Clearing the flag negates the interrupt request.

143


10.7.5 Interrupts

The interrupt controller assigns a number to each interrupt source, as Table 10-6 shows (Pending due to 3rd Party’s IP and C*Core’s IP).

Table 10-6 Interrupt Source Assignment Source Module Flag Source Description Flag Clearing Mechanism

0 USBC1

1 USBC2

2 RSA

3 DMAC

4 Reversed

5 PIT1

6 PIT2

7

EPORT

EPF0 Edge port flag 0 Write EPF0 = 1

8 EPF1 Edge port flag 1 Write EPF1 = 1







15 SCI1

TDRE Transmit Data Register empty Write SCIDRL after reading TDRE = 1

TC Transmit complete Write SCIDRL after reading TC = 1

RDRF Receive Data Register full Read SCIDRL after reading RDRF = 1

OR Receiver overrun Read SCIDRL after reading OR = 1

IDLE Receiver line idle Read SCIDRL after reading IDLE = 1

16 SCI2

TDRE Transmit Data Register empty Write SCIDRL after reading TDRE = 1

TC Transmit complete Write SCIDRL after reading TC = 1

RDRF Receive Data Register full Read SCIDRL after reading RDRF = 1

OR Receiver overrun Read SCIDRL after reading OR = 1

IDLE Receiver line idle Read SCIDRL after reading IDLE = 1

17 UCI1 ATR Answer to Reset Write UCITDR after reading ATR = 1

WTO WTC timeout Write WTEN =0

144


PF Parity Error

Read UCIRDR after reading PF=1 in receive mode. Write 1 to PF bit after reading PF=1 in transmit mode.

RDRF Receive Data Register full Read UCIRDR after reading RDRF = 1

OR Receiver overrun Read UCIRDR after reading OR = 1

TDRE Transmit Data Register empty Write UCITDR after reading TDRE = 1

TC Transmit complete Write UCITDR after reading TC = 1

18 UCI2

ATR Answer to Reset Write UCITDR after reading ATR = 1

WTO WTC timeout Write WTEN =0

PF Parity Error

Read UCIRDR after reading PF=1 in receive mode. Write 1 to PF bit after reading PF=1 in transmit mode.

RDRF Receive Data Register full Read UCIRDR after reading RDRF = 1

OR Receiver overrun Read UCIRDR after reading OR = 1

TDRE Transmit Data Register empty Write UCITDR after reading TDRE = 1

TC Transmit complete Write UCITDR after reading TC = 1

19 SPI1

MODF Mode fault Write to SPICR1 after reading MODF = 1

20 SPIF Transfer complete Access SPIDR after reading SPIF = 1

21 SPI2

MODF Mode fault Write to SPICR1 after reading MODF = 1

22 SPIF Transfer complete Access SPIDR after reading SPIF = 1

23 ECC DONE ECC encoding/decoding

done Write 1 to this bit

24 ENCR EWDONE Encryption Wrapper done Write 1 to this bit

25 PWM

26 I2C

27 TRNG

28 LVD

29 HVD

30 KPP

145


Section 11 RSA/SM2 Accelerator Module

11.1 Introduction

The RSA/SM2 Accelerator module supports popular public key cryptography algorithms by implementing some large integer arithmetic operations in hardware.

11.2 Features

The features of the RSA/SM2 Accelerator module include:

Large operand size N integer arithmetic - 192 bits - 256 bits - 512 bits - 1024 bits - 2048 bits

Programmable scalar or modulo16

- Y = A + B operation

- Y = A - B - Y = A * B - Y = (A + B) mod M - Y = (A - B) mod M - Y = (A * B) mod M - Y = (1/A) mod M - Y = (AE) mod M

Discrete "sea-of-gates" implementation - Protection against SPA and probing attacks

High performance N-bit ALU

16For exponentiation, the modulus must be odd and full-size, i.e. first and last bits must be set. For

inversion, the modulus must be a full size prime number. For even, non-prime exponentiation or

inversion, the Chinese Remainder Theorem (CRT) should be used to convert the operation into an

odd/prime computation that can be done by this hardware, and even/non-prime computations that

can be carried out by software.

146


- 1 to 3 clock cycles for modular addition/subtraction - 2N to 5N clock cycles for modular multiplication - Around 8N2 clock cycles (or less) for modular

exponentiation/inversion Additional ’general purpose’ operations

- Register Copy - Register Swap - Register Clear - Find First One - Montgomery Residue Conversion - Montgomery Product - Shift Right - Shift Left

11.3 Block Diagram

The block diagram of the RSA/SM2 Accelerator module is shown in Figure 11-1. The RSA/SM2 Accelerator module is essentially a pipelined Arithmetic Logic Unit (ALU) for large integer operands. The RSA/SM2 Accelerator module interfaces to the IPS bus, mostly supporting 32-bit access (for data transfer), with some 8-bit access support for control functions. The RSA/SM2 Accelerator module can generate a number of different interrupts when computations complete, which may be combined into a single interrupt as required by software. Status flags are also provided.

147


ALU ALUControl

BusControl

OperandStorage

int

32BitIPBUS

Figure 11-1 RSA/SM2 Accelerator Module Block Diagram

11.4 Memory Map

The RSA/SM2 Accelerator module memory map includes control and status registers and operand storage registers. The memory map, which occupies a 2KB section of IP bus space, is shown in Table 11-1. There are five 32-bit control and status registers, five 2048-bit operand/result registers, while the remaining addresses are reserved and always return zero.

Table 11-1 RSA/SM2 Accelerator Module Memory Map

Address Bits 31-24 Bits 23-16 Bits 15-8 Bits 7-0 Type17

0x00c6_0000

RSA/SM2 Accelerator Configuration Register (CACR)

0x00c6_0004 RSA/SM2 Accelerator Operations Register (CAOR)

0x00c6_0008 RSA/SM2 Accelerator Status Register (CASR)

0x00c6_000c RSA/SM2 Accelerator Interrupt Register (CAIR)

0x00c6_0010 Exponent First One Index Register (INXR)

0x00c6_0014 Reserved

0x00c6_0100

to

0x00c6_01fc

Operand Y and Result Register (OP_Y)

Volatile

17The listed register type is an indication only. Some commands do not affect any of the operand

registers (e.g. FF1) while others may affect/change several of the operand registers, including the

Non-Volatile registers (e.g. INV affects Y/A/B/E).

148


0x00c6_0200

to

0x00c6_02fc

Operand A and Alternate Result Register (OP_A)

Volatile

0x00c6_0300

to

0x00c6_03fc

Operand B Register (OP_B)

Volatile

0x00c6_0400

to

0x00c6_04fc

Operand E (Exponent) Register (OP_E)

Non-Volatile

0x00c6_0500

to

0x00c6_05fc

Operand M (Modulus) Register (OP_M)

Non-Volatile

0x00c6_0600 Reserved

The operand registers can only be accessed through word size (32-bit) transactions, with halfword or byte size access causing undefined behavior of the RSA/SM2 Accelerator module. The control and status registers can be accessed in word, halfword and byte mode through normal IPS bus transactions.

Note that the RSA/SM2 Accelerator module assumes all registers are accessed properly, i.e. at the right time, with the right size, and with the right data, depending on whatever operational state the module is in. Data in the ’Volatile’ operand registers may change as a result of arithmetic operations, while data in ’Non-Volatile’ registers may change only in certain cases, e.g. if a value is moved/copied to that register.

Hardware does not detect or prevent incorrect operation through wrong IPS bus accesses. For example, if the operand registers are written while a computation is in progress, the result may be undefined. Operations sharing source and destination operand registers are generally undefined (except for OP_Y).

Software should access the RSA/SM2 Accelerator module either driven by interrupts or after predicting bus timing. Alternatively, status bits may be polled to determine whether the RSA/SM2 Accelerator module can be safely accessed, although this is NOT a good method, because it is slow, and consumes power unnecessarily.

11.4.1 RSA/SM2 Accelerator Configuration Register

The RSA, shown in Table 1-2, is used to define the size of the operations of the RSA/SM2 Accelerator module.

149



31 30 29 28 27 26 25 24

R 0 0 0 0 0 0 0 0

W

RESET: 0 0 0 0 0 0 0 0

23 22 21 20 19 18 17 16

R 0 0 0 0 0 0 0 0

W

RESET: 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8

R 0 0 0 0 0 0 0 0

W

RESET: 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

R 0 0 0 0 0 OPSIZE[2:0]

W

RESET: 0 0 0 0 0 1 1 1


Figure 11-2 RSA/SM2 Accelerator Configuration Register (CACR)

OPSIZE[2:0] — Operand Size This field determines the size (width) of operations of the RSA/SM2 Accelerator module, including which bits of the operand registers are used/updated (see below).

000= Reserved (don’t use) 001= Reserved (don’t use) 010= Reserved (don’t use) 011= 192 bit operation 100= 256 bit operation 101= 512 bit operation 110= 1024 bit operation 111= 2048 bit operation

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NOTE: The RSA/SM2 Accelerator module assumes all operands are unsigned (positive) integers of the selected size (width). For modulus operands (stored in the OP_M register), it is expected that the most significant bit (MSb) of the operand (i.e. bit 191, 255, 511, 1023 or 2047) is non-zero, and for most operations, the modulus is expected to be an odd number, i.e. the least significant bit (LSb) is also non-zero. For some specific operations (e.g. inverse), the modulus is expected to be a prime number.

CAUTION: Hardware does not check for these requirements and correct operation is not guaranteed unless appropriate values are stored (by software) in the various operand registers.

CAUTION:: Changing the value of the OPSIZE[2:0] field while an operation is in progress may cause undefined behavior and incorrect results.

NOTE: The OPSIZE[2:0] command determines which parts of the operand registers (see Sections 11.4.6 to 11.4.10) can be read through the IPS bus. For example, if OPSIZE is set to 192-bits, then only OP_X[191:0] (addresses 0xK00 through 0xK17) can be read, while the higher words all return zero. This only affects reading, not writing, i.e. the whole 2048-bits of an operand can be written regardless of OPSIZE.

11.4.2 RSA/SM2 Accelerator Operations Register

The RSA/SM2 Accelerator Operations Register, shown in Figure 11-3, is used to activate operations of the RSA/SM2 Accelerator module, i.e. initiate a computation or other data-path function.


31 30 29 28 27 26 25 24

R 0 0 0 0 0 0 0 0

W

RESET: 0 0 0 0 0 0 0 0

23 22 21 20 19 18 17 16

R 0 0 0 0 0 0 0 0

W

RESET: 0 0 0 0 0 0 0 0

151


15 14 13 12 11 10 9 8

R OP2[1:0] OP1[1:0]

0 DEST[2:0]

W

RESET: 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

R 0 0 0 CMD[4:0]

W

RESET: 0 0 0 0 0 0 0 0


Figure 11-3 RSA/SM2 Accelerator Operations Register (CAOR)

OP2[1:0] — Second Operand This field specifies the second operand for the operation of the CMD[4:0] field. Not all commands need a second operand or have a fixed second operand, in which case OP2[1:0] is ignored.

Table 11-2 Second Operand Encoding

OP2[1:0] Operand

00 None (zero)

01 OP_A

10 OP_E

11 OP_Y

OP1[1:0] — First Operand This field specifies the first operand for the operation of the CMD[4:0] field. Not all commands need a first operand or have a fixed first operand, in which case OP1[1:0] is ignored.

152


Table 11-3 First Operand Encoding

OP1[1:0] Operand

00 None (zero)

01 OP_B

10 OP_M

11 OP_Y

DEST[2:0] — Destination (Write-Back) Register This field specifies the destination (result write-back) register for the operation of the CMD[4:0] field. Some commands have a fixed destination, in which case DEST[2:0] is ignored.

Table 11-4 Destination Register Encoding

DEST[2:0] Operand

000 None

001 None

010 None

011 OP_Y

100 OP_A

101 OP_B

110 OP_E

111 OP_M

CMD[4:0] — Command (Operation) This field determines the type of operation executed by the RSA/SM2 Accelerator module. The available commands are listed in Table 11-5.

NOTE: A command is executed in the cycle following a write-access to the RSA/SM2 Accelerator Operations Register, but only if the RSA/SM2 Accelerator module is not busy. If the RSA/SM2 Accelerator module is busy executing another (multi-cycle) command, then the write-access will be ignored. In this case, neither the Command nor the Operand and Destination fields will be updated and the RSA/SM2 Accelerator module will continue operating as before, until the current operation finishes as normal.

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Some commands require one or two operands and a destination register to be defined, while other commands use fixed operands and destination registers, in which case the operand and a destination register may be ignored.

CAUTION: Three of the five operand registers (B/M/E) are latch-based and must not be specified as both source (operand) and destination register, because the result may be undefined. Only Y and A can be used as both source and destination.

Commands are (started to be) executed in the cycle following writing to the CMD field, while the values written-to or stored-in the OP1, OP2 and DEST fields are used to select the source and destination operands. Consequently, successive commands could be initiated (using the same operands) by writing a byte to the CMD field, while keeping the OP1, OP2 and DEST fields as they are.

Table 11-5 RSA/SM2 Accelerator module Commands

CMD[4:0] Command Operation Description

00000 NOP n/a No Operation.

00001 ADDS DEST = OP1 + OP2 Add the value of the OP1 and OP2 operand registers and store the result in the DEST register. The carry-bit (CO) is updated.

00010 ADD1S DEST = OP1 + OP2 + 1

Add the value of the OP1 and OP2 operand registers and store the result in the DEST register. The carry-bit (CO) is updated. To implement a proper increment operation, one of the operands must be set to zero (either OP1[1:0] or OP2[1:0] is 00). A one (1) is loaded into the DEST register if both operands are set to zero (both OP1[1:0] and OP2[1:0] are 00).

00011 SUBS DEST = OP2 - OP1

Subtract the value of the OP1 operand register from OP2, and store the result in the DEST register. In fact, OP2 is added to the inverse (NOT) of OP1 plus one (1). The carry-bit (CO) is updated.

00100 DECS DEST = OP2 - 1 Decrement the value of the OP2 register and store the result in the DEST register. The carry-bit (CO) is updated.

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00101 ADDM DEST = OP1 + OP2 [-M]

Add the value of the OP1 and OP2 operand registers and store the result in the DEST register. Next, the value of the OP_M register is subtracted from DEST, unless the result is negative (MSb set), in which case OP_M is not subtracted (or in fact, it is added back to DEST). DEST can only be OP_A or OP_Y, otherwise the result may be undefined.

00110 SUBM DEST = OP2 - OP1 [+M]

Subtract the value of the OP1 operand register from OP2 and store the result in the DEST register. In fact, OP2 is added to the inverse (NOT) of OP1 plus one (1). The carry-bit (CO) is updated. Next, the value of the OP_M register is added to DEST if the result was negative (MSb set), otherwise OP_M is not added. DEST can only be OP_A or OP_Y, otherwise the result may be undefined.

00111 FF1 INX = FF1(OP1 + OP2)

Find the position (index) of the most significant set bit in the OP1 or OP2 register and store the result in the Exponent First One Index Register (INXR). Note that either OP1 or OP2 must be set to zero (00) for proper operation.

01000 SHL DEST = (OP1 + OP2) * 2

Shift the contents of the OP1 or OP2 register left by one bit and store the result in DEST. Zero (0) is shifted into the least significant bit (LSb) and the most significant bit (MSb) is shifted out into the carry bit (CO). Note that either OP1 or OP2 must be set to zero (00) for proper operation.

01001 SHR DEST = (OP1 + OP2) / 2

Shift the contents of the OP1 or OP2 register right by one bit and store the result in DEST. Zero (0) is shifted into the most significant bit (MSb) and the least significant bit (LSb) is shifted out into the carry bit (CO). Note that either OP1 or OP2 must be set to zero (00) for proper operation.

01010 n/a n/a Reserved (NOP).

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01011 MULS Y = A * B A = undefined

Multiply the values in the OP_A and OP_B registers, and store the result in OP_Y. If the result is wider than the operand size, the carry bit is set (1), otherwise it is cleared (0). OP_A is destroyed (garbage) during the multiplication.

01100 MULM Y = A * B mod M A = undefined

Modulus-multiply the values in the OP_A and OP_B registers, and store the result in DEST. The result is adjusted to be smaller than the modulus value in the OP_M register. OP_A is destroyed (garbage) during the multiplication.

01101 MPR Y = A Θ B Montgomery-multiply the values in the OP_A and OP_B registers, and store the result in OP_Y.

01110 MINV Y = 1 / A mod M

Modulus-invert the value in the OP_A register and store the result in OP_Y. The value in the OP_M register must be a prime number, otherwise the result is invalid. Note that the MINV command actually calculates Y = A(M - 2) mod M. The value in the OP_A, OP_B and OP_E registers may be overwritten. The value in the INXR register is also overwritten.

01111 EXPF Y = AE mod M

Modulus-exponentiate the value in the OP_A register to the power of OP_E and store the result in OP_Y. The value in the OP_M register must be an odd number, otherwise the result is invalid. The value in the OP_A and OP_B registers may be overwritten. The value in the INXR register is also overwritten. The execution time of this command depends on OP_E.


10001 MRES DEST = (OP1 + OP2) * 2N mod M

Find the (Montgomery) Modulo-Residu of OP1 or OP2 and store it in DEST. Note that either OP1 or OP2 should be set to zero (00) for proper Residu operation. DEST must specify either OP_A or OP_Y, otherwise the result will be undefined (garbage).

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10010 -


11.4.3 RSA/SM2 Accelerator Status Register

The RSA/SM2 Accelerator Status Register, shown in Figure 11-4, provides information about the status and result of operations of the RSA/SM2 Accelerator module. This includes any carry-out of computations as well as a busy-status flag, which sets during multi-cycle operations. Together with the command (CMD) stored in the RSA/SM2 Accelerator Operation Register, the current operational state of the RSA/SM2 Accelerator module can be determined.


31 30 29 28 27 26 25 24

R 0 0 0 0 0 0 0 0

W

RESET: 0 0 0 0 0 0 0 0

23 22 21 20 19 18 17 16

R 0 0 0 0 0 0 0 BSY

W

RESET: 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8

R 0 0 0 0 0 0 0 0

W

RESET: 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

R 0 0 0 0 MSB LSB CX CO

W

RESET: 0 0 0 0 0 0 0 0


Figure 11-4 RSA/SM2 Accelerator Status Register (CASR)

157


BSY — Busy Status Indicates the RSA/SM2 Accelerator module is busy executing a multi-cycle operation.

1= RSA/SM2 Accelerator module is busy 0= RSA/SM2 Accelerator module is not busy

MSb — Most Significant Bit This bit reflects the most significant bit of the last stored result (depending on the selected operand size, i.e bit 191, 255, 511, 1023 or 2047).

1= MSb is set (1) 0= MSb is cleared (0)

LSb — Least Significant Bit This bit reflects the least significant bit of the last stored result (bit 0).

1= LSb is set (1) 0= LSb is cleared (0)

CX — Extended Carry Out This bit contains an extended carry-out (overflow) that may have been the result of a Montgomery operation of the RSA/SM2 Accelerator module. It is essentially a carry-out of the ’normal’ carry-out. The two carry bits together with the data-path form a 2050-bit adder used in Montgomery Multiplication. This bit is made visible mainly for testing purposes and can be ignored during normal operation.

1= Extended Carry-out (overflow) occurred 0= No Extended Carry-Out occurred

Note that the CX bit can be (but should not be) written through the IPS bus.

CO — Carry Out This bit contains any carry-out (overflow or underflow) that may have been the result of an operation of the RSA/SM2 Accelerator module.

1= Carry-out (overflow) occurred 0= No Carry-Out occurred

Note that the CO bit can be (but should not be) written through the IPS bus.

11.4.4 RSA/SM2 Accelerator Interrupt Register

The RSA/SM2 Accelerator Interrupt Register, shown in Figure 1-5, is used to enable, check and clear interrupts that may be triggered by the RSA/SM2 Accelerator module.

158



31 30 29 28 27 26 25 24

R 0 0 0 0 0 0 0 0

W

RESET: 0 0 0 0 0 0 0 0

23 22 21 20 19 18 17 16

R 0 0 0 0 0 OIF MIF EIF

W

RESET: 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8

R 0 0 0 0 0 0 0 0

W

RESET: 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

R 0 0 0 0 0 OIE MIE EIE

W

RESET: 0 0 0 0 0 0 0 0


Figure 11-5 RSA/SM2 Accelerator Interrupt Register (CAIR)

OIF — Other Interrupt Flag Indicates an interrupt has occurred (other than for Multiplication of Exponentiation).

1= Other Interrupt Occurred 0= No Other Interrupt Occurred

MIF — Multiplication Interrupt Flag Indicates an interrupt has occurred (for Multiplication).

1= Multiplication Interrupt Occurred 0= No Multiplication Interrupt Occurred

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EIF — Exponentiation Interrupt Flag Indicates an interrupt has occurred (for Exponentiation).

1= Exponentiation Interrupt Occurred 0= No Exponentiation Interrupt Occurred

Interrupt flags assert if a multi-cycle operation completed and the corresponding interrupt enable bit was set. An interrupt can be cleared by writing a one (1) to the corresponding interrupt status flag.

OIE — Other Interrupt Enable Enables interrupts (other than for Multiplication of Exponentiation).

1= Other Interrupt Enabled 0= Other Interrupt Disabled

MIE — Multiplication Interrupt Enable Enables Multiplication interrupts.

1= Multiplication Interrupt Enabled 0= Multiplication Interrupt Disabled

EIE — Exponentiation Interrupt Enable Enables Exponentiation interrupts.

1= Exponentiation Interrupt Enabled 0= Exponentiation Interrupt Disabled

The RSA/SM2 Accelerator module supports three separate active-low interrupt signals. If only a single interrupt signal is needed/desired, then the three interrupt outputs can be tied together (using a logic AND gate) outside the RSA/SM2 Accelerator module.

11.4.5 Exponent First One Index Register

The Exponent First One Index Register, shown in Figure 11-6, is used to store the result of the FF1 command of the RSA/SM2 Accelerator module.

The FF1 command finds the bit-index of the highest (most significant) set bit of the value in the specified operand register. Note that this command can be executed explicitly by programming the FF1 command in the CMD register, or implicitly as a result of other commands, e.g. modular exponentiation.

160


Address : 0x00c6_0010through 0x00c6_0013

31 30 29 28 27 26 25 24

R 0 0 0 0 0 0 0 0

W

RESET: 0 0 0 0 0 0 0 0

23 22 21 20 19 18 17 16

R 0 0 0 0 0 0 0 IV

W

RESET: 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8

R 0 0 0 0 0 INX[10:8]

W

RESET: 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

R INX[7:0]

W

RESET: 0 0 0 0 0 0 0 0


Figure 11-6 Exponent First One Index Register (INXR)

IV — Index Valid This read-only bit indicates whether the value in INX[10:0] is valid, i.e. distinguish between the INX=11’b0 reset value and INX=11’b0 indicating that the OP_X[0] bit was set as the highest set bit. The IV flag is cleared when the INXR register is written through the IPS bus (any value to any byte), or when no set bit was found in OP_X.

1= INX[10:0] contains the index to the highest set bit of the last FF1 search

0= INX[10:0] is not valid

INX[10:0] — First One Index This field indicates the position of the most significant (set) bit in either an operand register specified for the FF1 command, or in operand E for an

161


EXPF, EXPS or MINV command (these commands use FF1 as part of their execution). Note that the INX bits can be (but should not be) written through the IPS bus.

CAUTION: The INXR register can be read in byte, halfword or word size transactions, but writing to INXR must be with halfword or word size transactions, with byte size write access causing undefined (garbage) results. Write access to INXR is added for test purposes only.

11.4.6 Operand Y and Result Register

The Operand Y and Result Register, shown in Figure 11-7, is used to store the Y operand and result of various RSA/SM2 Accelerator module operations.

The register is 2048-bit wide, but which portion of the register is used depends on the value of the OPSIZE[2:0] field (see Section 11.4.1).

Address : 0x00c6_0100through 0x00c6_01fc

Figure 11-7 Operand Y and Result Register (OP_Y)

The Operand Y and Result Register can be accessed through the IPS bus in 32-bit word-size increments. Individual bytes in these words are in big-endian order, i.e. the most significant byte is stored at the lowest address. Words, however, are stored in little-endian order, i.e. the least significant word is stored at the lowest address.

NOTE: Halfword and byte size access to this register is not allowed and may result in undefined behavior.

162


NOTE: IPS access to this register while a command is being executed is ignored. Writing has no effect, while reading returns zero.

CAUTION: Hardware does not detect or prevent incorrect IPS access to this register.

NOTE: IPS read access from this register (not write access) is limited by the OPSIZE field and reading of words higher than N returns zero.

11.4.7 Operand A and Alternate Result Register

The Operand A and Alternate Result Register, shown in Figure 11-8, is used to store the A operand and the result of various RSA/SM2 Accelerator module operations. The register is 2048-bit wide, but which portion of the register is used depends on the value of the OPSIZE[2:0] field (see Section 11.4.1).


Figure 11-8 Operand A and Alternate Result Register (OP_A)

The Operand A and Alternate Result Register can be accessed through the IPS bus in 32-bit word-size increments. Individual bytes in these words are in big-endian order, i.e. the most significant byte is stored at the lowest address. Words, however, are stored in little-endian order, i.e. the least significant word is stored at the lowest address.


163





11.4.8 Operand B Register

The Operand B Register, shown in Figure 1-9, is used to store the B operand (and result of some RSA/SM2 Accelerator module operations). The register is 2048-bit wide, but which portion of the register is used depends on the value of the OPSIZE[2:0] field (see Section 1.4.1).


Figure 11-9 Operand B Register (OP_B)

The Operand B Register can be accessed through the IPS bus in 32-bit word-size increments. Individual bytes in these words are in big-endian order, i.e. the most significant byte is stored at the lowest address. Words, however, are stored in little-endian order, i.e. the least significant word is stored at the lowest address.


164





11.4.9 Operand E (Exponent) Register

The Operand E (Exponent) Register, shown in Figure 11-10, is used to store the E operand (and the result of some RSA/SM2 Accelerator module operations). The register is 2048-bit wide, but which portion of the register is used depends on the value of the OPSIZE[2:0] field (see Section 11.4.1).


Figure 11-10 Operand E (Exponent) Register (OP_E)

The Operand E (Exponent) Register can be accessed through the IPS bus in 32-bit word-size increments. Individual bytes in these words are in big-endian order, i.e. the most significant byte is stored at the lowest address. Words, however, are stored in little-endian order, i.e. the least significant word is stored at the lowest address.


165





11.4.10 Operand M (Modulus) Register

The Operand M (Modulus) Register, shown in Figure 11-11, is used to store the M operand (and the result of some RSA/SM2 Accelerator module operations). The register is 2048-bit wide, but which portion of the register is used depends on the value of the OPSIZE[2:0] field (see Section 11.4.1).


Figure 11-11 Operand M (Modulus) Register (OP_M)

The Operand M (Modulus) Register can be accessed through the IPS bus in 32-bit word-size increments. Individual bytes in these words are in big-endian order, i.e. the most significant byte is stored at the lowest address. Words, however, are stored in little-endian order, i.e. the least significant word is stored at the lowest address.


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11.5 RSA/SM2 Accelerator Module Operation

The RSA/SM2 Accelerator module is intended to speed-up cryptographic (encoding/decoding) operations that use the RSA or SM2 algorithms. The performance speed-up (relative to software implementation) is achieved through the use of a set of large-size (defined in Section 11.4.1) integer arithmetic (and other) commands, which are defined Section 11.4.2.

11.5.1 Command Execution

The commands defined in Table 11-5 (Section 11.4.2) can all be executed simply by writing the appropriate command code to the CMD field. Before or while doing this, operand source and destination registers must be specified in the OP1, OP2 and DEST fields, and appropriate operand values must have been written (or copied) to the relevant operand registers.

Subsequent commands should be executed only after the previous command has been completed. This can either be immediately, after a few clock cycles, or after many clock cycles. Command timing is detailed in Table 11-6.

For those commands that have short, predictable duration, such as move or add commands, software may be structured such that commands are initiated in succession (e.g. timed as needed with the use of NOP/SYNC CPU instructions).

For those commands that have long, unpredictable duration, such as multiply or exponentiation commands, software should enter a low-power mode (doze, wait or stop) after issuing the command, and wait for an interrupt from the RSA/SM2 Accelerator module to wake-up from the low-power mode and continue program execution.

In theory, polling of the busy-status of the RSA/SM2 Accelerator module could also be used to determine when the current operation is finished and the next

167


command could be issued, however, this is not a good method, because it is slower and uses more power.

In the (variable-length) Command Timing in Table 11-6, the parameter N is used to indicate the operand-size, as defined in Section 11.4.1, i.e. 192, 256, 512, 1024 or 2048 bits.

Table 11-6 Command Timing

Command Cycles

Min Typ Max

NOP 1

ADDS 1

ADD1S 1

SUBS 1

DECS 1

ADDM 1 3

SUBM 1 2

FF1 1 N/64

SHL 1

SHR 1

MULS 2N + N/64

MULM 2N + N/64 5N + N/64 + 2

MPR N + N/64 2N + N/64 + 2

MINV 6 + 3N + 1.016N2 5 + 7.016N + 2.285N2 5 + 9.016N + 4.0313N2

EXPF 54 + 19.5N 2 + 7.016N + 2.285N2 2 + 9.016N + 4.0313N2

MRES N 3N

11.5.2 Other Algorithm Support

The RSA/SM2 Accelerator module is designed primarily to speed-up "normal" RSA and SM2 cryptographic operations, in particular encoding and decoding transforms.

The RSA/SM2 Accelerator module is specifically NOT intended to completely automate the whole cryptographic process, but merely to improve the performance of the (software) application by implementing some of the more frequently used computations in hardware.

168


Operations other than volume encryption/decryption, such as key-pair generation, are expected to be performed by software, possibly with limited support from (other) hardware. The RSA/SM2 Accelerator module can perhaps be used for this as well, but only as long as certain conditions are met.

The RSA/SM2 Accelerator module makes certain assumptions (that are quite valid for "normal" RSA and SM2 operation), which may limit its use for other operations:

For most modular commands, the modulus is assumed to be a full N-bit number, i.e. the most significant bit of the modulus is set (1).

For modular exponentiation, the modulus is expected to be odd, i.e. the least significant bit of the modulus is set (1).

For modular inversion, the modulus is expected to be a prime number.

Normal operands (A, B, Y, etc) are assumed to be less than the modulus.

Note that given the above assumptions, "normal" cryptographic (encode/ decode) operations can be implemented in hardware, but support for other operations is limited.

For example, in RSA encryption/decryption, the full-size modulus requirement is met by default (N-bit RSA requires by convention that the Nth bit is set, i.e. 1011 would be a proper 4-bit RSA modulus, but 0111 is not) and the odd-modulus requirement is also met, because the modulus is a product of two large prime numbers, which is odd.

Calculating the "totient" T = (P-1)(Q-1), which is needed for key-pair generation, can be done in hardware using the scalar multiplication command, but finding the private exponent D = 1/E mod T cannot be done through the modular-inversion command of the RSA/SM2 Accelerator module because T is an even (not prime) number.

For other algorithms, such as the Chinese Remainder Theorem (CRT), Extended Euclidean Algorithm (EEA) and various Primality Tests, only those parts that meet the requirements (e.g. odd or prime modulus) can be implemented using the RSA/SM2 Accelerator Module.

Given the fact that in "normal" cryptography, the bulk of the computations are concerned with encoding and/or decoding (while key-pair generation might occur infrequently, possibly only once), the limitations (operand restrictions) of the RSA/SM2 Accelerator module are considered acceptable.

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Section 12 Watchdog Timer Module

12.1 Introduction

The watchdog timer is a 16-bit timer used to help software recover from runaway code. The watchdog timer has a free-running down-counter (watchdog counter) that generates a reset on underflow. To prevent a reset, software must periodically restart the countdown by servicing the watchdog.


This subsection describes the operation of the watchdog timer in low-power modes and debug mode of operation.

12.2.1 Wait Mode

In wait mode with the WAIT bit set in the Watchdog Control Register (WCR), watchdog timer operation stops. In wait mode with the WAIT bit clear, the watchdog timer continues to operate normally.

12.2.2 Doze Mode

In doze mode with the DOZE bit set in WCR, watchdog timer module operation stops. In doze mode with the DOZE bit clear, the watchdog timer continues to operate normally.

12.2.3 Stop Mode

The watchdog operation stops in stop mode. When stop mode is exited, the watchdog operation continues operation from the state it was in prior to entering stop mode.

12.2.4 Debug Mode

In debug mode with the DBG bit set in WCR, watchdog timer module operation stops. In debug mode with the DBG bit clear, the watchdog timer continues to operate normally. When debug mode is exited, watchdog timer operation continues from the state it was in before entering debug mode, but any updates made in debug mode remain.

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12.3 Block Diagram

Figure 12-1 Watchdog Timer Block Diagram

12.4 Signals

The watchdog timer module has no off-chip signals.


This subsection describes the memory map and registers for the watchdog timer. The watchdog timer has a base address of 0x00c7_0000.

12.5.1 Memory Map

Refer Table 12-1 to for an overview of the watchdog memory map.

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Table 12-1 Watchdog Timer Module Memory Map

Address Bits 15-8 Bits 7-0 Access(18

0x00c7_0000

)

Watchdog Control Register (WCR) S

0x00c7_0002 Watchdog Modulus Register (WMR) S

0x00c7_0004 Watchdog Count Register (WCNTR) S/U

0x00c7_0006 Watchdog Service Register (WSR) S/U

12.5.2 Registers

The watchdog timer programming model consists of these registers:

The Watchdog Control Register (WCR) configures watchdog timer operation. See 12.5.2.1 Watchdog Control Register.

The Watchdog Modulus Register (WMR) determines the timer modulus reload value. See 12.5.2.2 Watchdog Modules Register.

The Watchdog Count Register (WCNTR) provides visibility to the watchdog counter value. See 12.5.2.3 Watchdog Count Register.

The Watchdog Service Register (WSR) requires a service sequence to prevent reset. See 12.5.2.4 Watchdog Service Register.

12.5.2.1 Watchdog Control Register

The 16-bit read/write Watchdog Control Register (WCR) configures watchdog timer operation.

18S = CPU supervisor mode access only. S/U = CPU supervisor or user mode access. User mode


error.

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Address : 0x00c7_0000 and 0x00c7_0001

15 14 13 12 11 10 9 8

R 0 0 0 0 0 0 0 0

W

RESET: 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

R 0 0 0 0 WAIT DOZE DBG EN

W

RESET: 0 0 0 0 1 1 1 1


Figure 12-2 Watchdog Control Register (WCR)

WAIT — Wait Mode Bit The read-always, write-once WAIT bit controls the function of the watchdog timer in wait mode. Once written, the WAIT bit is not affected by further writes except in debug mode. Reset sets WAIT.

1= Watchdog timer stopped in wait mode 0= Watchdog timer not affected in wait mode

DOZE — Doze Mode Bit The read-always, write-once DOZE bit controls the function of the watchdog timer in doze mode. Once written, the DOZE bit is not affected by further writes except in debug mode. Reset sets DOZE.

1= Watchdog timer stopped in doze mode 0= Watchdog timer not affected in doze mode

DBG — Debug Mode Bit The read-always, write-once DBG bit controls the function of the watchdog timer in debug mode. Once written, the DBG bit is not affected by further writes except in debug mode. During debug mode, watchdog timer registers can be written and read normally. When debug mode is exited, timer operation continues from the state it was in before entering debug mode, but any updates made in debug mode remain. If a write-once register is written for the first time in debug mode, the register is still writable when debug mode is exited.

1= Watchdog timer stopped in debug mode 0= Watchdog timer not affected in debug mode

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NOTE: Changing the DBG bit from 1 to 0 during debug mode starts the watchdog timer. Changing the DBG bit from 0 to 1 during debug mode stops the watchdog timer.

EN — Watchdog Enable Bit The read-always, write-once EN bit enables the watchdog timer. Once written, the EN bit is not affected by further writes except in debug mode. When the watchdog timer is disabled, the watchdog counter and prescaler counter are held in a stopped state.

1= Watchdog timer enabled 0= Watchdog timer disabled

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12.5.2.2 Watchdog Modules Register

Address : 0x00c7_0002 and 0x00c7_0003

15 14 13 12 11 10 9 8

R WM15 WM14 WM13 WM12 WM11 WM10 WM9 WM8

W

RESET: 1 1 1 1 1 1 1 1

7 6 5 4 3 2 1 0

R WM7 WM6 WM5 WM4 WM3 WM2 WM1 WM0

W

RESET: 1 1 1 1 1 1 1 1

Figure 12-3 Watchdog Modulus Register (WMR)

WM[15:0] — Watchdog Modulus Field The read-always, write-once WM[15:0] field contains the modulus that is reloaded into the watchdog counter by a service sequence. Once written, the WM[15:0] field is not affected by further writes except in debug mode. Writing to WMR immediately loads the new modulus value into the watchdog counter. The new value is also used at the next and all subsequent reloads. Reading WMR returns the value in the modulus register. Reset initializes the WM[15:0] field to 0xFFFF.

NOTE: The prescaler counter is reset anytime a new value is loaded into the watchdog counter and also during reset.

175


12.5.2.3 Watchdog Count Register

Address : 0x00c7_0004 and 0x00c7_0005

15 14 13 12 11 10 9 8

R WC15 WC14 WC13 WC12 WC11 WC10 WC9 WC8

W

RESET: 1 1 1 1 1 1 1 1

7 6 5 4 3 2 1 0

R WC7 WC6 WC5 WC4 WC3 WC2 WC1 WC0

W

RESET: 1 1 1 1 1 1 1 1


Figure 12-4 Watchdog Count Register (WCNTR)

WC[15:0] — Watchdog Count Field The read-only WC[15:0] field reflects the current value in the watchdog counter. Reading the 16-bit WCNTR with two 8-bit reads is not guaranteed to return a coherent value. Writing to WCNTR has no effect, and write cycles are terminated normally.

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12.5.2.4 Watchdog Service Register

When the watchdog timer is enabled, writing 0x5555 and then 0xAAAA to the Watchdog Service Register (WSR) before the watchdog counter times out prevents a reset. If WSR is not serviced before the timeout, the watchdog timer sends a signal to the reset controller module which sets the WDR bit and asserts a system reset.

Both writes must occur in the order listed before the timeout, but any number of instructions can be executed between the two writes. However, writing any value other than 0x5555 or 0xAAAA to WSR resets the servicing sequence, requiring both values to be written to keep the watchdog timer from causing a reset.

Address : 0x00c7_0006 and 0x00c7_0007

15 14 13 12 11 10 9 8

R WS15 WS14 WS13 WS12 WS11 WS10 WS9 WS8

W

RESET: 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

R WS7 WS6 WS5 WS4 WS3 WS2 WS1 WS0

W

RESET: 0 0 0 0 0 0 0 0

Figure 12-5 Watchdog Service Register (WSR)

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Section 13 Programmable Interrupt Timer Modules

(PIT1/2)

13.1 Introduction

The programmable interrupt timer (PIT) is a 16-bit timer that provides precise interrupts at regular intervals with minimal processor intervention. The timer can either count down from the value written in the modulus latch, or it can be a free-running down-counter.

13.2 Block Diagram

Figure 13-1 PIT Block Diagram

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This subsection describes the three low-power modes and the debug mode.

13.3.1 Wait Mode

In wait mode, the PIT module continues to operate normally and can be configured to exit the low-power mode by generating an interrupt request.

13.3.2 Doze Mode

In doze mode with the PDOZE bit set in the PIT Control and Status Register (PCSR), PIT module operation stops. In doze mode with the PDOZE bit clear, doze mode does not affect PIT operation. When doze mode is exited, PIT operation continues from the state it was in before entering doze mode.

13.3.3 Stop Mode

In stop mode, the system clock is absent, and PIT module operation stops.

13.3.4 Debug Mode

In debug mode with the PDBG bit set in PCSR, PIT module operation stops. In debug mode with the PDBG bit clear, debug mode does not affect PIT operation. When debug mode is exited, PIT operation continues from the state it was in before entering debug mode, but any updates made in debug mode remain.

13.4 Signals

The PIT module has no off-chip signals.


This subsection describes the memory map and register structure for PIT.

13.5.1 Memory Map

Refer to Table 13-1 for a description for the memory map.

This device has two programmable interrupt timers. PIT has a base address located at 0x00c8_0000.

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Table 13-1 Programmable Interrupt Timer Module Memory Map PIT1

Address PIT2


0x00c8_0000

)

0x00c9_0000 PIT Control and Status Register (PCSR) S

0x00c8_0002 0x00c9_0002 PIT Modulus Register (PMR) S

0x00c8_0004 0x00c9_0004 PIT Count Register (PCNTR) S/U

0x00c8_0006 0x00c9_0006 Unimplemented(20 — )

13.5.2 Registers

The PIT programming model consists of these registers:

The PIT Control and Status Register (PCSR) configures the timer’s operation. See 13.5.2.1 PIT Control and Status Register.

The PIT Modulus Register (PMR) determines the timer modulus reload value. See 13.5.2.2 PIT Modulus Register.

The PIT Count Register (PCNTR) provides visibility to the counter value. See 13.5.2.3 PIT Count Register.

13.5.2.1 PIT Control and Status Register

Address : PIT1 — 0x00c8_0000 and 0x00c8_0001

15 14 13 12 11 10 9 8

R 0 0 0 0 PRE3 PRE2 PRE1 PRE0

W

RESET: 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0



error. 20Accesses to unimplemented address locations have no effect and result in a cycle termination

transfer error.

180


R 0 PDOZE PDBG OVW PIE PIF RLD EN

W

RESET: 0 0 0 0 0 0 0 0


Figure 13-2 PIT Control and Status Register (PCSR)

PRE[3:0] — Prescaler Bits The read/write PRE[3:0] bits select the system clock divisor to generate the PIT clock as Table 13-2 shows. To accurately predict the timing of the next count, change the PRE[3:0] bits only when the enable bit (EN) is clear. Changing the PRE[3:0] resets the prescaler counter. System reset and the loading of a new value into the counter also reset the prescaler counter. Setting the EN bit and writing to PRE[3:0] can be done in this same write cycle. Clearing the EN bit stops the prescaler counter.

Table 13-2 Prescaler Select Encoding PRE[3:0] System Clock Divisor

0000 1

0001 2

0010 4

0011 8

0100 16

0101 32

0110 64

0111 128

1000 256

1001 512

1010 1,024

1011 2,048

1100 4,096

1101 8,192

1110 16,384

1111 32,768

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PDOZE — Doze Mode Bit The read/write PDOZE bit controls the function of the PIT in doze mode. Reset clears PDOZE.

1= PIT function stopped in doze mode 0= PIT function not affected in doze mode

When doze mode is exited, timer operation continues from the state it was in before entering doze mode.

PDBG — Debug Mode Bit The read/write PDBG bit controls the function of the PIT in debug mode. Reset clears PDBG.

1= PIT function stopped in debug mode 0= PIT function not affected in debug mode

During debug mode, register read and write accesses function normally. When debug mode is exited, timer operation continues from the state it was in before entering debug mode, but any updates made in debug mode remain.

NOTE: Changing the PDBG bit from 1 to 0 during debug mode starts the PIT timer. Likewise, changing the PDBG bit from 0 to 1 during debug mode stops the PIT timer.

OVW — Overwrite Bit The read/write OVW bit enables writing to PMR to immediately overwrite the value in the PIT counter.

1= Writing PMR immediately replaces value in PIT counter. 0= Value in PMR replaces value in PIT counter when count reaches

0x0000.

PIE — PIT Interrupt Enable Bit The read/write PIE bit enables the PIF flag to generate interrupt requests.

1= PIF interrupt requests enabled 0= PIF interrupt requests disabled

PIF — PIT Interrupt Flag The read/write PIF flag is set when the PIT counter reaches 0x0000. Clear PIF by writing a 1 to it or by writing to PMR. Writing 0 has no effect. Reset clears PIF.

1= PIT count has reached 0x0000. 0= PIT count has not reached 0x0000.

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RLD — Reload Bit The read/write RLD bit enables loading the value of PMR into the PIT counter when the count reaches 0x0000.

1= Counter reloaded from PMR on count of 0x0000 0= Counter rolls over to 0xFFFF on count of 0x0000

EN — PIT Enable Bit The read/write EN bit enables PIT operation. When the PIT is disabled, the counter and prescaler are held in a stopped state.

1= PIT enabled 0= PIT disabled

13.5.2.2 PIT Modulus Register

The 16-bit read/write PIT Modulus Register (PMR) contains the timer modulus value for loading into the PIT counter when the count reaches 0x0000 and the RLD bit is set.

When the OVW bit is set, PMR is transparent, and the value written to PMR is immediately loaded into the PIT counter. The prescaler counter is reset anytime a new value is loaded into the PIT counter and also during reset. Reading the PMR returns the value written in the modulus latch. Reset initializes PMR to 0xFFFF.

Address : PIT1 — 0x00c8_0002 and 0x00c8_0003

15 14 13 12 11 10 9 8

R PM15 PM14 PM13 PM12 PM11 PM10 PM9 PM8

W

RESET: 1 1 1 1 1 1 1 1

7 6 5 4 3 2 1 0

R PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0

W

RESET: 1 1 1 1 1 1 1 1

Figure 13-3 PIT Modulus Register (PMR)

183


13.5.2.3 PIT Count Register

The 16-bit, read-only PIT Control Register (PCNTR) contains the counter value. Reading the 16-bit counter with two 8-bit reads is not guaranteed to be coherent. Writing to PCNTR has no effect, and write cycles are terminated normally.

Address : PIT1 — 0x00c8_0004 and 0x00c8_0005 PIT2 — 0x00c9_0004 and 0x00c9_0005

15 14 13 12 11 10 9 8

R PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8

W

RESET: 1 1 1 1 1 1 1 1

7 6 5 4 3 2 1 0

R PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

W

RESET: 1 1 1 1 1 1 1 1


Figure 13-4 PIT Count Register (PCNTR)


This subsection describes the PIT functional operation.

13.6.1 Set-and-Forget Timer Operation

This mode of operation is selected when the RLD bit in the PCSR register is set.

When the PIT counter reaches a count of 0x0000, the PIF flag is set in PCSR. The value in the modulus latch is loaded into the counter, and the counter begins decreasing toward 0x0000. If the PIE bit is set in PCSR, the PIF flag issues an interrupt request to the CPU.

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When the OVW bit is set in PCSR, the counter can be directly initialized by writing to PMR without having to wait for the count to reach 0x0000.

Figure 13-5 Counter Reloading from the Modulus latch

13.6.2 Free-Running Timer Operation

This mode of operation is selected when the RLD bit in PCSR is clear. In this mode, the counter rolls over from 0x0000 to 0xFFFF without reloading from the modulus latch and continues to decrement.

When the counter reaches a count of 0x0000, the PIF flag is set in PCSR. If the PIE bit is set in PCSR, the PIF flag issues an interrupt request to the CPU.

When the OVW bit is set in PCSR, the counter can be directly initialized by writing to PMR without having to wait for the count to reach 0x0000.

Figure 13-6 Counter in Free-Running Mode

13.6.3 Timeout Specifications

The 16-bit PIT counter and prescaler supports different timeout periods. The prescaler divides the system clock as selected by the PRE[3:0] bits in PCSR. The PM[15:0] bits in PMR select the timeout period.

185


13.7 Interrupt Operation

Table 13-3 lists the interrupt requests generated by the PIT.

Table 13-3 PIT Interrupt Requests Interrupt Request Flag Enable Bit

Timeout PIF PIE

The PIF flag is set when the PIT counter reaches 0x0000. The PIE bit enables the PIF flag to generate interrupt requests. Clear PIF by writing a 1 to it or by writing to the PMR.

186


Section 14 Serial Communications Interface Modules

(SCI1/2)

14.1 Introduction

The serial communications interface (SCI) allows asynchronous serial communications with peripheral devices and other microcontroller units (MCU).

14.2 Features

Features of each SCI module include:

Full-duplex operation

Standard mark/space non-return-to-zero (NRZ) format

13-bit baud rate selection

Programmable 8-bit or 9-bit data format

Separately enabled transmitter and receiver

Separate receiver and transmitter central processor unit (CPU) interrupt requests

Programmable transmitter output polarity

Two receiver wakeup methods:

- Idle line wakeup

- Address mark wakeup

Interrupt-driven operation with eight flags:

- Transmitter empty

- Transmission complete

- Receiver full

- Idle receiver input

- Receiver overrun

- Noise error

- Framing error

- Parity error

187


Receiver framing error detection

Hardware parity checking

1/16 bit-time noise detection

General-purpose, I/O capability

14.3 Block Diagram

Figure 14-1 SCI Block Diagram

188



SCI operation is identical in run, special, and emulation modes. The SCI has two low-power modes, doze and stop.

NOTE: Run mode is the normal mode of operation and the WAIT instruction does not affect SCI operation.

14.4.1 Doze Mode

When the SCIDOZ bit in the SCI Pullup and Reduced Drive (SCIPURD) Register is set, the DOZE instruction stops the SCI clock and puts the SCI in a low-power state. The DOZE instruction does not affect SCI register states. Any transmission or reception in progress stops at doze mode entry and resumes when an internal or external interrupt request brings the CPU out of doze mode. Exiting doze mode by reset aborts any transmission or reception in progress and resets the SCI. See 14.6.7 SCI Pullup and Reduced Drive Register.

When the SCIDOZ bit is clear, execution of the DOZE instruction has no effect on the SCI. Normal module operation continues, allowing any SCI interrupt to bring the CPU out of doze mode.

14.4.2 Stop Mode

The STOP instruction stops the SCI clock and puts the SCI in a low-power state. The STOP instruction does not affect SCI register states. Any transmission or reception in progress halts at stop mode entry and resumes when an external interrupt request brings the CPU out of stop mode. Exiting stop mode by reset aborts any transmission or reception in progress and resets the SCI.

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Table 14-1 gives an overview of the signals which are described here.


Name Function Port Reset State Default Pullup State

RXD Receive data pin SCIPORT0 0 Disabled

TXD Transmit data

pin SCIPORT1 0 Disabled

14.5.1 RXD

RXD is the SCI receiver pin. RXD is available for general-purpose I/O when it is not configured for receiver operation.

14.5.2 TXD

TXD is the SCI transmitter pin. TXD is available for general-purpose I/O when it is not configured for transmitter operation.

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Table 14-2 shows the SCI memory map.

NOTE: Reading unimplemented addresses (0x00ca_000b through 0x00ca_000f and 0x00cb_000b through 0x00cb_000f ) returns 0s. Writing to unimplemented addresses has no effect. Accessing unimplemented addresses does not generate an error response.

Table 14-2 Serial Communications Interface Module Memory Map1

SCI1 SCI2 Bits 7–0 Access2

0x00ca_0000 0x00cb_0000 SCI Baud Register High (SCIBDH) S/U

0x00ca_0001 0x00cb_0001 SCI Baud Register Low (SCIBDL) S/U

0x00ca_0002 0x00cb_0002 SCI Control Register 1 (SCICR1) S/U

0x00ca_0003 0x00cb_0003 SCI Control Register 2 (SCICR2) S/U

0x00ca_0004 0x00cb_0004 SCI Status Register 1 (SCISR1) S/U

0x00ca_0005 0x00cb_0005 SCI Status Register 2 (SCISR2) S/U

0x00ca_0006 0x00cb_0006 SCI Data Register High (SCIDRH) S/U

0x00ca_0007 0x00cb_0007 SCI Data Register Low (SCIDRL) S/U

0x00ca_0008 0x00cb_0008 SCI Pullup and Reduced Drive Register (SCIPURD) S/U

0x00ca_0009 0x00cb_0009 SCI Port Data Register (SCIPORT) S/U

0x00ca_000a 0x00cb_000a SCI Data Direction Register (SCIDDR) S/U

0x00ca_000b

|

0x00ca_000f

00x00cb_000b

|

0x00cb_000f

Reserved3 S/U

1. Each module is assigned 64K bytes of address space, all of which may not be decoded. Accesses

outside of the specified module memory map generate a bus error exception.

2. S/U = CPU supervisor or user mode access. User mode accesses to supervisor only addresses

have no effect and result in a cycle termination transfer error.

3. Within the specified module memory map, accessing reserved addresses does not generate a bus

error exception. Reads of reserved addresses return 0s and writes have no effect

191


14.6.1 SCI Baud Rate Registers

Address: SCI1 0 00 0000 SCI2 0 00 b 0000

Bit7 6 5 4 3 2 1 Bit0

Read: 0 0 0 SBR12 SBR11 SBR10 SBR9 SBR8

Write:

RESET: 0 0 0 0 0 0 0 0


Figure 14-2 SCI Baud Rate Register High (SCIBDH)

Address: SCI1 0 00 0001 SCI2 0 00 b 0001

Bit7 6 5 4 3 2 1 Bit0

Read: SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0

Write:

RESET: 0 0 0 0 0 1 0 0

Figure 14-3 SCI Baud Rate Register Low (SCIBDL)

Read: Anytime

Write: Anytime

SBR[12:8], SBR[7:0] — SCI Baud Rate Bits These read/write bits control the SCI baud rate:

SCIbaudratefsys

16 SBR 12:0[ ]×--------------------------=

where: 1 SBR[12:0] 8191≤ ≤

NOTE: The baud rate generator is disabled until the TE bit or the RE bit in SCICR2 is set for the first time after reset. The baud rate generator is disabled when SBR[12:0] = 0.

Writing to SCIBDH has no effect without also writing to SCIBDL. Writing to SCIBDH puts the data in a temporary location until data is written to SCIBDL.

192


14.6.2 SCI Control Register 1

Address: SCI1 : 0x00ca_0002; SCI2 : 0x00cb_0002;

Bit7 6 5 4 3 2 1 Bit0

Read: LOOPS WMS RSRC M WAKE ILT PE PT

Write:

RESET: 0 0 0 0 0 0 0 0

Figure 14-4 SCI Control Register 1 (SCICR1)

Read: Anytime

Write: Anytime

LOOPS — Loop Select Bit This read/write control bit switches the SCI between normal mode and loop mode. Reset clears LOOPS.

1= Loop mode SCI operation 0= Normal mode SCI operation

The SCI operates normally (LOOPS = 0, RSRC = X) when the output of its transmitter is connected to the TXD pin, and the input of its receiver is connected to the RXD pin. In loop mode (LOOPS =1, RSRC = 0), the input to the SCI receiver is internally disconnected from the RXD pin logic and instead connected to the output of the SCI transmitter. The behavior of TXD is governed by the DDRSC1 bit in SCIDDR. If DDRSC1 = 1, the TXD pin is driven with the output of the SCI transmitter. If DDRSC1 = 0, the TXD pin idles high. See 14.13 Loop Operation for additional information. For either loop mode or single-wire mode to function, both the SCI receiver and transmitter must be enabled by setting the RE and TE bits in SCIxCR2.

NOTE: The RXD pin becomes general-purpose I/O when LOOPS = 1, regardless of the state of the RSRC bit. DDRSC0 in SCIDDR is the data direction bit for the RXD pin.

Table 14-3 shows how the LOOPS, RSRC, and DDRSC0 bits affect SCI operation and the configuration of the RXD and TXD pins.

193


Table 14-3 SCI Normal, Loop, and Single-Wire Mode Pin Configurations

LOOPS

RSRC

SCI MODE

Receiver Input

RXD Pin

Func.

DDRSC 0

Transmitter Output

TXD Pin

Function

0 X Normal Tied to RXD

input buffer

Receive pin

X Tied to TXD output driver

Transmit pin

1

0 Loop Tied to transmitter output General

-purpose I/O

0 Tied to receiver input only

None (idles high)

1

Tied to receiver

input and TXD output driver

Transmit pin

1 Single-wire Tied to TXD

0 No connection Receive pin

1 Tied to TXD

output driver Transmit pin

WMS — Wired Mode Select Bit This read/write bit configures the TXD and RXD pins for open-drain operation. This allows all of the TXD pins to be tied together in a multiple-transmitter system. WMS also affects the TXD and RXD pins when they are general-purpose outputs. External pullup resistors are necessary on open-drain outputs. Reset clears WMS.

1= TXD and RXD pins open-drain when outputs 0= TXD and RXD pins CMOS drive when outputs

NOTE: This bit has no effect in this part. Thus wired-AND mode is not supported.

RSRC — Receiver Source Bit This read/write bit selects the internal feedback path to the receiver input when LOOPS = 1. Reset clears RSRC.

1= Receiver input tied to TXD pin when LOOPS = 1 0= Receiver input tied to transmitter output when LOOPS = 1

194


M — Data Format Mode Bit This read/write bit selects 11-bit or 10-bit frames. Reset clears M.

1= Frames have 1 start bit, 9 data bits, and 1 stop bit. 0= Frames have 1 start bit, 8 data bits, and 1 stop bit.

WAKE — Wakeup Bit This read/write bit selects the condition that wakes up the SCI receiver when it has been placed in a standby state by setting the RWU bit in SCICR2. When WAKE is set, a logic 1 (address mark) in the most significant bit position of a received data character wakes the receiver. An idle condition on the RXD pin does so when WAKE = 0. Reset clears WAKE.

1= Address mark receiver wakeup 0= Idle line receiver wakeup

ILT — Idle Line Type Bit This read/write bit determines when the receiver starts counting logic 1s as idle character bits. The counting begins either after the start bit or after the stop bit. If the count begins after the start bit, then a string of logic 1s preceding the stop bit may cause false recognition of an idle character. Beginning the count after the stop bit avoids false idle character recognition, but requires properly synchronized transmissions. Reset clears ILT.

1= Idle frame bit count begins after stop bit. 0= Idle frame bit count begins after start bit.

PE — Parity Enable Bit This read/write bit enables the parity function. When enabled, the parity function inserts a parity bit in the most significant bit position of an SCI data word. Reset clears PE.

1= Parity function enabled 0= Parity function disabled

PT — Parity Type Bit This read/write bit selects even parity or odd parity. With even parity, an even number of 1s clears the parity bit and an odd number of 1s sets the parity bit. With odd parity, an odd number of 1s clears the parity bit and an even number of 1s sets the parity bit. Reset clears PT.

1= Odd parity when PE = 1 0= Even parity when PE = 1

195


14.6.3 SCI Control Register 2


Bit7 6 5 4 3 2 1 Bit0

Read: TIE TCIE RIE ILIE TE RE RWU SBK

Write:

RESET: 0 0 0 0 0 0 0 0

Figure 14-5 SCI Control Register 2 (SCICR2)

Read: Anytime

Write: Anytime

TIE — Transmitter Interrupt Enable Bit This read/write bit allows the TDRE flag to generate interrupt requests. Reset clears TIE.

1= TDRE interrupt requests enabled 0= TDRE interrupt requests disabled

TCIE — Transmission Complete Interrupt Enable Bit This read/write bit allows the TC flag to generate interrupt requests. Reset clears TCIE.

1= TC interrupt requests enabled 0= TC interrupt requests disabled

RIE — Receiver Interrupt Enable Bit This read/write bit allows the RDRF and OR flags to generate interrupt requests. Reset clears RIE.

1= RDRF and OR interrupt requests enabled 0= RDRF and OR interrupt requests disabled

ILIE — Idle Line Interrupt Enable Bit This read/write bit allows the IDLE flag to generate interrupt requests. Reset clears ILIE.

1= DLE interrupt requests enabled 0= IDLE interrupt requests disabled

196


TE — Transmitter Enable Bit This read/write bit enables the transmitter and configures the TXD pin as the transmitter output. Toggling TE queues an idle frame. Reset clears TE.

1= Transmitter enabled 0= Transmitter disabled

RE — Receiver Enable Bit This read/write bit enables the receiver. Reset clears RE.

1= Receiver enabled 0= Receiver disabled

NOTE: When LOOPS = 0 and TE = RE = 1, the RXD pin is an input and the TXD pin is an output regardless of the state of the DDRSC1 (TXD) and DDRSC0 (RXD) bits.

RWU — Receiver Wakeup Bit This read/write bit puts the receiver in a standby state that inhibits receiver interrupt requests. The WAKE bit determines whether an idle input or an address mark wakes up the receiver and clears RWU. Reset clears RWU.

1= Receiver asleep when RE = 1 0= Receiver awake when RE = 1

SBK — Send Break Bit Setting this read/write bit causes the SCI to send break frames of 10 (M = 0) or 11 (M =1) logic 0s. To send one break frame, set SBK and then clear it before the break frame is finished transmitting. As long as SBK is set, the transmitter continues to send break frames.

1= Transmitter sends break frames. 0= Transmitter does not send break frames.

197


14.6.4 SCI Status Register 1

Address:

Bit7 6 5 4 3 2 1 Bit0

Read: TDRE TC RDRF IDLE OR NF FE PF

Write:

RESET: 1 1 0 0 0 0 0 0


Figure 14-6 SCI Status Register 1 (SCISR1)

Read: Anytime

Write: Has no meaning or effect

TDRE — Transmit Data Register Empty Flag The TDRE flag is set when the transmit shift register receives a word from the SCI Data Register. It signals that the SCIDRH and SCIDRL are empty and can receive new data to transmit. If the TIE bit in the SCICR2 is also set, TDRE generates an interrupt request. Clear TDRE by reading SCISR1 and then writing to SCIDRL. Reset sets TDRE.

1= Transmit data register empty 0= Transmit data register not empty

TC — Transmit Complete Flag The TC flag is set when TDRE = 1 and no data, preamble, or break frame is being transmitted. It signals that no transmission is in progress. If the TCIE bit is set in SCICR2, TC generates an interrupt request. When TC is set, the TXD pin is idle (logic 1). TC is cleared automatically when a data, preamble, or break frame is queued. Clear TC by reading SCISR1 with TC set and then writing to SCIDRL. TC cannot be cleared while a transmission is in progress. Reset sets TC.

1= No transmission in progress 0= Transmission in progress

RDRF — Receive Data Register Full Flag The RDRF flag is set when the data in the receive shift register is transferred to SCIDRH and SCIDRL. It signals that the received data is available to the MCU. If the RIE bit is set in SCICR2, RDRF generates an

198


interrupt request. Clear RDRF by reading the SCISR1 and then reading SCIDRL. Reset clears RDRF.

1= Received data available in SCIDRH and SCIDRL 0= Received data not available in SCIDRH and SCIDRL

IDLE — Idle Line Flag The IDLE flag is set when 10 (if M = 0) or 11 (if M = 1) consecutive logic 1s appear on the receiver input. If the ILIE bit in SCICR2 is set, IDLE generates an interrupt request. Once IDLE is cleared, a valid frame must again set the RDRF flag before an idle condition can set the IDLE flag. Clear IDLE by reading SCISR1 and then reading SCIDRL. Reset clears IDLE.

1= Receiver idle 0= Receiver active or idle since reset or idle since IDLE flag last cleared

NOTE: When RWU of SCICR2 =1, an idle line condition does not set the IDLE flag.

OR — Overrun Flag The OR flag is set if data is not read from SCIDRL before the receive shift register receives the stop bit of the next frame. This is a receiver overrun condition. If the RIE bit in SCICR2 is set, OR generates an interrupt request. The data in the shift register is lost, but the data already in the SCIDRH and SCIDRL is not affected. Clear OR by reading SCISR1 and then reading SCIDRL. Reset clears OR.

1= Overrun 0= No overrun

NF — Noise Flag The NF flag is set when the SCI detects noise on the receiver input. NF is set during the same cycle as the RDRF flag but does not get set in the case of an overrun. Clear NF by reading SCISR1 and then reading SCIDRL. Reset clears NF.

1= Noise 0= No noise

FE — Framing Error Flag The FE flag is set when a logic 0 is accepted as the stop bit. FE is set during the same cycle as the RDRF flag but does not get set in the case of an overrun. FE inhibits further data reception until it is cleared. Clear FE by reading SCISR1 and then reading SCIDRL. Reset clears FE.

1= Framing error 0= No framing error

199


PF — Parity Error Flag The PF flag is set when PE = 1 and the parity of the received data does not match its parity bit. Clear PF by reading SCISR1 and then reading SCIDRL. Reset clears PF.

1= Parity error 0= No parity error

14.6.5 SCI Status Register 2


Bit7 6 5 4 3 2 1 Bit0

Read: 0 0 0 0 0 0 0 RAF

Write:

RESET: 0 0 0 0 0 0 0 0


Figure 14-7 SCI Status Register 2 (SCISR2)

Read: Anytime

Write: Has no meaning or effect

RAF — Receiver Active Flag The RAF flag is set when the receiver detects a logic 0 during the RT1 time period of the start bit search. When the receiver detects an idle character, it clears RAF. Reset clears RAF.

1= Reception in progress 0= No reception in progress

200


14.6.6 SCI Data Registers


Bit7 6 5 4 3 2 1 Bit0

Read: R8 T8

0 0 0 0 0 0

Write:

RESET: 0 0 0 0 0 0 0 0


Figure 14-8 SCI Data Register High (SCIDRH)


Bit7 6 5 4 3 2 1 Bit0

Read: R7 R6 R5 R4 R3 R2 R1 R0

Write: T7 T6 T5 T4 T3 T2 T1 T0

RESET: 0 0 0 0 0 0 0 0

Figure 14-9 SCI Data Register Low (SCIDRL)

Read: Anytime

Write: Anytime; writing to R8 has no effect

R8 — Receive Bit 8 The R8 bit is the ninth received data bit when using the 9-bit data format (M = 1). Reset clears R8.

T8 — Transmit Bit 8 The T8 bit is the ninth transmitted data bit when using the 9-bit data format (M = 1). Reset clears T8.

R[7:0] — Receive Bits [7:0] The R[7:0] bits are receive bits [7:0] when using the 9-bit or 8-bit data format. Reset clears R[7:0].

201


T[7:0] — Transmit Bits [7:0] The T[7:0] bits are transmit bits [7:0] when using the 9-bit or 8-bit data format. Reset clears T[7:0].

NOTE: If the value of T8 is the same as in the previous transmission, T8 does not have to be rewritten. The same value is transmitted until T8 is rewritten.

When using the 8-bit data format, only SCIDRL needs to be accessed. When using 8-bit write instructions to transmit 9-bit data, write first to SCIDRH, then to SCIDRL.

14.6.7 SCI Pullup and Reduced Drive Register


Bit7 6 5 4 3 2 1 Bit0

Read: SCISDOZ

0 RSVD5 RDPSCI

0 0 RSVD1 PUPSCI

Write:

RESET: 0 0 0 0 0 0 0 0


Figure 14-10 SCI Pullup and Reduced Drive Register (SCIPURD)

Write: Anytime

SCISDOZ — SCI Stop in Doze Mode Bit The SCISDOZ bit disables the SCI in doze mode.

SCI disabled in doze mode SCI enabled in doze mode

RSVD[5,1] — Reserved Writing to these read/write bits updates their values but has no effect on functionality.

RDPSCI — Reduced Drive Bit This read/write bit controls the drive capability of TXD and RXD.

1= Reduced TXD and RXD pin drive 0= Full TXD and RXD pin drive

202


NOTE: The RDPSCI bit has no effect in this part.

PUPSCI — Pullup Enable Bit This read/write bit enables the pullups on pins TXD and RXD. If a pin is programmed as an output, the pullup is disabled.

1= TXD and RXD pullups enabled 0= TXD and RXD pullups disabled

NOTE: The PUPSCI bit has no effect in this part. Pullups are always enabled.

14.6.8 SCI Port Data Register


Bit 7 6 5 4 3 2 1 Bit 0

Read: RSVD7 RSVD6 RSVD5 RSVD4 RSVD3 RSVD2 PORTSC1 PORTSC0

Write:

RESET: 0 0 0 0 0 0 0 0

Pin function: TXD RXD

Figure 14-11 SCI Port Data Register (SCIPORT)

Read: Anytime; when DDRSCx = 0, its pin is configured as an input, and reading PORTSCx returns the pin level; when DDRSCx = 1, its pin is configured as an output, and reading PORTSCx returns the pin driver output level.

Write: Anytime; data stored in internal latch drives pin only if DDRSC bit = 1

RSVD[7:2] — Reserved Writing to these read/write bits updates their values but has no effect on functionality.

PORTSC[1:0] — SCIPORT Data Bits These are the read/write data bits of the SCI port.

NOTE: Writes to SCIPORT do not change the pin state when the pin is configured for SCI input.

To ensure correct reading of the SCI pin values from SCIPORT, always wait at least one cycle after writing to SCIDDR before reading SCIPORT.

203


14.6.9 SCI Data Direction Register

Address: SCI1 : 0x00ca_000a; SCI2 : 0x00cb_000a;

Bit7 6 5 4 3 2 1 Bit0

Read: RSVD7 RSVD6 RSVD5 RSVD4 RSVD3 RSVD2 DDRSC1 DDRSC0

Write:

RESET: 0 0 0 0 0 0 0 0

Figure 14-12 SCI Data Direction Register (SCIDDR)

Read: Anytime

Write: Anytime

RSVD[7:2] — Reserved Writing to these read/write bits updates their values but has no effect on functionality.

DDRSC[1:0] — SCIPORT Data Direction Bits These bits control the data direction of the SCIPORT pins. Reset clears DDRSC[1:0].

1= Corresponding pin configured as output 0= Corresponding pin configured as input

NOTE: When LOOPS = 0 and TE = RE = 1, the RXD pin is an input and the TXD pin is an output regardless of the state of the DDRSC1 (TXD) and DDRSC0 (RXD) bits.

204



The SCI allows full-duplex, asynchronous, non-return-to-zero (NRZ) serial communication between the MCU and remote devices, including other MCUs. The SCI transmitter and receiver operate independently, although they use the same baud rate generator. The CPU monitors the status of the SCI, writes the data to be transmitted, and processes received data.

14.8 Data Format

The SCI uses the standard NRZ mark/space data format shown in Figure 14-13

Each frame has a start bit, eight or nine data bits, and one or two stop bits. Clearing the M bit in SCCR1 configures the SCI for 10-bit frames. Setting the M bit configures the SCI for 11-bit frames.

When the SCI is configured for 9-bit data, the ninth data bit is the T8 bit in SCI Data Register high (SCIDRH). It remains unchanged after transmission and can be used repeatedly without rewriting it. A frame with nine data bits has a total of 11 bits.

Figure 14-13 SCI Data Formats

14.9 Baud Rate Generation

A 13-bit modulus counter in the baud rate generator derives the baud rate for both the receiver and the transmitter. The value from 0 to 8191 written to SCIBDH and SCIBDL determines the system clock divisor. The baud rate clock is synchronized with the bus clock and drives the receiver. The baud rate clock divided by 16 drives the transmitter. The receiver acquisition rate is 16 samples per bit time.

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Baud rate generation is subject to two sources of error:

1. Integer division of the module clock may not give the exact target frequency

2. Synchronization with the bus clock can cause phase shift.

Table 14-4 Example Baud Rates (System Clock = 33 MHz)

SBR[12:0] Receiver Clock

(Hz) Transmitter Clock

(Hz) Target

Baud Rate Percent

Error

0x0012 1,833,333.3 114,583.3 115,200 0.54

0x0024 916,666.7 57,291.7 57,600 0.54

0x0036 611,111.1 38,194.4 38,400 0.54

0x003d 540,983.6 33,811.4 33,600 0.63

0x0048 458,333.3 28,645.8 28,800 0.54

0x006b 308,411.2 19,275.7 19,200 0.39

0x0008f 230,769.2 14,423.1 14,400 0.16

0x00d7 153,488.4 95,93.0 9,600 0.07

0x01ae 76,744.2 4,796.5 4,800 0.07

0x035b 38,416.8 2,401.0 2,400 0.04

0x06b7 19,197.2 1,199.8 1,200 0.01

0x0d6d 9,601.4 600.1 600 0.01

0x1adb 4,800.0 300.0 300 0

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14.10 Transmitter

Figure 14-14 Transmitter Block Diagram

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14.10.1 Frame Length

The transmitter can generate either 10-bit or 11-bit frames. In SCICR1, the M bit selects frame length, and the PE bit enables the parity function. One data bit may be an address mark or an extra stop bit. All frames begin with a start bit and end with one or two stop bits. When transmitting 9-bit data, bit T8 in SCI Data Register high (SCIDRH) is the ninth bit (bit 8).

Table 14-5 Example 10-Bit and 11-Bit Frames

M Bit Frame Length

Start Bit

Data Bits

Parity Bit

Address

Mark21

Stop Bit(s)

0 10 bits

1 8 No No 1

1 7 No No 2

1 7 No Yes 1

1 7 Yes No 1

1 11 bits

1 9 No No 1

1 8 No No 2

1 8 No Yes 1

1 8 Yes No 1

1 7 No Yes 2

1 7 Yes No 1

21When implementing a multidrop network using the SCI, the address mark bit is used to designate

subsequent data frames as a network address and not device data.

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14.10.2 Transmitting a Frame

To begin an SCI transmission:

1. Configure the SCI:

a. Write a baud rate value to SCIBDH and SCIBDL.

b. Write to SCICR1 to:

i. Enable or disable loop mode and select the receiver feedback path

ii. Select open-drain or wired-AND SCI outputs

iii. Select 10-bit or 11-bit frames

iv. Select the receiver wakeup condition: address mark or idle line

v. Select idle line type

vi. Enable or disable the parity function and select odd or even parity

c. Write to SCICR2 to:

i. Enable or disable TDRE, TC, RDRF, and IDLE interrupt requests

ii. Enable the transmitter and queue a break frame

iii. Enable or disable the receiver

iv. Put the receiver in standby if required

2. Transmit a byte:

a. Clear the TDRE flag by reading SCISR1 and, if sending 9-bit data, write the ninth data bit to SCDRH.

b. Write the byte to be transmitted (or low-order 8 bits if sending 9-bit data) to SCIDRL.

3. Repeat step 2 for each subsequent transmission.

Writing the TE bit from 0 to 1 loads the transmit shift register with a preamble of 10 (if M = 0) or 11 (if M = 1) logic 1s. When the preamble shifts out, the SCI transfers the data from SCIDRH and SCIDRL to the transmit shift register. The transmit shift register prefaces the data with a 0 start bit and appends the data with a 1 stop bit and begins shifting out the frame.

The SCI sets the TDRE flag every time it transfers data from SCIDRH and SCIDRL to the transmit shift register. TDRE indicates that SCIDRH and SCIDRL can accept new data. If the TIE bit is set, TDRE generates an interrupt request.

NOTE: SCIDRH and SCIDRL transfer data to the transmit shift register and sets TDRE 9/16ths of a bit time after the previous frame’s stop bit starts to shift out.

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Hardware supports odd or even parity. When parity is enabled, the most significant data bit is the parity bit.

When the transmit shift register is not transmitting a frame, the TXD pin goes to the idle condition, logic 1. Clearing the TE bit while the transmitter is idle will return control of the TXD pin to the SCI data direction (SCIDDR) and SCI port (SCIPORT) registers.

If the TE bit is cleared while a transmission is in progress (while TC = 0), the frame in the transmit shift register continues to shift out. Then the TXD pin reverts to being a general-purpose I/O pin even if there is data pending in the SCI Data Register. To avoid accidentally cutting off a message, always wait until TDRE is set after the last frame before clearing TE.

To separate messages with preambles with minimum idle line time, use this sequence between messages:

1. Write the last byte of the first message to SCIDRH and SCIDRL.

2. Wait until the TDRE flag is set, indicating the transfer of the last frame to the transmit shift register.

3. Queue a preamble by clearing and then setting the TE bit.

4. Write the first byte of the second message to SCIDRH and SCIDRL.

When the SCI relinquishes the TXD pin, the SCIPORT and SCIDDR registers control the TXD pin.

To force TXD high when turning off the transmitter, set bit 1 of the SCI Port Register (SCIPORT) and bit 1 of the SCI Data Direction Register (SCIDDR). The TXD pin goes high as soon as the SCI relinquishes control of it. See 14.6.8 SCI Port Data Register and 14.6.9 SCI Data Direction Register.

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14.10.3 Break Frames

Setting the SBK bit in SCICR2 loads the transmit shift register with a break frame. A break frame contains all logic 0s and has no start, stop, or parity bit. Break frame length depends on the M bit in the SCICR1 register. As long as SBK is set, the SCI continuously loads break frames into the transmit shift register. After SBK is clear, the transmit shift register finishes transmitting the last break frame and then transmits at least one logic 1. The automatic logic 1 at the end of a break frame guarantees the recognition of the next start bit.

The SCI recognizes a break frame when a start bit is followed by eight or nine 0 data bits and a 0 where the stop bit should be. Receiving a break frame has these effects on SCI registers:

Sets the FE flag

Sets the RDRF flag

Clears the SCIDRH and SCIDRL

May set the OR flag, NF flag, PE flag, or the RAF flag

14.10.4 Idle Frames

An idle frame contains all logic 1s and has no start, stop, or parity bit. Idle frame length depends on the M bit in the SCICR1 register. The preamble is a synchronizing idle frame that begins the first transmission after writing the TE bit from 0 to 1.

If the TE bit is cleared during a transmission, the TXD pin becomes idle after completion of the transmission in progress. Clearing and then setting the TE bit during a transmission queues an idle frame to be sent after the frame currently being transmitted.

NOTE: When queuing an idle frame, return the TE bit to logic 1 before the stop bit of the current frame shifts out to the TXD pin. Setting TE after the stop bit appears on TXD causes data previously written to SCIDRH and SCIDRL to be lost. Toggle TE to queue an idle frame, while the TDRE flag is set, immediately before writing new data to SCIDRH and SCIDRL.

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14.11 Receiver

Figure 14-15 SCI Receiver Block Diagram

14.11.1 Frame Length

The receiver can handle either 8-bit or 9-bit data. The state of the M bit in SCICR1 selects frame length. When receiving 9-bit data, bit R8 in SCIDRH is the ninth bit (bit 8).

14.11.2 Receiving a Frame

When the SCI receives a frame, the receive shift register shifts the frame in from the RXD pin.

After an entire frame shifts into the receive shift register, the data portion of the frame transfers to SCIDRH and SCIDRL. The RDRF flag is set, indicating that the received data can be read. If the RIE bit is also set, RDRF generates an interrupt request.

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14.11.3 Data Sampling

The receiver samples the RXD pin at the RT clock rate. The RT clock is an internal signal with a frequency 16 times the baud rate. To adjust for baud rate mismatch, the RT clock resynchronizes:

After every start bit

After the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit samples at RT8, RT9, and RT10 returns a valid logic 1 and the majority of the next RT8, RT9, and RT10 samples returns a valid logic 0)

To locate the start bit, data recovery logic does an asynchronous search for a 0 preceded by three 1s. When the falling edge of a possible start bit occurs, the RT clock begins to count to 16.

Figure 14-16 Receiver Data Sampling

To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7.

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Table 14-6 Start Bit Verification

RT3, RT5, and RT7 Samples Start Bit

Verification Noise Flag

000 Yes 0

001 Yes 1

010 Yes 1

011 No 0

100 Yes 1

101 No 0

110 No 0

111 No 0

If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins.

To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10.

Table 14-7 Data Bit Recovery

RT8, RT9, and RT10 Samples Data Bit Determination Noise Flag

000 0 0

001 0 1

010 0 1

011 1 1

100 0 1

101 1 1

110 1 1

111 1 0

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NOTE: The RT8, RT9, and RT10 data samples do not affect start bit verification. If any or all of the RT8, RT9, and RT10 samples are logic 1s following a successful start bit verification, the NF flag is set and the receiver interprets the bit as a start bit (logic 0).

The RT8, RT9, and RT10 samples also verify stop bits.

Table 14-8 Stop Bit Recovery

RT8, RT9, and RT10 Samples Framing Error Flag Noise Flag

000 1 0

001 1 1

010 1 1

011 0 1

100 1 1

101 0 1

110 0 1

111 0 0

In Figure 14-17 the verification samples RT3 and RT5 determine that the first low detected was noise and not the beginning of a start bit. The RT clock is reset and the start bit search begins again. The NF flag is not set because the noise occurred before the start bit was verified.

Figure 14-17 Start Bit Search Example 1

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In Figure 14-18 noise is perceived as the beginning of a start bit although the RT3 sample is high. The RT3 sample sets the noise flag. Although the perceived bit time is misaligned, the RT8, RT9, and RT10 data samples are within the bit time, and data recovery is successful.


In Figure 14-19 a large burst of noise is perceived as the beginning of a start bit, although the RT5 sample is high. The RT5 sample sets the noise flag. Although this is a worst-case misalignment of perceived bit time, the data samples RT8, RT9, and RT10 are within the bit time and data recovery is successful.


Figure 14-20 shows the effect of noise early in the start bit time. Although this noise does not affect proper synchronization with the start bit time, it does set the noise flag.

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Figure 14-21 shows a burst of noise near the beginning of the start bit that resets the RT clock. The sample after the reset is low but is not preceded by three high samples that would qualify as a falling edge. Depending on the timing of the start bit search and on the data, the frame may be missed entirely or it may set the framing error flag.


In Figure 14-22 a noise burst makes the majority of data samples RT8, RT9, and RT10 high. This sets the noise flag but does not reset the RT clock. In start bits only, the RT8, RT9, and RT10 data samples are ignored.

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14.11.4 Framing Errors

If the data recovery logic does not detect a 1 where the stop bit should be in an incoming frame, it sets the FE flag in SCISR1. A break frame also sets the FE flag because a break frame has no stop bit. The FE flag is set at the same time that the RDRF flag is set.

14.11.5 Baud Rate Tolerance

A transmitting device may be operating at a baud rate below or above the receiver baud rate. Accumulated bit time misalignment can cause one of the RT8, RT9, and RT10 stop bit data samples to fall outside the stop bit. A noise error occurs if the samples are not all the same value. If more than one of the samples is outside the stop bit, a framing error occurs. In most applications, the baud rate tolerance is much more than the degree of misalignment that is likely to occur.

As the receiver samples an incoming frame, it resynchronizes the RT clock on any valid falling edge within the frame. Resynchronization within frames corrects misalignments between transmitter bit times and receiver bit times.

14.11.5.1 Slow Data Tolerance

Figure 14-23 shows how much a slow received frame can be misaligned without causing a noise error or a framing error. The slow stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit data samples at RT8, RT9, and RT10.

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Figure 14-23 Slow Data

For 8-bit data, sampling of the stop bit takes the receiver:

9 bit times 16 RT cycles× 10 RT cycles 154 RT cycles=+

With the misaligned data shown in Figure 14-23, the receiver counts 154 RT cycles at the point when the count of the transmitting device is:


The maximum percent difference between the receiver count and the transmitter count for slow 8-bit data with no errors is:

154 147–154

--------------- 100 4.54=× %



10 bit time 16 RT cycles× 3 RT cycles 163 RT cycles=+

The maximum percent difference between the receiver count and the transmitter count for slow 9-bit data with no errors is:

170 163–170

--------------- 100 4.12=× %

14.11.5.2 Fast Data Tolerance

Figure 14-24 shows how much a fast received frame can be misaligned without causing a noise error or a framing error. The fast stop bit ends at RT10 instead of RT16 but is still sampled at RT8, RT9, and RT10.

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Figure 14-24 Fast Data




10 bit times 16RTcycles× 160 RT cycles=

The maximum percent difference between the receiver count and the transmitter count for fast 8-bit data with no errors is:

154 160–154

--------------- 100 3.90=× %




11 bit times 16RTcycles× 176 RT cycles=

The maximum percent difference between the receiver count and the transmitter count for fast 9-bit data with no errors is:

170 176–170

--------------- 100 3.53=× %

14.11.6 Receiver Wakeup

So that the SCI can ignore transmissions intended only for other devices in multiple-receiver systems, the receiver can be put into a standby state. Setting the RWU bit in SCICR2 puts the receiver into a standby state during which receiver interrupts are disabled.

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The transmitting device can address messages to selected receivers by including addressing information in the initial frame or frames of each message.

The WAKE bit in SCICR1 determines how the SCI is brought out of the standby state to process an incoming message. The WAKE bit enables either idle line wakeup or address mark wakeup.

14.11.6.1 Idle Input Line Wakeup (WAKE = 0)

When WAKE = 0, an idle condition on the RXD pin clears the RWU bit and wakes up the receiver. The initial frame or frames of every message contain addressing information. All receivers evaluate the addressing information, and receivers for which the message is addressed process the frames that follow. Any receiver for which a message is not addressed can set its RWU bit and return to the standby state. The RWU bit remains set and the receiver remains on standby until another idle frame appears on the RXD pin.

Idle line wakeup requires that messages be separated by at least one idle frame and that no message contains idle frames.

The idle frame that wakes up the receiver does not set the IDLE flag or the RDRF flag.

The ILT bit in SCICR1 determines whether the receiver begins counting logic 1s as idle frame bits after the start bit or after the stop bit.

14.11.6.2 Address Mark Wakeup (WAKE = 1)

When WAKE = 1, an address mark clears the RWU bit and wakes up the receiver. An address mark is a 1 in the most significant data bit position. The receiver interprets the data as address data. When using address mark wakeup, the MSB of all non-address data must be 0. User code must compare the address data to the receiver’s address and, if the addresses match, the receiver processes the frames that follow. If the addresses do not match, user code must put the receiver back to sleep by setting the RWU bit. The RWU bit remains set and the receiver remains on standby until another address frame appears on the RXD pin.

The address mark clears the RWU bit before the stop bit is received and sets the RDRF flag.

Address mark wakeup allows messages to contain idle frames but requires that the most significant byte (MSB) be reserved for address data.

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NOTE: With the WAKE bit clear, setting the RWU bit after the RXD pin has been idle can cause the receiver to wake up immediately.

14.12 Single-Wire Operation

Normally, the SCI uses the TXD pin for transmitting and the RXD pin for receiving (LOOPS = 0, RSRC = X). In single-wire mode, the RXD pin is disconnected from the SCI and is available as a general-purpose I/O pin. The SCI uses the TXD pin for both receiving and transmitting.

In single-wire mode (LOOPS = 1, RXRC = 1), setting the data direction bit for the TXD pin configures TXD as the output for transmitted data. Clearing the data direction bit configures TXD as the input for received data.

Figure 14-25 Single-Wire Operation (LOOPS = 1, RSRC = 1)

Enable single-wire operation by setting the LOOPS bit and the RSRC bit in SCICR1. Setting the LOOPS bit disables the path from the RXD pin to the receiver. Setting the RSRC bit connects the receiver input to the output of the TXD pin driver. Both the transmitter and receiver must be enabled (TE = 1 and RE = 1).

The WMS bit in the SCICR1 register configures the TXD pin for full CMOS drive or for open-drain drive. WMS controls the TXD pin in both normal operation and in single-wire operation. When WMS is set, the DDR bit for the TXD pin does not have to be cleared for transmitter to receive data.

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14.13 Loop Operation

In loop mode (LOOPS = 1, RSRC = 0), the transmitter output goes to the receiver input. The RXD pin is disconnected from the SCI and is available as a general-purpose I/O pin.

Setting the DDR bit for the TXD pin connects the transmitter output to the TXD pin. Clearing the data direction bit disconnects the transmitter output from the TXD pin.

Figure 14-26 Loop Operation (LOOPS = 1, RSRC = 0)

Enable loop operation by setting the LOOPS bit and clearing the RSRC bit in SCICR1. Setting the LOOPS bit disables the path from the RXD pin to the receiver. Clearing the RSRC bit connects the transmitter output to the receiver input. Both the transmitter and receiver must be enabled (TE = 1 and RE = 1).

The WMS bit in SCICR1 configures the TXD pin for full CMOS drive or for open-drain drive. WMS controls the TXD pin during both normal operation and loop operation.

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14.14 I/O Ports

The SCIPORT register is associated with two pins:

The TXD pin is connected to SCIPORT1.

The RXD pin is connected to SCIPORT0.

The SCI Data Direction Register (SCIDDR) configures the pins as inputs or outputs (see 14.6.9 SCI Data Direction Register).

14.15 Reset

Reset initializes the SCI registers to a known startup state as described in 14.6 Memory Map and Registers

14.16 Interrupts

lists the five interrupt requests associated with each SCI module.

Table 14-9 SCI Interrupt Request Sources

Source Flag Enable Bit

Transmitter TDRE TIE

TC TCIE

Receiver

RDRF RIE

OR RIE

IDLE ILIE

14.16.1 Transmit Data Register Empty

The TDRE flag is set when the transmit shift register receives a byte from the SCI Data Register. It signals that SCIDRH and SCIDRL are empty and can receive new data to transmit. If the TIE bit in SCICR2 is also set, TDRE generates an interrupt request. Clear TDRE by reading SCISR1 and then writing to SCIDRL. Reset sets TDRE.

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14.16.2 Transmission Complete

The TC flag is set when TDRE = 1 and no data, preamble, or break frame is being transmitted. It signals that no transmission is in progress. If the TCIE bit is set in SCICR2, TC generates an interrupt request. When TC is set, the TXD pin is idle (logic 1). TC is cleared automatically when a data, preamble, or break frame is queued. Clear TC by reading SCISR1 with TC set and then writing to the SCIDRL register. TC cannot be cleared while a transmission is in progress.

14.16.3 Receive Data Register Full

The RDRF flag is set when the data in the receive shift register transfers to SCIDRH and SCIDRL. It signals that the received data is available to be read. If the RIE bit is set in SCICR2, RDRF generates an interrupt request. Clear RDRF by reading SCISR1 and then reading SCIDRL.

14.16.4 Idle Receiver Input

The IDLE flag is set when 10 (if M = 0) or 11 (if M = 1) consecutive logic 1s appear on the receiver input. This signals an idle condition on the receiver input. If the ILIE bit in SCICR2 is set, IDLE generates an interrupt request. Once IDLE is cleared, a valid frame must again set the RDRF flag before an idle condition can set the IDLE flag. Clear IDLE by reading SCISR1 with IDLE set and then reading SCIDRL.

14.16.5 Overrun

The OR flag is set if data is not read from SCIDRL before the receive shift register receives the stop bit of the next frame. This signals a receiver overrun condition. If the RIE bit in SCICR2 is set, OR generates an interrupt request. The data in the shift register is lost, but the data already in SCIDRH and SCIDRL is not affected. Clear OR by reading SCISR1 and then reading SCIDRL.

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Section 15 DES

15.1 Introduction

The Data Encryption Standard (DES) module is the cryptographic module that achieves the DES and Triple-DES encryption algorithm.

15.2 Features

Support DES and Triple-DES encryption and decryption algorithm

Support DES algorithm with 64(56) bits key

Support Triple-DES algorithm with 128(112) bits or 192(168) bits key

Support ECB mode and CBC mode

Support MLBBUS Interface with CS320D CPU

Data process speed up to 27.83MBps@80MHz for DES

Data process speed up to 11.64MBps@80MHz for Triple-DES


The DES controller is not affected by low-power mode. CPU can stop DES by setting the corresponding module stop bit in Clock Module.

226


15.4 Block Diagram

Figure 15-1 DES Block Diagram

15.5 Module Memory Map and Register

DES module has a base address located at 0x00cc_0000. Refer to Table 15-1 for a description of the memory map.

DES module consists of these registers:

Input Data Register (DAEDINR) : Input of 64-bit data for DES/Triple-DES

Input Key1 Register (DAEKIN1R) : Input of 64-bit key for DES or input of the first 64-bit key for Triple-DES.

Input Key2 Register (DAEKIN2R) : Input of the second 64-bit key for Triple-DES

Input Key3 Register (DAEKIN3R) : Input of the third 64-bit key for Triple-DES

Input IV Register (DAEIVINR) : Input of 64-bit initial vectors for CBC mode of DES/Triple-DES

Output Data Register (DAEDOUTR) : Output of 64-bit result from DES/Triple-DES

Control Status Register (DAECSR) : Configurations of DES module.

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15.5.1 Module Memory Map

Table 15-1 shows the DES register memory map.


Address Register Attribute1 Access2

0x00cc_0000 Input Data Register (DAEDINR) R/W

S/U

0x00cc_0004 S/U

0x00cc_0008 Input Key1 Register (DAEKIN1R) R/W

S/U

0x00cc_000c S/U


S/U

0x00cc_0014 S/U


S/U

0x00cc_001c S/U

0x00cc_0020 Input Initial Vectors Register (DAEIVINR) R/W

S/U

0x00cc_0024 S/U

0x00cc_0028 Output Data Register (DAEDOUTR) RO

S/U

0x00cc_002c S/U

0x00cc_0033 Control Status Register (DAECSR) R/W S/U

1. R=Read; W=Write

2. S=Supervisor mode access; U=User mode access

3. DES supports only word write/read operation to the registers.


This subsection provides a description of the DES module registers.

15.5.2.1 DAEDINR

Address : 0x00cc_0000 to 0x00cc_0007

Bit63 62 . . . 1 Bit0

Read: DAEDINR

Write:

RESET: 0 0 . . . 0 0


Figure 15-2 Input Data Register

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DAEDINR[63:0] — Input Data Register A 64-bit input data register for DES/Triple-DES. Write the most significant 32 bits of data to DAEDINR at the address of 0x00cc_0000 and the least significant 32 bits at 0x00cc_0004. Reset clears DAEDINR.

NOTE: The least significant 32-bits shall be written after all the register has been configured. Because the write operation to the lower 32-bits of the DAEDINR register will start the DES operation.

15.5.2.2 DAEKIN1R

Address : 0x00cc_0008 to 0x00cc_000f

Bit63 62 . . . 1 Bit0

Read: DAEKIN1R

Write:

RESET: 0 0 . . . 0 0


Figure 15-3 Input Key1 Register

DAEKIN1R[63:0] — Input Key1 Register A 64-bit input key register for DES or for Triple-DES first key. Write the most significant 32 bits of data to DAEKIN1R at the address of 0x00cc_0008 and the least significant 32 bits at 0x00cc_000c. Reset clears DAEKIN1R register to 0x0101010101010101.

NOTE: The least significant bit of every eight bits is the odd parity bit.

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15.5.2.3 DAEKIN2R


Bit63 62 . . . 1 Bit0

Read: DAEKIN2R

Write:

RESET: 0 0 . . . 0 0



DAEKIN2R[63:0] — Input Key2 Register A 64-bit input key register for Triple-DES second key. Write the most significant 32 bits of data to DAEKIN2R at the address of 0x00cc_0010 and the least significant 32 bits at 0x00cc_0014. Reset clears DAEKIN2R. Reset clears DAEKIN2R register to 0x0101010101010101.


15.5.2.4 DAEKIN3R


Bit63 62 . . . 1 Bit0

Read: DAEKIN3R

Write:

RESET: 0 0 . . . 0 0



DAEKIN3R[63:0] — Input Key3 Register A 64-bit input key register for DES or for Triple-DES first key. Write the most significant 32 bits of data to DAEKIN1R at the address of 0x00cc_0018 and the least significant 32 bits at 0x00cc_001c. Reset clears DAEKIN3R. Reset clears DAEKIN3R register to 0x0101010101010101.


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15.5.2.5 DAEIVINR


Bit63 62 . . . 1 Bit0

Read: DAEIVINR

Write:

RESET: 0 0 . . . 0 0


Figure 15-6 Input Initial Vectors Register

DAEIVINR[63:0] — Input Initial Vectors Register A 64-bit input initial vectors register for DES/Triple-DES. Write the most significant 32 bits of IV to DAEIVINR at the address of 0x00cc_0020 and the least significant 32 bits at 0x00cc_0024. Reset clears DAEIVINR. Note: Input initial vector is necessary when DES is working at CBC mode and for bit in COMMAND/STATUS register is set.

15.5.2.6 DAEDOUTR


Bit63 62 . . . 1 Bit0

Read: DAEOUTR

Write:

RESET: 0 0 . . . 0 0


Output Data Register

DAEOUTR[63:0] — Output Data Register A 64-bit output data register for DES/Triple-DES. Read most significant 32 bits of data from DAEDOUTR at the address of 0x00cc_0028 and the least significant 32 bits at 0x00cc_002c. Reset clears DAEDOUTR.

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15.5.2.7 DAECSR

Address : 0x00cc_0033

Bit7 6 5 4 3 2 1 Bit0

Read: Err KS1 KS0 FR OP E/D EN

BUSY

Write:

RESET: 0 0 0 0 0 0 0 0


Figure 15-7 Control Status Register

BUSY — DES bus indicator bit DES module sets the BUSY flag when software writes input Data to the DAEDINR. DES module clears BUSY when encryption/decryption operation finished. Reset Clears BUSY.

1= DES module is busy. 0= DES module is idle.

EN — DES module enable bit Set the EN bit to enable DES mode or clear the EN bit to disable DES module. Reset clears EN bit.

1= DES module enabled 0= DES module disabled

E/D — Encrypt or Decrypt operation selection bit The ED bit selects encryption or decryption operation. Reset clears ED bit.

1= Encrypt mode 0= Decrypt mode

OP — Work mode selection bit Set the OP bit to make the DES work in CBC mode or clear the OP bit to make the DES work in ECB mode. Reset clears OP bit.

1= DES module works in CBC mode. 0= DES module works in ECB mode.

FR — CBC start bit When DES works in CBC mode, the FR bit determines the first run function. This bit is cleared automatically when the first run CBC encryption is complete.

1= First run CBC encryption 0= Not first run CBC encryption

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KS[1:0] — Key number bit The KS bit selects operation key size. Reset Clears KS. 00/01 = operation with 64(56) bits key for DES 10 = operation with 128(112) bits for Triple-DES 11 = operation with 192(168) bits for Triple-DES

Err — Key parity error indicator bit In every key, the lowest bit of each 8 bits is parity check bit. E.g., in KEY1[7:0], KEY1[0] is the parity check bit. If the parity check error happens, Err bit will be set as 1. Reset clears Err bit.


DES module support DES ECB Mode operation, DES CBC Mode operation, Triple-DES ECB Mode operation and Triple-DES CBC Mode operation.

15.6.1 DES ECB Mode Operation

The process for the operation is described as follow:

1 : Write DAECSR to set the operation mode.

2 : Write DAEKIN1R to input 64-bit Key.

3 : Write DAEDINR to input 64bit Data, then DES module starts running and BUSY flag of DAECSR is set high.

4 : Read DAECSR and check the BUSY flag until the BUSY flag is turned to low.

5 : Read DAEDOUTR for 64-bit Result output.

6 : Repeat the operations from Step 3 to Step 5 with the same key or repeat from Step 2 to Step 5 for a new key.

15.6.2 DES CBC Mode Operation



2 : Write DAEKIN1R to input 64-bit Key.

3 : Write DAEIVINR to input 64-bit Initial Vectors.

4 : Write DAEDINR to input 64-bit Data, then DES module starts running and BUSY flag of DAECSR is set high.

233




7 : Repeat the operations from Step 4 to Step 6 with the same key and initial vectors. Repeat from Step 3 to Step 6 for a new initial vectors. Repeat from Step 2 to Step 6 for a new key.

15.6.3 Triple-DES ECB Mode Operation



2 : Write DAEKIN1R to input the first 64-bit Key.

3 : Write DAEKIN2R to input the second 64-bit Key. Write DAEKIN3R to input the third 64-bit Key when the operation with 192(168) bits key.




7 : Repeat the operations from Step 4 to Step 6 with the same key or repeat from Step 2 to Step 6 for a new key.

15.6.4 Triple-DES CBC Mode Operation



2 : Write DAEKIN1R to input the first 64-bit Key.

3 : Write DAEKIN2R to input the second 64-bit Key. Write DAEKIN3R to input the third 64-bit Key when the operation with 192(168) bits key.

4 : Write DAEIVINR to input 64-bit Initial Vectors.




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8 : Repeat the operations from Step 5 to Step 7 with the same key and initial vectors. Repeat from Step 4 to Step 7 for a new initial vectors. Repeat from Step 2 to Step 7 for a new key.

15.7 Reset Operation

DES module supports hard reset operation. Hard reset operation by reset signal (ipg_hard_async_reset_b) initializes the registers to a known startup state as described (see 15.5.1 Module Memory Map).

Reset operation initializes the operation core and control to initial state.

235


Section 16 Edge Port Module (EPORT)

16.1 Introduction

The edge port module (EPORT) has eight external interrupt pins. Each pin can be configured individually as a low level-sensitive interrupt pin, an edge-detecting interrupt pin (rising edge, falling edge, or both), or a general-purpose input/output/ (I/O) pin. See Figure 16-1.

Figure 16-1 EPORT Block Diagram


This subsection describes the operation of the EPORT module in low-power modes.

16.2.1 Wait and Doze Modes

In wait and doze modes, the EPORT module continues to operate normally and may be configured to exit the low-power modes by generating an interrupt request on either a selected edge or a low level on an external pin.

236


16.2.2 Stop Mode

In stop mode, there are no clocks available to perform the edge-detect function. Only the level-detect logic is active (if configured) to allow any low level on the external interrupt pin to generate an interrupt (if enabled) to exit stop mode.

NOTE:

The input pin synchronizer is bypassed for the level-detect logic since no clocks are available.

16.3 Interrupt/General-Purpose I/O Pin Descriptions

All pins default to general-purpose input pins at reset. The pin value is synchronized to the rising edge of CLKOUT when read from the EPORT Pin Data Register (EPPDR). The values used in the edge/level detect logic are also synchronized to the rising edge of CLKOUT. These pins use Schmitt triggered input buffers which have built in hysteresis designed to decrease the probability of generating false edge-triggered interrupts for slow rising and falling input signals.


This subsection describes the memory map and register structure.

16.4.1 Memory Map

Refer toTable 16-1 for a description of the EPORT memory map. The EPORT has a base address of 0x00ce_0000.

237


Table 16-1 Module Memory Map


0x00ce_0000

)

EPORT Pin Assignment Register (EPPAR) S

0x00ce_0002 EPORT Data Direction Register

(EPDDR)

EPORT Interrupt Enable Register

(EPDDR) S

0x00ce_0004 EPORT Data Register (EPDR) EPORT Pin Data Register (EPPDR) S/U

0x00ce_0006 EPORT Flag Register (EPFR) Reserved(23 S/U )

16.4.2 Registers

The EPORT programming model consists of these registers:

The EPORT Pin Assignment Register (EPPAR) controls the function of each pin individually.

The EPORT Data Direction Register (EPDDR) controls the direction of each one of the pins individually.

The EPORT Interrupt Enable Register (EPIER) enables interrupt requests for each pin individually.

The EPORT Data Register (EPDR) holds the data to be driven to the pins.

The EPORT Pin Data Register (EPPDR) reflects the current state of the pins.

The EPORT Flag Register (EPFR) individually latches EPORT edge events.



error. 23Writing to reserved address locations has no effect, and reading returns 0s.

238


16.4.2.1 EPORT Pin Assignment Register

Address : 0x00ce_0000 through 0x00ce_0001

15 14 13 12 11 10 9 8

R EPPA7 EPPA6 EPPA5 EPPA4

W

RESET: 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

R EPPA3 EPPA2 EPPA1 EPPA0

W

RESET: 0 0 0 0 0 0 0 0

Figure 16-2 EPORT Pin Assignment Register (EPPAR)

EPPA[7:0] — EPORT Pin Assignment Select Fields The read/write EPPAx fields configure EPORT pins for level detection and rising and/or falling edge detection as shows. Pins configured as level-sensitive are inverted so that a logic 0 on the external pin represents a valid interrupt request. Level-sensitive interrupt inputs are not latched. To guarantee that a level-sensitive interrupt request is acknowledged, the interrupt source must keep the signal asserted until acknowledged by software. Level sensitivity must be selected to bring the device out of stop mode with an INTx interrupt. Pins configured as edge-triggered are latched and need not remain asserted for interrupt generation. A pin configured for edge detection is monitored regardless of its configuration as input or output.

Table 16-2 EPPAx Field Settings EPPAx Pin Configuration

00 Pin INTx level-sensitive

01 Pin INTx rising edge triggered

10 Pin INTx falling edge triggered

11 Pin INTx both falling edge and rising edge triggered

239


Interrupt requests generated in the EPORT module can be masked by the interrupt controller module. EPPAR functionality is independent of the selected pin direction. Reset clears the EPPAx fields.

16.4.2.2 EPORT Data Direction Register

Address : 0x00ce_0002

7 6 5 4 3 2 1 0

R EPDD7 EPDD6 EPDD5 EPDD4 EPDD3 EPDD2 EPDD1 EPDD0

W

RESET: 0 0 0 0 0 0 0 0

Figure 16-3 EPORT Data Direction Register (EPDDR)

EPDD[7:0] — Edge Port Data Direction Bits Setting any bit in the EPDDR configures the corresponding pin as an output. Clearing any bit in EPDDR configures the corresponding pin as an input. Pin direction is independent of the level/edge detection configuration. Reset clears EPDD[7:0]. To use an EPORT pin as an external interrupt request source, its corresponding bit in EPDDR must be clear. Software can generate interrupt requests by programming the EPORT Data Register when the EPDDR selects output.

Corresponding EPORT pin configured as output Corresponding EPORT pin configured as input

16.4.2.3 Edge Port Interrupt Enable Register


7 6 5 4 3 2 1 0

R EPIE7 EPIE6 EPIE5 EPIE4 EPIE3 EPIE2 EPIE1 EPIE0

W

RESET: 0 0 0 0 0 0 0 0

Figure 16-4 EPORT Port Interrupt Enable Register (EPIER)

240


EPIE[7:0] — Edge Port Interrupt Enable Bits The read/write EPIE[7:0] bits enable EPORT interrupt requests. If a bit in EPIER is set, EPORT generates an interrupt request when:

The corresponding bit in the EPORT Flag Register (EPFR) is set or later becomes set, or

The corresponding pin level is low and the pin is configured for level-sensitive operation

Clearing a bit in EPIER negates any interrupt request from the corresponding EPORT pin. Reset clears EPIE[7:0].

1= Interrupt requests from corresponding EPORT pin enabled 0= Interrupt requests from corresponding EPORT pin disabled

16.4.2.4 Edge Port Data Register


7 6 5 4 3 2 1 0

R EPD7 EPD6 EPD5 EPD4 EPD3 EPD2 EPD1 EPD0

W

RESET: 0 0 0 0 0 0 0 0

Figure 16-5 EPORT Port Data Register (EPDR)

EPD[7:0] — Edge Port Data Bits Data written to EPDR is stored in an internal register; if any pin of the port is configured as an output, the bit stored for that pin is driven onto the pin. Reading EDPR returns the data stored in the register. Reset sets EPD[7:0].

16.4.2.5 Edge Port Pin Data Register


7 6 5 4 3 2 1 0

R EPPD7 EPPD6 EPPD5 EPPD4 EPPD3 EPPD2 EPPD1 EPPD0

W

RESET: P P P P P P P P


P = Current pin state

Figure 16-6 EPORT Port Pin Data Register (EPPDR)

241


EPPD[7:0] — Edge Port Pin Data Bits The read-only EPPDR reflects the current state of the EPORT pins. Writing to EPPDR has no effect, and the write cycle terminates normally. Reset does not affect EPPDR.

16.4.2.6 Edge Port Flag Register


7 6 5 4 3 2 1 0

R EPPD7 EPPD6 EPPD5 EPPD4 EPPD3 EPPD2 EPPD1 EPPD0

W




Figure 16-7 EPORT Port Flag Register (EPFR)

EPF[7:0] — Edge Port Flag Bits When an EPORT pin is configured for edge triggering, its corresponding read/write bit in EPFR indicates that the selected edge has been detected. Reset clears EPF[7:0].

1= Selected edge for INTx pin has been detected. 0= Selected edge for INTx pin has not been detected.

Bits in this register are set when the selected edge is detected on the corresponding pin. A bit remains set until cleared by writing a 1 to it. Writing 0 has no effect. If a pin is configured as level-sensitive (EPPARx = 00), pin transitions do not affect this register.

242


Section 17 SM1

17.1 Introduction

The SM1 module implements the SM1 symmetric cryptographic algorithms.

17.2 Features

The SM1 controller features include:

Support SM1 module encryption/decryption algorithm

128 bits data unit for encryption and decryption

Support Electronic Code Book (ECB) mode

128~256 bits security key length selectable

128 bits system key

Data process speed up to 80MBps@80MHz


The SM1 controller is not affected by low-power mode. CPU can stop SM1 by setting the corresponding module stop bit in Clock Module.

243



Table 17-1 shows the SM1 register memory map.


Address Bits 31-24 Bits 23-16 Bits 15-8 Bits 7-0 Access24,25

0x00cf_0000

SM1 Control Register (SM1CR) S/U

0x00cf_0004 SM1 Status Register (SM1SR) S/U

0x00cf_0008 SM1 Write Data Register (SM1WDR) S/U

0x00cf_000c SM1 Read Data Register (SM1RDR) S/U




244



17.5.1 SM1 Control Register (SM1CR)

SM1CR contains the control bits for SM1 module.

Address : 0x00cf_0000 through 0x00cf_0003

31 30 29 28 27 26 25 24

R 0 0 0 0 0 0 0 0

W

RESET: 0 0 0 0 0 0 0 0

23 22 21 20 19 18 17 16

R 0 0 0 0 0 0 0 SM1RST

W

RESET: 0 0 0 0 0 0 0 1

15 14 13 12 11 10 9 8

R 0 0 0 0 0 0 SK_EXTN

ENC_DEC

N W

RESET: 0 0 0 0 0 0 1 1

7 6 5 4 3 2 1 0

R 0 0 0 0 0 0 DATA_TYPE[1:0]

W

RESET: 0 0 0 0 0 0 0 0


Figure 17-1 SM1 Control Register

SM1RST — SM1 Soft Ware Reset SM1RST bit is used to reset the SM1 module. After system reset, the SM1 module is put on reset state since SM1RST’s initial value is 1’b1.

1= Reset the SM1 module. 0= Reset to SM1 is released.

245


SK_EXTN — System Key Selection SK_EXTN bit is used to select the system key modes.

1= SK is the SM1 internal fixed value. 0= SK is the combination of the internal fixed value and the external SK

data input.

ENC_DECN — Encode/Decode Selection ENC_DECN bit is used to select the operation modes.

1= SM1 is in Encode mode. 0= SM1 is in Decode mode.

DATA_TYPE[1:0] — Data Type Selection DATA_TYPE bits are used to select the data type.

Table 17-2 SM1 Data Type Selection DATA_TYPE[1:0] Data Type

00 EK

01 AK

10 SK

11 DATA

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17.5.2 SM1 Status Register (SM1SR)

Address : 0x00cf_0004 through 0x00cf_0007

31 30 29 28 27 26 25 24

R 0 0 0 0 0 0 0 0

W

RESET: 0 0 0 0 0 0 0 0

23 22 21 20 19 18 17 16

R 0 0 0 0 0 0 0 0

W

RESET: 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8

R 0 0 0 0 0 0 0 0

W

RESET: 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

R 0 0 0 0 0 TBUSY DATARDY KEYRDY

W

RESET: 0 0 0 0 0 0 0 0


Figure 17-2 SM1 Status Register (SM1SR)

TBUSY — SM1 Transfer Busy Flag TBUSYbit indicates the write data is being transferred to SM1 module and SM1WDR can not be accessed.

1= Data transfer busy. 0= No data transfer.

DATARDY — SM1 Data Ready Flag DATARDY bit indicates the SM1 output data is ready and can be accessed by reading SM1RDR. Clear this flag by writing 1 to this bit.

1= SM1 output data ready. 0= SM1 output data not ready.

247


KEYRDY — SM1 Key Ready Flag KEYRDY bit indicates the SM1 key is ready. Clear this flag by writing 1 to this bit.

SM1 key ready. SM1 key not ready.

248


17.5.3 SM1 Write Data Register (SM1WDR)

Address : 0x00cf_0008 through 0x00cf_000b

31 30 29 28 27 26 25 24

R

W

RESET: 0 0 0 0 0 0 0 0

23 22 21 20 19 18 17 16

R

W

RESET: 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8

R

W

RESET: 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

R

W

RESET: 0 0 0 0 0 0 0 0


Figure 17-3 SM1 Write Data Register (SM1WDR)

SM1WDR register is the SM1 input data FIFO entry. Once 4x32bit data is written to SM1WDR, the 128bit data in the FIFO will be transferred to SM1 module in the following 4 clock cycles.

249


17.5.4 SM1 Read Data Register (SM1RDR)

Address : 0x00cf_000c through 0x00cf_000f

31 30 29 28 27 26 25 24

R

W

RESET: 0 0 0 0 0 0 0 0

23 22 21 20 19 18 17 16

R

W

RESET: 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8

R

W

RESET: 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

R

W

RESET: 0 0 0 0 0 0 0 0


Figure 17-4 SM1 Read Data Register (SM1RDR)

SM1RDR register is the SM1 output data FIFO entry. Once the encode/decode completes and DATARDY flag is set, the 128bit output data can be read from SM1RDR register.

250



17.6.1 Module Reset

The module’s reset is controlled by SM1RST bit in SM1CR. The module is always put in reset state after any chip reset since SM1RST’s reset value is 1.

To enable the module, software must clear SM1RST bit to release the module reset.

17.6.2 Key Description

The module needs three kinds of Key:

Elementary Key : EK (128Bits)

Assistant Key: AK (0~128Bits)

System Key: SK (128Bits).

The KEY is the combination of EK and AK. If AK’s bit count is less than 128, AK should be extended to 128bit by adding 0 to its tail.

SK’s mode is decided by SK_EXTN bit. If SK_EXTN bit is 1, SK will select the internal fixed value and software can input any value during SK input stage. If SK_EXTN bit is 0, SK is the combination of the input data during SK input stage and the internal fixed value.

17.6.3 Key and Data Input

The EK, AK, SK and DATA are inputted according to the following steps:

1. Set DATA_TYPE[1:0] to the corresponding value. For example, if the next stage is to write EK, set DATA_TYPE[1:0] = 2’b00;

2. Write 128bit Data to SM1WDR by four times word write;

3. Wait four clock cycle or check if TBUSY flag is cleared.

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17.6.4 Input KEY

The KEY is inputted according to the following steps:

1. Input EK (4words);

2. Input AK (4words);

3. Input SK (4words);

4. Check KEYRDY bit. If the flag is set, the key generation is completed.

5. To regenerate the KEY, clear the KEYRDY bit and repeat the above steps.

17.6.5 Encryption/Decryption

The data unit for encryption and decryption is 128bits.

The base operation of encryption is the same as the decryption’s. The only difference is about ENC_DECN bit.

17.6.5.1 Normal Mode

The following is the steps for the normal operation:

1. Set operation mode by writing ENC_DECN bit;

2. Input data (4words);

3. Check DATARDY bit;

4. If DATARDY is set, get the result (128bits) by reading SM1RDR four times;

5. Clear DATARDY bit;

6. Repeat the steps 2~5 to encrypt/decrypt another data group(128bits).

252


Section 18 Universal Serial Interface Modules

(USI1/2)

18.1 Introduction

The USI provides the smart card interface. It is compatible with ISO7816-3.

18.2 Features

Features of USI module include:

Support of ISO7816-3

Support both card and card reader mode

Support T=0 and T=1 protocol

Half-duplex operation

1 transmit buffer + 1 receive buffer

13-bit baud rate selection or F/D selection (11.625, 23.25, 46.5, 93, 186, 372, 744)

9-bit guard time counter (GTCNT)

24 bits waiting time counter (WTCNT)

Programmable transmitter output polarity

Interrupt-driven operation with eight flags:

- Transmitter empty

- Transmission complete

- Receiver full

- Receiver overrun

- Noise error

- Parity error

- Timeout on WT counter

- Answer to Reset

Auto-character repetition on error signal detection in transmit mode

253


Auto-error signal generation on parity error detection in receive mode

Hardware parity checking

1/16 bit-time noise detection

General purpose, IO capability

18.3 Block Diagram

IP INTERFACE

BARRELSHIFT REGISTER

USIDATA REGISTERS

BAUD RATEGENERATOR

SYSTEMCLOCK

÷16

UART Mode Controller

USICONTROL REGISTERS

USISTATUS REGISTER

GUARD TIMECOUNTER

WAITING TIMECOUNTER

USIBDR[12:0]

SYSTEMCLOCK

INTERRUPT GENERATOR

ISOCLKISORST

ISODAT

USI INTERRUPT

Figure 18-1 USI Block Diagram

254



USI operation is identical in run, special, and emulation modes. The USI has two low-power modes, doze and stop.

NOTE: Run mode is the normal mode of operation and the WAIT instruction does not affect USI operation.

18.4.1 Doze Mode

When the DOZ bit in the USI Control Register 1 (USICR1) is set, the DOZE instruction stops the USI clock and puts the USI in a low-power state. The DOZE instruction does not affect USI register states. Any transmission or reception in progress stops at doze mode entry and resumes when an internal or external interrupt request brings the CPU out of doze mode. Exiting doze mode by reset aborts any transmission or reception in progress and resets the USI.

NOTE: DOZE instruction never stops the Card Clocks.

When the DOZ bit is clear, execution of the DOZE instruction has no effect on the USI. Normal module operation continues, allowing any USI interrupt to bring the CPU out of doze mode.

18.4.2 Stop Mode

The STOP instruction stops the USI clocks and puts the USI in a low-power state. The STOP instruction does not affect USI register states. Any transmission or reception in progress halts at stop mode entry and resumes when an external interrupt request brings the CPU out of stop mode. Exiting stop mode by power on reset or card reset which aborts any transmission or reception in progress.

255



Table 18-1 gives an overview of the signals which are described here.


Name Primary Function Port Direction

(Card Mode)

Direction (Card Reader

Mode)

ISODAT Card Data Input/Output USIPORT[2] I/O I/O

ISOCLK Card Clock USIPORT[1] I O

ISORST Card Reset from the interface device

USIPORT[0] I O

18.5.1 ISODAT

This signal is used as Smart Card Interface data input/output. It can also be configured as GPIO.

18.5.2 ISORST

This signal is used as Smart Card reset signal. It always works at GPI mode. In card mode, this pin should be configured as input (reset state) and in card reader mode, this pin should be configured as output.

In card mode, when the card reset occurred, the answer to reset interrupt will be asserted and the interrupt can wake up the CPU from stop mode.

NOTE: ISORST is not used as the system reset.

18.5.3 ISOCLK

This signal is used as Smart Card clock signal. It can also be configured as GPIO.

NOTE: There is not a dedicated control bit for selecting the work modes (card or card reader modes). ISOCLK’s direction is controlled by DDRUSI[1] bit even not in GPIO mode.

256



Table 18-2 shows the USI memory map.

NOTE: Reading unimplemented addresses (0x00d0_000e through 0x00d0_001f and 0x00d1_000e through 0x00d1_001f) returns 0s. Writing to unimplemented addresses has no effect. Accessing unimplemented addresses does not generate an error response.

Table 18-2 Universal Serial Interface Module Memory Map26

26Each module is assigned 64K bytes of address space, all of which may not be decoded. Accesses

outside of the specified module memory map generate a bus error exception.

257


USI USI Bits 15–8 Bits 7–0 Access27

0x00d0_0000

0x00d1_0000 USI Baud Register High

(USIBDRH) USI Baud Register Low

(USIBDRL) S/U

0x00d0_0002 0x00d1_0002 USI Control Register 1

(USICR1) USI Control Register 2

(USICR2) S/U

0x00d0_0004 0x00d1_0004 USI Status Register (USISR) USI Interrupt Enable Register

(USIER) S/U

0x00d0_0006 0x00d1_0006 USI Receive Data Register

(USIRDR) USI Transmit Data Register

(USITDR) S/U

0x00d0_0008 0x00d1_0008 USI Wait Time Register High (USIWTRH) S/U

0x00d0_000a 0x00d1_000a USI Wait Time Register Low (USIWTRL) S/U

0x00d0_000c 0x00d1_000c USI Guard Time Register High

(USIGTRH) USI Guard Time Register Low

(USIGTRL) S/U

0x00d0_000e 0x00d1_000e USI Card Clock Select Register (USICSR) S/U

0x00d0_0010 0x00d1_0010 USI Port Control Register (USIPCR) S/U

0x00d0_0012 0x00d1_0012 USI Port Data Register

(USIPDR) USI Data Direction Register

(USIDDR) S/U

0x00d0_0014 to

0x00d0_001f

0x00d1_0014 to

0x00d1_001f Reserved28 S/U

27S/U = CPU supervisor or user mode access. User mode accesses to supervisor only addresses

have no effect and result in a cycle termination transfer error.

28Within the specified module memory map, accessing reserved addresses does not generate a bus

error exception. Reads of reserved addresses return 0s and writes have no effect.

258


18.6.1 USI Baud Rate Registers (BDGM = 0)

Address: 0x00d0_0000,0x00d1_0000

Bit7 6 5 4 3 2 1 Bit0

Read: 0 0 0 UBR12 UBR11 UBR10 UBR9 UBR8

Write:

RESET: 0 0 0 0 0 0 0 0


Figure 18-2 USI Baud Rate Register High (USIBDRH)

Address: 0x00d0_0001,0x00d1_0001

Bit7 6 5 4 3 2 1 Bit0

Read: UBR7 UBR6 UBR5 UBR4 UBR3 UBR2 UBR1 UBR0

Write:

RESET: 0 0 0 0 0 0 0 0

Figure 18-3 USI Baud Rate Register Low (USIBDRL)

Read: Anytime

Write: Anytime

UBR[12:8], UBR[7:0] — USI Baud Rate Bits These read/write bits control the USI baud rate. When system clock source is selected to generate baud rate,

USIBaudfsys

16 UBR 12:0[ ]×--------------------------=

where fsys is system clock, which is from PLL or external clock, and 1 UBR[12:0] 8191≤ ≤

The detail description see 18.7.2 Baud Rate Generation.

NOTE:

The baud rate generator is disabled when UBR[12:0]=0.

Writing to USIBDRH has no effect without also writing to USIBDRL. Writing to USIBDRH puts the data in a temporary location until data is written to USIBDRL.

259


18.6.2 USI Baud Rate Registers (BDGM = 1)

Address: 0x00d0_0000,0x00d1_0000

Bit7 6 5 4 3 2 1 Bit0

Read: 0 0 0 0 0 0 0 0

Write:

RESET: 0 0 0 0 0 0 0 0


Figure 18-4 USI Baud Rate Register High (USIBDRH)

Address: 0x00d0_0001,0x00d1_0001

Bit7 6 5 4 3 2 1 Bit0

Read: 0 0 0 0 0 FDSEL[2:0]

Write:

RESET: 0 0 0 0 0 0 0 0

Figure 18-5 USI Baud Rate Register Low (USIBDRL)

Read: Anytime

Write: Anytime

Table 18-3 F/D Selection FDSEL[2:0] F/D Value

0 Reserved

1 744

2 372(29

3

)

186

4 93

5 46.5

6 23.25

7 11.625

29The value during ATR.

260


18.6.3 USI Control Register 1

Address: 0x00d0_0002,0x00d1_0002

Bit7 6 5 4 3 2 1 Bit0

Read: BDGM DOZ CONV UART TMOD GTEN WTEN PT

Write:

RESET: 0 0 0 0 0 0 0 0

Figure 18-6 USI Control Register 1 (USICR1)

Read: Anytime

Write: Anytime

BDGM — Baud Gen Mode Bit The BDGM bit determines the baudgen mode. In F/D Mode, the system clock frequency should be bigger than 4 times of ISOCLK’s frequency. In general baud generation mode, the system clock source must be from ISOCLK.

1= F/D Mode 0= General Baudgen Mode

DOZ — USI Stop in Doze Mode Bit The DOZ bit disables the USI in doze mode.

1= UART disabled in doze mode 0= UART enabled in doze mode

CONV — USI Convention Select Bit This bit selects the USI convention.

1= The inverse convention: MSB(b7 bit) is sent first, the parity bit is added after b0 bit and a low level on the Card I/O pin represents a "1".

0= The direct convention: LSB(b0 bit) is sent first, the parity bit is added after b7 bit and a low level on the Card I/O pin represents a "0".

UART — USI UART Mode Enable Bit This read/write bit enables USI module’s UART controller. Writing the UART bit from 0 to 1 loads the transmit shift register with a preamble of 12 logic 1s. After the preamble shifts out, the USI transfers the data from USITDR to the transmit shift register.

1= UART enabled. 0= UART disabled.

261


TMOD — USI Transfer Mode Select Bit This read/write bit selects the transfer mode.

1= T=1 mode, the minimum delay between two consecutive start bits is 11 etu.

0= T=0 mode, the minimum delay between two consecutive start bits is 12 etu.

GTEN — Guard Time Counter Enable This bit enables the Guard Time Counter.

1= The Guard Time Counter is enabled 0= The Guard Time Counter is stopped

WTEN — Wait Time Counter Enable This bit enables the Wait Time Counter.

1= The Wait Time Counter is enabled 0= The Wait Time Counter is stopped

PT — Parity Type Bit This read/write bit selects even parity or odd parity. With even parity, an even number of 1s clears the parity bit and an odd number of 1s sets the parity bit. With odd parity, an odd number of 1s clears the parity bit and an even number of 1s sets the parity bit. System reset clears PT.

1= Odd parity 0= Even parity

262


18.6.4 USI Control Register 2

Address: 0x00d0_0003,0x00d1_0003

Bit7 6 5 4 3 2 1 Bit0

Read:

Write: AREG RCRP2 RCRP1 RCRP0 ACRP TCRP2 TCRP1 TCRP0

RESET: 0 0 0 0 0 0 0 0

Figure 18-7 USI Control Register 2 (USICR2)

Read: Anytime

Write: Anytime

AREG — Automatic Receive Error Generation Enable Bit This read/write bit enables Auto-error signal generation on parity error detection in receive mode. In T=0 mode, this bit must be set, while in T=1 mode, the function is disabled regardless of the bit state.

1= Auto-error signal generation enabled 0= Auto-error signal generation disabled

RCRP[2:0] — Receive Character Repetition Select Bits These read/write bits determines how many times character repetition in receive mode before the parity error flag (PF) is set. For example, if RCRP = 3 and in receive mode, three times error indication will be performed and the PF is set after four times parity error detection.

NOTE: If the AREG bit is clear, the RCRP bits have no effect.

ACRP — Automatic Character Repetition Enable Bit This read/write bit enables automatic character repetition when a parity error is indicated in transmit mode. In T= 0 mode, this bit must be set, while in T=1 mode, the function is disabled regardless of the bit state.

Automatic character repetition enabled. Automatic character repetition disabled.

TCRP[2:0] — Transmit Character Repetition Select Bit These read/write bits determines how many times character repetition in transmit mode before the parity error flag (PF) is set. For example, if TCRP = 4 and in transmit mode, four times character repetition will be performed and the PF is set after five times consecutive parity error indication.

NOTE: If the ACRP bit is clear, the TCRP bits has no effect.

263


18.6.5 USI Status Register

Address: 0x00d0_0004,0x00d1_0004

Bit7 6 5 4 3 2 1 Bit0

Read: TDRE TC RDRF OR NF ATR WTO PF

Write:

RESET: 1 1 0 0 0 0 0 0


Figure 18-8 USI Status Register (USISR)

Read: Anytime

Write: Has no meaning or effect except PF flag

TDRE — Transmit Data Register Empty Flag The TDRE flag is set when the shift register receives a word from the USI Transmit Data Register. It signals that the USITDR are empty and can receive new data to Transmit.If the TIE bit in the USIIER is also set, TDRE generates an interrupt request. Clear TDRE by reading USISR and then writing to USITDR. System reset sets TDRE.

1= Transmit data register empty 0= Transmit data register not empty

TC — Transmit Complete Flag The TC flag is set when TDRE = 1 and no data is being transmitted. It signals that no transmission is in progress. If the TCIE bit is set in USIIER, TC generates an interrupt request. When TC is set, the ISODAT pin is idle (logic 1). TC is cleared automatically when a data is queued. Clear TC by reading USISR with TC set and then writing to USITDR. TC cannot be cleared while a transmission is in progress. System reset sets TC.

1= No transmission in progress 0= Transmission in progress

RDRF — Receive Data Register Full Flag The RDRF flag is set when the data in the shift register is transferred to USIRDR. It signals that the received data is available to the MCU. If the RIE bit is set in USIIER, RDRF generates an interrupt request. Clear RDRF by reading the USISR and then reading USIRDR. System reset clears RDRF.

1= Received data available in USIRDR 0= Received data not available in USIRDR

264


OR — Overrun Flag The OR flag is set if data is not read from USIRDR before the shift register receives the stop bit of the next frame. This is a receiver overrun condition. If the RIE bit in USIIER is set, OR generates an interrupt request. The data in the shift register is lost, but the data already in the USIRDR is not affected. Clear OR by reading USISR and then reading USIRDR. System reset clears OR.

1= Overrun 0= No overrun

NF — Noise Flag The NF flag is set when the USI detects noise on the receiver input. NF is set during the same cycle as the RDRF flag but does not get set in the case of an overrun. Clear NF by reading USISR and then reading USIRDR. System reset clears NF.

1= Noise 0= No noise

ATR— Answer to Reset Flag The ATR flag indicates that there is an ATR request from the Host occurred. Clear ATR by writing 1 to it. Power on reset clears ATR.

1= reset signal is detected 0= No reset signal is detected

WTO — Wait TimeOut Flag The WTO flag is set when USI Waiting Time Counter times out. Clear WTO by clear WTEN (write 0 to WTEN when WTEN=1). System reset clears WTO.

1= Waiting Time Counter times out 0= No timeout

PF — Parity Error Flag The PF flag is set when the parity of the received data does not match its parity bit or error signal detected in transmit mode. Clear PF in receive mode by reading USISR and then reading USIRDR. Clear PF in transmit mode by reading USISR and then writing 1 to PF bit. System reset clears PF.

1= Parity error 0= No parity error

265


18.6.6 USI Interrupt Enable Register

Address: 0x00d0_0005,0x00d1_0005

Bit7 6 5 4 3 2 1 Bit0

Read:

Write:

RESET:

TIE TCIE RIE WTOIE ATRIE 0 0

PIE

0 0 0 0 0 0 0 0


Figure 18-9 USI Interrupt Enable Register (USIIER)

Read: Anytime

Write: Anytime

TIE — Transmitter Interrupt Enable Bit This read/write bit allows the TDRE flag to generate interrupt requests. Reset clears TIE.

1= TDRE interrupt requests enabled 0= TDRE interrupt requests disabled

TCIE — Transmission Complete Interrupt Enable Bit This read/write bit allows the TC flag to generate interrupt requests. Reset clears TCIE.

1= TC interrupt requests enabled 0= TC interrupt requests disabled

RIE — Receiver Interrupt Enable Bit This read/write bit allows the RDRF and OR flags to generate interrupt requests. Reset clears RIE.

1= RDRF and OR interrupt requests enabled 0= RDRF and OR interrupt requests disabled

WTOIE — Wait Timeout Interrupt Enable Bit This read/write bit allows the WTO flag to generate interrupt requests. Reset clears WTO.

1= WTO interrupt requests enabled 0= WTO interrupt requests disabled

266


ATRIE — Answer to Reset Interrupt Enable bit This read/write bit allows the ATR flag to generate interrupt requests.

1= ATR interrupt requests enabled 0= ATR interrupt requests disabled

PIE — Parity Error Interrupt Enable Bit This read/write bit allows the PF flag to generate interrupt requests. Reset clears PIE.

1= PF interrupt requests enabled 0= PF interrupt requests disabled

267


18.6.7 USI Data Registers

Address: 0x00d0_0006,0x00d1_0006

Bit7 6 5 4 3 2 1 Bit0

Read:

Write:

R7 R6 R5 R4 R3 R2 R1 R0

RESET: 0 0 0 0 0 0 0 0


Figure 18-14 USI Receive Data Register (USIRDR)

Address: 0x00d0_0007

Bit7 6 5 4 3 2 1 Bit0

Read:


RESET: 0 0 0 0 0 0 0 0

Figure 18-15 USI Transmit Data Register (USITDR)

Read: Anytime

Write: Anytime

R[7:0] — Receive Bits [7:0] The R[7:0] bits are receive bits [7:0]. System reset clears R[7:0].

T[7:0] — Transmit Bits [7:0] The T[7:0] bits are transmit bits [7:0]. System reset clears T[7:0].

268


18.6.8 USI Wait Time Register

Address : 0x00d0_0008 and 0x00d0_0009,0x00d1_0008 and 0x00d1_0009

15 14 13 12 11 10 9 8

Read: 0 0 0 0 0 0 0 0

Write:

RESET: 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

Read: WT23 WT22 WT21 WT20 WT19 WT18 WT17 WT16

Write:

RESET: 0 0 0 0 0 0 0 0


Figure 18-14 USI Wait Time Register High (USIWTRH)

Address : 0x00d0_000a and 0x00d0_000b, 0x00d1_000a and 0x00d1_000b

15 14 13 12 11 10 9 8


Write:

RESET: 0 0 1 0 0 1 0 1

7 6 5 4 3 2 1 0


Write:

RESET: 1 0 0 0 0 0 0 0


Figure 18-15 USI Wait Time Register Low (USIWTRL)

Read: Anytime

Write: Anytime

WT[23:0] — USI Character/Block Wait Time Register Bits The WT[23:0] is the reload value of the Wait Time Counter (WTC). The WTC is a general-purpose Timer decreasing at the USI Baud Rate. It is used to check the maximum time between two consecutive start bits. See 18.7.4 Wait Time Counter (WTC).

269


18.6.9 USI Guard Time Register

Address : 0x00d0_000c and 0x00d0_000d,x00d1_000c and 0x00d1_000d

15 14 13 12 11 10 9 8

Read: 0 0 0 0 0 0 0 GT8

Write:

RESET: 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

Read: GT7 GT6 GT5 GT4 GT3 GT2 GT1 GT0

Write:

RESET: 0 0 0 0 1 1 0 0


Figure 18-14 USI Guard Time Register (USIGTR)

Read: Anytime;

Write: Anytime;

GT[8:0] — Transmit Guard Time Bits

The GT[8:0] bits is the reload value of the Guard Time Counter (GTC). The GTC is decremented at the USI baud rate. It is used to control the minimum time between two consecutive start bits in transmit mode. See 18.7.3 Guard Time Counter (GTC).

Guard Time GT[8:0] ETU×= where

ETU1

USIBaudrate------------------------=

270


18.6.10 USI Card Clock Select Register

This register is used to control the card clock generation in card reader mode.

Address: 0x00d0_000e~0x00d0_000f, 0x00d1_000e~0x00d1_000f

Bit7 6 5 4 3 2 1 Bit0

Read: 0 0 0 0 0 0 0 0

Write:

RESET: 0 0 0 0 0 0 0 0

Bit7 6 5 4 3 2 1 Bit0

Read: CCLKE

0 CCPS[5:0]

Write:

RESET: 0 0 0 0 0 0 0 0


Figure 18-15 USI Card Clock Select Register (UCICSR)

Read: Anytime

Write: Anytime

CCLKE — Main Card Clock Enable Bit The CCLKE bit enables ISOCLK’s generation.

1= Card clock generator enabled. 0= Card clock generator disabled.

CCPS[5:0] — Card Clock Prescaler Selection bits These read/write bits control the Card Clock (ISOCLK) frequency when CCLKE is set:

fCCLKfsys

CCPS 5:0[ ] 2×------------------------=

NOTE: The prescaler is disabled when CCPS[5:0] = 0.

The USICSR’s reset value is for normal card mode.

271


18.6.11 USI Port Control Register

Address: 0x00d0_0010~0x00d0_0011,0x00d1_0010~0x00d1_0011

Bit7 6 5 4 3 2 1 Bit0

Read: 0 0 0 0 0 0 0 0

Write:

RESET: 0 0 0 0 0 0 0 0

Bit7 6 5 4 3 2 1 Bit0

Read: CIOPA CCLKPA WMUSI[2:0] PUPUSI[2:0]

Write:

RESET: 0 0 0 0 0 1 1 1

ISODAT ISOCLK ISORST ISODAT ISOCLK ISORST


Figure 18-16 USI Port Control Register (USIPCR)

Read: Anytime

Write: Anytime

CIOPA — USI Port[2] Assignment Bit The read/write bit selects the ISODAT’s function mode.

1= Pin configured as GPIO. 0= Pin configured as primary function.

CCLKPA — USI Port[1] Assignment Bit The read/write bit selects the ISOCLK’s function mode.

1= Pin configured as GPIO. 0= Pin configured as primary function.

WMUSI[2:0] — Wired mode Bits The read/write bits set the corresponding USI pins to open-drain drive mode. WMUSI[2] for ISODAT pin is available in both GPIO and its primary function mode. WMUSI[1:0] are only available in GPIO mode.

1= Open-drain when output. 0= CMOS drive when output.

PUPUSI[2:0] — Pullup Enable Bits The read/write bits enable the pullups of corresponding USI pins. These bits are available in both primary function and GPIO mode.

1= Pullup Enabled. 0= Pullup Disabled.

272


18.6.12 USI Port Data Register

Address: 0x00d0_0012,0x00d1_0012

Bit7 6 5 4 3 2 1 Bit0

Read:

Write:

0 0 0 0 0 PORTUSI[2:0]

RESET: 0 0 0 0 0 ISODAT ISOCLK ISORST

Figure 18-17 USI Port Data Register (USIPDR)

Read: Anytime

Write: Anytime

PORTUSI[2:0] — USI Port Data Bits Writes to these bits set the output data for the corresponding USI pins configured as GPIO. Reading these bits return the USI pins’ level.

NOTE: Writes to PORTUSI do not change the pin state when the pin is configured as primary function.

273


18.6.13 USI Data Direction Register

Address: 0x00d0_0013,0x00d1_0013

Bit7 6 5 4 3 2 1 Bit0

Read:

Write:

0 0 0 0 0 DDRUSI[2:0]

RESET: 0 0 0 0 0 0 0 0

ISODAT ISOCLK ISORST

Figure 18-18 USI Data Direction Register (USIDDR)

Read: Anytime

Write: Anytime

DDRUSI[2:0] — USI Data Direction Bits The read/write bits control the data direction of the USI pins.


NOTE: Writes to DDRUSI[2] do not change ISODAT’s direction when the pin is configured as primary function.

274


18.7 Function Descriptions

The USI provides the smart card interface compliant with ISO7816-3. It allows half-duplex, asynchronous, serial communication between the card and remote devices. The USI transmitter and receiver operate independently, although they use the same baud rate generator. The CPU monitors the status of the USI, writes the data to be transmitted, and processes received the data.

18.7.1 Data Format

Each character is composed of:

one start bit

8 bits of data

one even parity bit

a guardtime slot including two stop bits without parity error (see Figure 18-19 Data Format without Parity Error).

a guardtime slot including three stop bits with parity error indication (see Figure 18-20 Data Format with Parity Error). The parity error signal’s duration is one etu in receive mode, and from one etu to two etu in transmit mode.

BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 PARITYSTART START2 STOP

Figure 18-19 Data Format without Parity Error

BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 PARITYSTART STARTERRORSIGNAL STOP

Figure 18-20 Data Format with Parity Error

The ISO 7816-3 specification implements two different conventions for data transfer: direct or reverse convention, which can be selected by the CONV and PT bits in USICR1 (see Figure 18-6 USI Control Register 1 (USICR1)).

Direct Convention (CONV=0 and PT = 0):

Not inverted bits (logical “1” = High level)

Least Significant Bit (LSB) first

Even parity (number of “1’s” in data + parity fields is even)

275


Reverse Convention:

Inverted bits (logical “1” = Low level)

Most Significant Bit (MSB) first

Odd parity (number of “1’s” in data + parity fields is odd)

18.7.2 Baud Rate Generation

A 13-bit modulus counter in the baud rate generator derives the baud rate for both the receiver and the transmitter. The value from 0 to 8191 written to USIBDH and USIBDL determines the system clock divisor. The baud rate clock is synchronized with the bus clock and drives the receiver. The baud rate clock divided by 16 drives the transmitter. The receiver acquisition rate is 16 samples per bit time.

Baud rate generation is subject to two sources of error:

1. Integer division of the module clock may not give the exact target frequency

2. Synchronization with the bus clock can cause phase shift.

Table 18-4 Example Baud Rates (System Clock = 60 MHz)

SBR[12:0] Receiver Clock

(Hz) Transmitter Clock

(Hz) Target

Baud Rate Percent

Error

0x0021 1,818,181.8 113,636.4 115,200 1.36

0x0041 923,076.9 57,692.3 57,600 0.16

0x0062 612,244.9 38,265.3 38,400 0.35

0x0070 535,714.2 33,482.1 33,600 0.35

0x0082 461,538.5 28,846.2 28,800 0.16

0x00c3 307,692.3 19,230.8 19,200 0.16

0x0104 230,769.2 14,423.1 14,400 0.16

0x0187 153,452.7 95,90.8 9,600 0.10

0x030d 76,824.6 4,801.5 4,800 0.03

0x061b 38,387.8 2,399.2 2,400 0.03

0x0c35 19,200 1,200 1,200 0

276


0x186a 9,600 600 600 0

18.7.3 Guard Time Counter (GTC)

The GTC is a 9 bits wide counter controlled by the Guard Time Register (GTR) (see 18.6.9 USI Guard Time Register) and it is decremented at the USI Baud Rate. The interval from start to GTC timeout is the minimum time between the leading edge of the start bit of a character and the leading edge of the start bit of the following character transmitted (Guard time). In fact, the GTC’s timeout is the enable signal of the new character transmitting (see Figure 18-21 Transmit Control with Guard Time).

CHAR1 CHAR2

TDRE

=Guard Time

CHAR1 CHAR2

TDRE

>Guard Time

Figure 18-21 Transmit Control with Guard Time

277


18.7.4 Wait Time Counter (WTC)

The WTC is a general 24 bits wide down counter which can be loaded with the value contained in the WTR register (see 18.6.8 USI Wait Time Register). As the GTC, the WTC is also decremented at the USI Baud Rate. Its main purpose is to generate timeout signal.

When the WTC timeout, an interrupt is generated if WTOIE is set. The WTO flag can be cleared by resetting the USI block or reloading the counter.

There is a automatic load on the start bit detection. This automatic load is very useful for changing on-the-fly the Timeout value since there is a register to hold the load value.

After a time out of the counter in USI mode, the restart is done.

CHAR1

WTC

CHAR2

<WT1*ETU

WTR WT1

>0 && <=WT1

WT2

CHAR3

WTO

<WT2*ETU >WT2*ETU

>0 && <=WT2 >0 && <=WT2 =0

Figure 18-22 Wait Time Counter (WTEN =1)

278


18.7.5 Answer to Reset

When the rising edge of the signal on ISORST comes, the 9 bits reset counter begin to count at USI Clock rate. When it counts up to 512, it sets the ATR flag. When ATRIE is enabled, it generates an ATR Interrupt (ATRI). Clear ATR flag by reading USISR and then writing to USITDR. System reset or card reset clears ATR flag.(see Figure 18-23 Reset of the Card)

Figure 18-23 Reset of the Card

18.8 Interrupts

lists the four interrupt requests associated with USI module.

Table 18-5 USI Interrupt Request Sources

Source Source Number

Flag Enable Bit

Transmitter 14 TDRE TIE

TC TCIE

Receiver 13 RDRF RIE

OR RIE

Error 12 WTO WTOIE

PF PIE

Reset 11 ATR ATRIE

279


18.8.1 Transmit Interrupt

Two kinds of flag can generate transmit interrupt (TRI) when in transmission.

The TDRE flag is set when the shift register receives a byte from the USI Transmit Data Register. It signals that USITDR is empty and can receive new data to transmit. If the TIE bit in USIIER is also set, TDRE generates an interrupt request TRI signal. Clear TDRE by reading USISR and then writing to USITDR. Reset sets TDRE.

The TC flag is set when TDRE = 1 and no data is being transmitted. It signals that no transmission is in progress. If the TCIE bit is set in USIIER, TC generates an interrupt request TRI signal. When TC is set, the ISODAT pin is idle (logic 1). TC is cleared automatically when a data is queued. Clear TC by reading USISR with TC set and then writing to the USITDR register. TC cannot be cleared while a transmission is in progress.

18.8.2 Receive Interrupt

Two kinds of flag can generate Receive Interrupt (REI) when receive data.

The RDRF flag is set when the data in the shift register transfers to USIRDR. It signals that the received data is available to be read. If the RIE bit is set in USIIER, RDRF generates an interrupt request REI signal. Clear RDRF by reading USISR and then reading USIRDR.

The OR flag is set if data is not read from USIRDR before the shift register receives the stop bit of the next frame. This signals a receiver overrun condition. If the RIE bit in USIIER is set, OR generates an interrupt request RI signal. The data in the shift register is lost, but the data already in USIRDR is not affected. Clear OR by reading USISR and then reading USIRDR.

18.8.3 Error Interrupt

The PF flag is set when the parity of the received data does not match its parity bit or error signal detected in transmit mode. If PIE bit in USIIER is set, PF generates an interrupt request Error Interrupt EI signal. Clear PF in receive mode by reading USISR and then reading USIRDR. Clear PF in transmit mode by reading USISR and then writing 1 to PF bit. Reset clears PF.

When the WTC timeout, Error Interrupt is also generated if WTOIE is set. The WTO flag can be cleared by resetting the USI block or reloading the counter.

280


18.8.4 Reset Interrupt

The ATR flag is set after the rising edge of ISORST and ATR Interrupt is also generated if ATRIE is set. The ATR flag can be cleared by reading USISR and then writing to USITDR.

281


Section 19 DMA Controller

19.1 Introduction

The DMA controller is one of the CLB masters that can transfer data with minimal CPU interaction. The DMA module provides two channels that allow byte, halfword and word transfers.

19.2 Features

The DMA controller features include:

One independently programmable DMA controller channels

Data transfers in 8, 16, 32 bit

Single cycle transfer


The DMA controller is not affected by any low-power modes. CPU can stop DMAC by setting the corresponding module stop bit in Clock Module.

282


19.4 Block Diagram

IPBUS

CLB Bus

BI

Reserved

PAR

DSR BCR

BAR

DCR

DMA Control CLB Interface

Figure 19-1 DMAC Block Diagram

283



Table 19-1 shows the MIM register memory map.



0x00d2_0000

Buffer Address Register (BAR) S

0x00d2_0004 Peripheral Address Register (PAR) S

0x00d2_0008 DSR byte Count Register (BCR) S

0x00d2_000c Reserved DCR S




284



19.6.1 Buffer Address Registers (BAR)

BAR contains the buffer address which can be written anytime. But the BAR will not be loaded to buffer address counter until software start DMA.

Address : 0x00d2_0000 through 0x00d2_0003

31 30 29 28 27 26 25 24

R 0 0 0 0 0 0 0 0

W

RESET: 0 0 0 0 0 0 0 0

23 22 21 20 19 18 17 16

R 0 0 0 0 0 0 0 0

W

RESET: 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8

R BAR[15] BAR[14] BAR[13] BAR[12] BAR[11] BAR[10] BAR[9] BAR[8]

W

RESET: 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

R BAR[7] BAR[6] BAR[5] BAR[4] BAR[3] BAR[2] BAR[1] BAR[0]

W

RESET: 0 0 0 0 0 0 0 0


19.6.3 Buffer Address Registers (BAR)

285


19.6.2 Peripheral Address Registers (PAR)

PAR contains the peripheral address which can be written anytime. But the PAR will not be loaded to peripheral address counter until software start DMA.


31 30 29 28 27 26 25 24

R PAR[31] PAR[30] PAR[29] PAR[28] PAR[27] PAR[26] PAR[25] PAR[24]

W

RESET: 0 0 0 0 0 0 0 0

23 22 21 20 19 18 17 16


W

RESET: 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8


W

RESET: 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0


W

RESET: 0 0 0 0 0 0 0 0


Figure 19-3 Peripheral Address Registers (PAR)

286


19.6.3 DMA Status Register (DSR)

Register address : 0x00d2_0008

7 6 5 4 3 2 1 0

R 0 0 0 AEF 0 0 0 DONE

W

RESET: 0 0 0 0 0 0 0 0


Figure 19-4 DMA Status Register

AEF — Access Error Flag This read-only bit indicates there is an access error during the DMA transfer.

1= The DMA channel terminated with an access error acknowledge. 0= No access error occurred.

DONE — DMA Transactions done. This read-only bit indicates all the DMA channel’s transactions complete. When BCR reaches zero or an access error occurs, DONE is set automatically.

1= DMA transfer completed. Software must clear DONE before reprogramming the DMA.

0= No effect.

287


19.6.4 Byte Count Register (BCR)

Register address : 0x00d2_0009 and 0x00d2_000b

23 22 21 20 19 18 17 16

R 0 0 0 0 0 0 0 0

W

RESET: 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8

R BCR15 BCR14 BCR13 BCR12 BCR11 BCR10 BCR9 BCR8

W

RESET: 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

R BCR7 BCR6 BCR5 BCR4 BCR3 BCR2 BCR1 BCR0

W

RESET: 0 0 0 0 0 0 0 0


Figure 19-5 Byte Count Register

BCR register bits contain the number of bytes yet to be transferred for a given block. BCR decrements on the successful completion of the address transfer of a write transfer. BCR decrements by 1,2 or 4 for byte, half-word or word, respectively. When software start DMA, BCR will be loaded to buffer byte counter.

288


19.6.5 DMA Control Register (DCR)

Register address : 0x00d2_000e to 0x00d2_000f

15 14 13 12 11 10 9 8

R DIE TDIR BNUM[1:0] BINC PINC TSIZ[1:0]

W

RESET: 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

R 0 0 0 0 AREN WEN

0

W START

RESET: 0 0 0 0 0 1 1 0


Figure 19-6 DMA Control Register

DIE — DMA Interrupt Enable The DIE bit determines whether an interrupt is generated when all the DMA transactions complete or an access error occurs.

1= DMA interrupt enabled. 0= DMA interrupt disabled.

TDIR — Transfer Direction The TDIR bit determines the direction of transfer.

1= Transfer from Peripheral to Buffer. 0= Transfer from Buffer to Peripheral.

BNUM[1:0] — Buffer Number. The BNUM[1:0] bits determines which buffer to be selected.

Table 19-2 BNUM Description

00 FIFO0~3 0x0080_0000~0x0080_07FF SRAM(2k) 0x0080_0800~0x0080_0FFF SRAM(4k) 0x0080_1000~0x0080_1FFF

01 SRAM(12k) 0x0080_2000~0x0080_4FFF

10 ECC be selected

11 buffer3 be selected

289


PINC — Peripheral Address Increment The PINC bit determines whether a peripheral address increments after a successful transfer.

1= PAR increments by 1, 2, 4, as determined by the transfer size. 0= No change to PAR after a successful transfer.

BINC — Buffer Address Increment The BINC bit determines whether the buffer address increments after a successful transfer.

1= Buffer address increments by 1,2,4, as determined by the transfer size.

0= No change to buffer address after a successful transfer.

TSIZ[1:0] — Transfer Size Bits. The TSIZ[1:0] bits determines the transfer size of the bus cycle.

Table 19-3 Transfer Size Encoding TSIZE[1:0] Transfer Size

0 0 Word

0 1 byte

1 0 Halfword

1 1 Auto

Autosize :The hardware will start the DMA transactions by word-->halfword--> byte

AREN — MLB Arbiter Enable The AREN bit determines whether the DMAC transfer data on MLB bus.

1= Transfer on MLB bus (core and DMAC can’t work at the same time). 0= Transfer not on MLB bus (core and DMAC can work at the same

time).

WEN — Buffer Write Enable The WEN bit determines whether the DMAC can transfer infinite data to buffer.

1= DMAC can transfer infinite data to buffer. 0= DMAC can only transfer finite data (512 bytes) to buffer.

START — Start Transfer Bit The START bit is used to start the DMA transactions by software. This bit is always read as "0".

1= Writing "1" to this bit will start the DMA transactions. 0= No effect.

290


Section 20 I2C

20.1 Introduction

I2C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange, minimizing the interconnection between devices. This bus is suitable for applications requiring occasional communications over a short distance between many devices. The flexible I2C allows additional devices to be connected to the bus for expansion and system development.

The interface operates up to 12.5KBps with maximum bus loading and timing.

The I2C system is a true multiple-master bus including arbitration and collision detection that prevents data corruption if multiple devices attempt to control the bus simultaneously. This feature supports complex applications with multiprocessor control and can be used for rapid testing and alignment of end products through external connections to an assembly-line computer.

20.2 Features

Compatibility with I2C bus standard.

Multiple masters operation.

Software-programmable for one of 64 different serial clock frequencies.

Software-selectable acknowledge bit.

Interrupt-driven, byte-by- byte data transfer.

Arbitration-lost interrupt with automatic mode switching from master to slave.

Transfer completion and read configure interrupt.

Start and stop signal generation/detection.

Repeated START signal generation.

Acknowledge bit generation/detection.

Bus-busy detection.

291


20.3 System and Block Diagram

Figure 20-1 I2C Block Diagram


There are two identical copies of the I2C module in the A5101 device. See 2.2 Address Map for the base addresses of these two I2C modules.

There are five registers in the I2C memory map, as shown in Table 20-1.

Table 20-1 I2C Memory Map Address Bits 7- 0

0x00d3_0000 I2C Slave Address Register (I2CSA)

0x00d3_0001 I2C Control Register (I2CC)

0x00d3_0002 I2C Clock Prescaler Register (I2CP)

0x00d3_0003 I2C Status Register (I2CS)

0x00d3_0004 I2C Data Register (I2CD)

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20.4.1 I2C Slave Address Register (I2CSA)

Address : 0x00d3_0000

Bit7 6 5 4 3 2 1 Bit0

Read: ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1

0

Write:

RESET: 0 1 0 0 0 0 0 0


The I2CSA stores the address when the I2C works as slave and responds to the address sent by a master.

ADDR[7:1] - Module Slave Address. Slave address when the I2C module is in slave mode. (I2C is slave by default).

20.4.2 I2C Control Register (I2CC)


Bit7 6 5 4 3 2 1 Bit0

Read: 0 0 0 REPSTA ACKEN MSMOD IEN EN

Write:

RESET: 0 0 0 0 1 0 0 0


I2CC is used to control the working of I2C module.

EN - I2C enable/disable control. 1= module is enabled. 0= module is disabled.

It enables/disables the module. Also controls the software reset of the entire I2C module. Resetting the bit generates an internal reset to the module which gets asserted after 2 clock of resetting the bit and remains asserted for 3 clocks. Thus reset gets negated after 5 clocks of resetting IEN bit. If the module is enabled in the middle of a byte transfer, slave mode ignores the current bus transfer and starts operating when the next start condition is detected. Master mode is not aware that the bus is busy; so initiating a start cycle may corrupt the current bus cycle, ultimately causing either the current

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master or the I2C module to lose arbitration, after which bus operation returns to normal.

IEN - I2C interrupt enable control. It enables the I2C interrupt when it is set.

1= I2C interrupt enabled. 0= I2C interrupt disabled.

MSMOD - I2C master/slave mode selection control. If the master loses arbitration, MSMOD is cleared without generating a STOP signal. Changing MSMOD from 1 to 0 generates a STOP on the bus and selects slave mode. Changing MSMOD from 0 to 1 generates a START on the bus and selects master mode.

1= Master mode. 0= Slave mode.

ACKEN - Acknowledge enable control. Specifies the value driven onto SDA during acknowledge cycles for both master and slave receivers. Note that writing ACKEN applies only when the I2C bus receives data and if the bit is clear before address transfer, the module will refuse other masters addressing.

1= An acknowledge signal is sent to the SDL at the ninth clock bit after receiving one byte of data.

0= No acknowledge signal is sent to the SDL at the ninth clock bit after receiving one byte of data.

REPSTA - Repeat Start Instead of signaling a STOP, the master can repeat the START signal, followed by a calling command.

1= Generate repeat start. 0= No repeat start.

20.4.3 I2C Clock Prescaler Register (I2CP)


Bit7 6 5 4 3 2 1 Bit0

Read: 0 TEST PRE5 PRE4 PRE3 PRE2 PRE1 PRE0

Write:

RESET: 0 0 0 0 0 0 0 0


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2CP is a prescaler to generate a bit-rate clock for the data transceiver. Due to potentially slow SCL and SDA rise and fall times, bus signals are sampled at the prescaler frequency. The serial bit clock frequency is equal to the system clock divided by the divider.

PRE[5:0] - Prescaler Divider Value

TEST - Clock Test Enable It enables test mode for the I2C clock. In test mode, the I2C maximum clock frequency is a quarter of the system frequency. In normal mode, its maximum frequency is fsys/(396x(PRE[5:0]+1)+1). In test mode, the frequency is fsys/(8x(PRE[5:0]+1)+1).

1= Clock Test Mode Enable 0= Normal Mode

20.4.4 I2C Status Register (I2CS)


Bit7 6 5 4 3 2 1 Bit0

Read: AACK DACK RXTX ARBL BBUSY AASLV RC TF

Write:

RESET: 0 0 0 0 0 0 0 0


The I2CS register shows the status of I2C module.

TF - Transfer Flag Indicates there is data transmitted or received. It is set by the falling edge of the ninth clock of a byte transfer. If the IEN bit in I2CC is also set, an interrupt will be generated. Clear TF by reading I2CS with TF set and then accessing I2CD or writing I2CC.

No data received or transmitted. Data be received or transmitted.

RC - Receiver Configure Shows it is time to configure the receiver. It is set by the falling edge of the ninth clock of a byte transfer. If the IEN bit in I2CC is also set, an interrupt will be generated. Clear RC by reading I2CS with RC set and then writing I2CC.

1= No transfer complete. 0= Transfer complete.

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AASLV - Addressed as a slave Shows the I2C module is addressed as a slave and its slave address matches the calling address on SDL.

1= Not as a slave. 0= Addressed as a slave.

BBUSY - I2C bus busy Shows the bus status.

1= Bus is idle. It is cleared from STOP bit. 0= Bus is busy. It is set from START bit.

ARBL - Arbitration lost Shows the arbitration status of the bus. It will be set in the following cases during SCL high: 1. SDA is sampled low when the master drives high during START condition, address cycle, data-transmit cycle or STOP condition. 2. SDA is sampled low when the master drives high during the acknowledge bit of a data-receive cycle. 3. A start cycle is attempted when the bus is busy. ARBL must be cleared by software by reading the I2CS register.

1= Arbitration not lost. 0= Arbitration lost.

RXTX - Receive or transmit. Shows whether the I2C is in receive or transmit mode during the transfer. In slave mode the bit is set according R/W from the other master.

1= Receive, receive data. 0= Transmit, transmit data.

DACK - Data acknowledge received. Shows the transmitter has received the acknowledge bit of SDA during data transmission.

1= No acknowledge bit received. 0= Acknowledge bit received.

AACK - Address acknowledge error. Shows the master did not receive an address acknowledge. It is set by the ninth clock and cleared by reading I2CS.

1= No address acknowledge error. 0= Acknowledge error.

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20.4.5 I2C Data Register (I2CD)


Bit7 6 5 4 3 2 1 Bit0

Read: R7 R6 R5 R4 R3 R2 R1 R0


RESET: 0 0 0 0 0 0 0 0


The I2CD register holds the data to be transmitted (next byte) or data received. In master mode it also holds the slave address and transfer direction to be transmitted. Bits [7:1] form the slave address and bit [0] is the transfer direction (R/W). In master-receive mode, reading I2CD allows a read to occur and initiates next byte data receiving. In master-transmit mode, writing I2CD will store the byte of the next transmit. In slave mode, the same function is available after it is addressed.

R[7:0] - Receive Bits [7:0]

T[7:0] - Transmit Bits [7:0]


The I2C module is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange, minimizing the interconnection between devices. Software can poll the I2C status flags or I2C operation can be interrupt driven. When a byte is received or to be transmitted, the TF bit in I2CS will be set and if the IEN bit in I2CC is also set, an interrupt will be generated.

If arbitration is lost during its transfer, the ARBL will be set and if the IEN bit in I2CC is also set, an interrupt will be generated. It can also be generated if there is no address acknowledge from the slave (AACK set).

The module can clear ACKEN if it does not want to receive next byte.

20.5.1 Master Mode

The I2C module may initial a transfer if the bus is free (the BBUSY bit of I2CS is clear) when it works as a master. Changing the MSMOD bit from 0 to 1 generates a START on the bus and selects master mode. The MSMOD bit

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controls the direction of transfer, namely the R/W bit. The first byte of a transfer sent by the module is the slave address, the following byte is data. Change the MSMOD bit from 1 to 0 to generate a STOP on the bus if no acknowledge is received after each ninth cycle of clock. The PRE[5:0] bits in I2CP control the bit-rate clock of I2C-bus.

By setting the REPSTA bit, the master can repeat the START signal instead of signaling a STOP.

20.5.2 Slave Mode

If the MSMOD bit is cleared the module is a slave and can be addressed by other masters. When a winning master is trying to address it, it will release the SDA line and switch over immediately to its slave mode.

Note: the I2C can’t work in slave mode and master mode at the same time.

20.5.3 Protocol

The I2C communication protocol consists of six components: START, Data Source/Recipient, Data Direction, Slave Acknowledge, Data, Data Acknowledge and STOP. These are shown in Figure 20-2 and described in the following text.

Figure 20-2 I2C Communication Protocol

1. START signal—When no other device is bus master (both SCL and SDA lines are at logic high), a device can initiate communication by sending a START signal (see A in Figure 20-2). A START signal is defined as a high-to-low transition of SDA while SCL is high. This signal denotes the beginning of a data transfer (each data transfer can be several bytes long) and awakens all slaves.

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2. Slave address transmission—The master sends the slave address in the first byte after the START signal (B). After the seven-bit calling address, it sends the R/W bit (C), which tells the slave the data transfer direction.

Each slave must have a unique address. An I2C master must not transmit an address that is the same as its own slave address; it cannot be master and slave at the same time. The slave whose address matches that sent by the master pulls SDA low at the ninth clock (D) to return an acknowledge bit.

3. Data transfer—When successful slave addressing is achieved, the data transfer can proceed (E) on a byte-by- byte basis in the direction specified by the R/W bit sent by the calling master.

Data can be changed only while SCL is low and must be held stable while SCL is high, as Figure 20-2 shows. SCL is pulsed once for each data bit, with the MSB being sent first. The receiving device must acknowledge each byte by pulling SDA low at the ninth clock; therefore, a data byte transfer takes nine clock pulses.

If it does not acknowledge the master, the slave receiver must leave SDA high. The master can then generate a STOP signal to abort the data transfer or generate a START signal (repeated start, shown in Figure 20-3) to start a new calling sequence.

If the master receiver does not acknowledge the slave transmitter after a byte transmission, it means end-of-data to the slave. The slave releases SDA for the master to generate a STOP or START signal.

4. STOP signal—The master can terminate communication by generating a STOP signal to free the bus. A STOP signal is defined as a low-to-high transition of SDA while SCL is at logical high (F). Note that a master can generate a STOP even if the slave has made an acknowledgment, at which point the slave must release the bus.

5. Instead of signaling a STOP, the master can repeat the START signal, followed by a calling command, (A in Figure 20-3). A repeated START occurs when a START signal is generated without first generating a STOP signal to end the communication. The master uses a repeated START to communicate with another slave or with the same slave in a different mode (transmit/receive mode), without releasing the bus.

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Figure 20-3 Repeat Start of I2C protocol

20.5.4 Arbitration Procedure

If multiple devices simultaneously request the bus, the bus clock is determined by a synchronization procedure in which the low period equals the longest clock-low period among the devices and the high period equals the shortest. A data arbitration procedure determines the relative priority of competing devices. A device loses arbitration if it sends logic high while another sends logic low; it immediately switches to slave-receive mode and stops driving SDA.

A master that loses the arbitration can generate clock pulses until the end of the byte in which it loses the arbitration. It’s possible that the winning master is trying to address it. The losing master must therefore switch over immediately to its slave mode.

In this case, the transition from master to slave mode does not generate a STOP condition. Meanwhile, hardware sets the ARBL bit of I2CSR to indicate loss of arbitration.

20.5.5 Clock Synchronization

Because wired-AND logic is used, a high-to-low transition on SCL affects all devices connected to the bus. Devices start counting their low period when the master drives SCL low. When a device clock goes low, it holds SCL low until the clock high state is reached. However, the low-to-high change in this device clock may not change the state of SCL if another device clock is still in its low period.

Therefore, the device with the longest low period holds the synchronized clock SCL low. Devices with shorter low periods enter a high wait state during this time (See Figure 20-4). When all devices involved have counted off their low period, the synchronized clock SCL is released and pulled high.

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There is then no difference between device clocks and the state of SCL, so all of the devices start counting their high periods. The first device to complete its high period pulls SCL low again.

20.5.6 Handshaking

The clock synchronization mechanism can be used as a handshake in data transfers. Slave devices can hold SCL low after completing one byte transfer (9 bits). In such a case, the clock mechanism halts the bus clock and forces the master clock into wait states until the slave releases SCL.

20.5.7 Clock Stretching

Slaves can use the clock synchronization mechanism to slow down the transfer bit rate. After the master has driven SCL low, the slave can drive SCL low for the required period and then release it. If the slave SCL low period is longer than the master SCL low period, the resulting SCL bus signal low period is stretched.

Figure 20-4 SCL Synchronization

20.5.8 Software Transaction Flow Diagrams

1. Initialization.

Figure 20-5 Slave Mode Initialization

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Figure 20-6 Master Mode Initialization

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2. Interrupt transaction

Figure 20-7 Interrupt Transaction

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Section 21 BCH

21.1 Introduction

The ECC module provides an ECC engine which performs BCH Correction Encoding/Decoding ’on the fly’ while data is being written to or read from the NANDFLASH ECC Data Channel. The ECC module supports 2 types of flash, which are a traditional type flash with 512+16 bytes, and newly developed with 512+28 bytes.

21.2 Features

The ECC controller features include:

Hocquenghem, Bose, Chaudury (BCH) Algorithm

Hardware "On the fly" Encoding/Decoding

Supports 528 bytes and 540 bytes flash memory

14 bytes ECC codes for 528 type flash

26 bytes ECC codes for 540 type flash

Can correct up to 8 bits data per page (512 data + 14 bytes ECC code).

Can correct up to 16 bits data per page (512 data + 26 bytes ECC code).

Decoding parallel working with key equation solver and error location searching.

Automatic error correction by hardware.


The ECC controller continues work in wait and doze mode. In stop mode, the system clock is absent, and ECC module operation stops.

CPU can disable ECC by setting the corresponding module stop bit in Clock Module.

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21.4 Block Diagram

IPBUS

MLBBUS

BCH SRAM

Figure 21-1 BCH Block Diagram

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Table 21-1 shows the ECC memory map.



0x00d4_0000

ECCB0 ECCB1 ECCB2 ECCB3 S

0x00d4_0004 ECCB4 ECCB5 ECCB6 ECCB7 S

0x00d4_0008 ECCB8 ECCB9 ECCBa ECCBb S

0x00d4_000c ECCBc ECCBd ECCBe ECCBf S

0x00d4_0010 ECCBg ECCBh ECCBi ECCBj S

0x00d4_0014 ECCBk ECCBl ECCBm ECCBn S

0x00d4_0018 ECCBo ECCBp EBSA S

0x00d4_001c ECCSR ECCCR S

0x00d4_0020 Revised PGNCR S




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21.6.1 ECC byte Registers (ECCBx)

When the ECC encoding has been done, ECCBx contains the 14 bytes ECC codes for 528 type flash and, 26 bytes ECC codes for 540 type flash. ECCBx will be changed after the next ECC encoding/decoding starts.

Address : 0x00d4_0000 through 0x00d4_00018 (ECCB0 ~ ECCBp)

7 6 5 4 3 2 1 0

R ECCBx[7:0]

W

RESET: 0 0 0 0 0 0 0 0


Figure 21-2 ECC byte Registers (ECCBx)

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21.6.2 SRAM Base Address Register (EBSA)

EBSA contains the destination base addresses of SRAM when decoding. If there are "dirty data" detected during decoding process, the ECC module will correct the data base on this base address and offset address. Accroding the pipe-line future of ECC module this register should be updated only after the previous correct process done (ECC_DONE).

Address : 0x00d4_001a

15 14 13 12 11 10 9 8

R EBSA[14:8]

W

RESET: 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

R EBSA[7:0]

W

RESET: 0 0 0 0 0 0 0 0


Figure 21-3 SRAM Base Address Register (EBSA)

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21.6.3 ECC Status Register (ECCSR)

Register address : 0x00d4_001c

15 14 13 12 11 10 9 8

R 0 0 0 0 ERN[3:0]

W

RESET: 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

R 0 0 ALL1 ALL0 Correctbus

y CDONE FAIL DONE

W

RESET: 0 0 0 0 0 0 0 0


Figure 21-4 ECC Status Register

ERN[3:0] — Error Number Bits The ERN[3:0] shows the error number found by ECC decoding. These read-only bits are valid when DONE Flag is set.

ALL1 — All Bits Are "1" Flag This read-only bit indicates that from the start of ECC encode/decode, all the bits through ECC channel are "1". Write 1 to DONE bit will clear this flag.

1= All the bits loaded from the beginning of ECC encode/decode are "1". 0= Not all the bits loaded from the beginning of ECC encode/decode are

"1".

ALL0 — All Bits Are "0" Flag This read-only bit indicates that from the start of ECC encode/decode, all the bits through ECC channel are "0". Write 1 to DONE bit will clear this flag.

1= All the bits loaded from the beginning of ECC encode/decode are "0". 0= Not all the bits loaded from the beginning of ECC encode/decode are

"0".

Correct_busy — ECC Busy State This read-only bit indicates that ECC is correcting data.

1= ECC is correcting data. 0= ECC is Free.

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CDONE— ECC Codec Done Flag This read-only bit indicates that previously codec (decode/encode) process complete, software can load the next flash page data to (decode/encode). Write 1 to DONE bit will clear this flag.

1= previous codec process complete. 0= previous codec process has not complete.

FAIL — ECC Decoding Failed Flag This read-only bit indicates an unrecoverable ECC decoding error occurred. Write 1 to DONE bit will clear this flag.

1= ECC decoding failed. 0= No effect.

DONE — ECC Correct Done Flag This read-only bit indicates ECC correct has been completed. ECC encoding will be done after 512 bytes data have been written to ECC channel address. Normally, ECC decoding will be done after 512+13 bytes(512+25 for 540 type flash) data have been loaded from ECC channel address. An unrecoverable error will also terminate the ECC decoding. If there are no "dirty data" in the transaction, the ECC correct done same as the ECC codec Done Flag, and if there has "dirty data" in the transaction, this flag will be set after the correct process done. As for the 2-stage pipeline future, the soft ware must detect the assertion of ECC correct Done Flag of first transaction before load the third flash page data. Write 1 to this bit will clear all the flags.

1= ECC encoding/decoding completed. Software must clear DONE before the next encoding/decoding.

0= No effect.

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21.6.4 ECC Control Register (ECCCR)

Register address : 0x00d4_001e to 0x00d4_001f

15 14 13 12 11 10 9 8

R 0 0 ECCWS[1:0]

0 RESET_H

AND TM[1] TM[0]

W

RESET: 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

R SKCOR PPC IGALL1 ZERC

0 DF TYPE ECCIE

W

RESET: 0 0 0 0 0 0 0 0


Figure 21-5 ECC Control Register

ECCWS[1:0] — ECC Wait State Bit These bits determines the ECC calculation cycle number for one byte.

Table 21-1 ECC Calculation Cycles

ECCWS[1:0]

ECC Calculation

Cycle Number

Maximum Operating Frequency(MHz)

Minimum NANDFLASH Access Cycle

8bit Port 16bit Port 32bit Port

0 1 40 1 2 4

1 2 80 2 4 8

2 3 120 3 6 12

3 4 160 4 8 16

TM[1] — ECC Mode Bit This bit determines the ECC mode and it is only valid in ECC Test mode.

ECC decoding. ECC encoding.

TM[0] — ECC Test Mode Bit This bit determines whether ECC module is in test mode or not. In test mode, the data is from a special address.

1= ECC Test Mode enabled. 0= ECC Test Mode disabled.

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SKCOR— Skip Correct Control Bit This bit was used for MPT only. To less the flash scan time, when set one to this bit, the BCH will not correct the data, only give the Error Number, and tag the failed page.

1= Skip Correct data process 0= Not Skip Correct data process

PPC— Pipe-Line Control bit This bit affect the interrupt generation, when set to zero no pipe-line will performed, the ECC module will generate the interrupt after correction finished, when set to one, the ECC module will generate the interrupt when ECC decode data path free.

NOTE: When read the last page of Flash this bit must be set to ZERO to generate the correct interruption.

1= ECC decoding in pipe-line mode 0= ECC decoding in no pipe-line mode

IGALL1 — Ignore All1 Decoding Enable The IGALL1 bit determines whether ECC decoding result is ignored if the decoded page(528 bytes) is all "FF". If the result is ignored, no error flag will be set.

1= ECC decoding result is ignored if the page is all "FF". 0= ECC decoding result is enabled even if the page is all "FF".

ZERC — Zero Error Control bit This bit was used for MPT only. To less the flash scan time, when set one to this bit, the BCH will tag the failed page when the error number more then one.

1= Zero Error Control 0= Not Zero Error Control

TYPE — Flash Type The TYPE bit determines which flash type be used in system.

1= 540 Flash type (512 bytes + 26 ECC Code) 0= 528 Flash type (512 bytes + 14 ECC code)

DF — Data Format This is an alternate bit. The DF bit determines which data format be used in system. When set this bit, the software can use 513 data bytes + 13 ECC code data format, which only supported by 8 bit port flash.

1= 513 data bytes + 13 ECC code 0= 512 data bytes + 14 ECC code

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ECCIE — ECC Done Interrupt Enable The ECCIE bit determines whether an interrupt is generated when the ECC encoding/decoding has been done.

1= ECC Done interrupt enabled. 0= ECC Done interrupt disabled.

RESET_HAND — Reset ECC Data Path. Write ONE to this bit will reset the ECC Data Path. It’s always reads ZERO.

1= Reset ECC Data Path.

21.6.5 Page Number Counter Register (PGNCR)

The PGNCR provide the page number has been corrected, when before a read start the software should give it a start number (default is zero).

Register address : 0x00d4_0022 to 0x00d4_0023

15 14 13 12 11 10 9 8

R 0 0 0 0 0 0 0 0

W

RESET: 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

R PGNCR[7:0]

W

RESET: 0 0 0 0 0 0 0 0


Figure 21-6 Page Number Counter Register

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21.7.1 On-the-fly Encoding/Decoding

ECC module can detect the data through the ECC channel (See Memory Integration Module for the details) automatically and encode/decode the data on-the-fly.

NOTE: To a continuous transfer through the ECC channel - If the transfer size is word, the transfer cycles must be not less than 4. If the transfer size is half-word, the transfer cycles must be not less than 2.

It is most important that the ECC is used as intended, i.e. page data is transferred in segments of 512 bytes through ECC channel address. If the data and ECC codes are not transferred in the proper order, the ECC registers may contain incorrect values, which will cause incorrect data to be stored and transferred.

After a segment of 512 bytes has been sent to the ECC channel address, the CPU is responsible for sending ECC bytes.

The Decoder requires both the 512 data bytes and the 14 bytes ECC code (26 bytes ECC code for 540 type flash) to be read in sequence in order to detect whether there were errors or not.

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Section 22 On-Chip Emulation Module (OnCE)

22.1 Introduction

The Leo has only one JTAG (Joint Test Action Group) TAP (test access port) controllers:

1. OnCE (on-chip emulation) controller that allows access to the central processor unit (CPU) and debugger-related registers.

The OnCE TAP controller can be enabled in either of two ways:

1. With the top-level TAP controller in its test-logic-reset state:

a. Deassert TRST, test reset (logic1)

b. Assert DE, the debug event (logic 0) for two TCLK, test clock, cycles

2. Shift the ENABLE_MCU_ONCE instruction, 0x3, into the top-level TAP controller’s Instruction Register (IR) and pass through the TAP controller state update-IR.

Refer to Figure 22-1.

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22.2 Low-Level TAP (OnCE) Module

The low-level TAP (OnCE, on-chip emulation) circuitry provides a simple, inexpensive debugging interface that allows external access to the processor’s internal registers and to memory/peripherals. OnCE capabilities are controlled through a serial interface, mapped onto a JTAG test access port (TAP) protocol. Refer to Figure 22-1 for a block diagram of the OnCE.

The interface to the OnCE controller and its resources is based on the TAP defined for JTAG in the IEEE 1149.1 standard.

Figure 22-1 OnCE Block Diagram

Figure 22-2 shows the OnCE (low-level TAP module) data registers.

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Figure 22-2 Low-Level (OnCE) Tap Module Data Registers (DRs)

317



The OnCE pin interface is used to transfer OnCE instructions and data to the OnCE control block. Depending on the particular resource being accessed, the CPU may need to be placed in debug mode. For resources outside of the CPU block and contained in the OnCE block, the processor is not disturbed and may continue execution. If a processor resource is required, the OnCE controller may assert an internal debug request (DBGRQ) to the CPU. This causes the CPU to finish the instruction being executed, save the instruction pipeline information, enter debug mode, and wait for further commands.

NOTE: Asserting DBGRQ causes the device to exit stop, doze, or wait mode and to enter debug mode.

22.3.1 Debug Serial Input (TDI)

Data and commands are provided to the OnCE controller through the TDI pin. Data is latched on the rising edge of the TCLK serial clock. Data is shifted into the OnCE serial port least significant bit (LSB) first.

22.3.2 Debug Serial Clock (TCLK)

The TCLK pin supplies the serial clock to the OnCE control block. The serial clock provides pulses required to shift data and commands into and out of the OnCE serial port. (Data is clocked into the OnCE on the rising edge and is clocked out of the OnCE serial port on the falling edge.) The debug serial clock frequency must be no greater than 50 percent of the processor clock frequency.

22.3.3 Debug Serial Output (TDO)

Serial data is read from the OnCE block through the TDO pin. Data is always shifted out the OnCE serial port LSB first. Data is clocked out of the OnCE serial port on the falling edge of TCLK. TDO is three-stateable and is actively driven in the shift-IR and shift-DR controller states. TDO changes on the falling edge of TCLK.

22.3.4 Debug Mode Select (TMS)

The TMS input is used to cycle through states in the OnCE debug controller. Toggling the TMS pin while clocking with TCLK controls the transitions through the TAP state controller.

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22.3.5 Test Reset (TRST)

The TRST input is used to reset the OnCE controller externally by placing the OnCE control logic in a test logic reset state. OnCE operation is disabled in the reset controller and reserved states.

22.3.6 Debug Event (DE)

The DE pin is a bidirectional open drain pin. As an input, DE provides a fast means of entering debug mode from an external command controller. As an output, this pin provides a fast means of acknowledging debug mode entry to an external command controller.

The assertion of this pin by a command controller causes the CPU to finish the current instruction being executed, save the instruction pipeline information, enter debug mode, and wait for commands to be entered from the TDI line. If DE was used to enter debug mode, then DE must be negated after the OnCE responds with an acknowledgment and before sending the first OnCE command.

The assertion of this pin by the CPU acknowledges that it has entered debug mode and is waiting for commands to be entered from the TDI line.

319



The on-chip emulation (OnCE) circuitry provides a simple, inexpensive debugging interface that allows external access to the processor’s internal registers and to memory/peripherals. OnCE capabilities are controlled through a serial interface, mapped onto a JTAG test access port (TAP) protocol. Figure 22-3 shows the components of the OnCE circuitry.

22.4.1 Operation

An instruction is scanned into the OnCE module through the serial interface and then decoded. Data may then be scanned in and used to update a register or resource on a write to the resource, or data associated with a resource may be scanned out for a read of the resource.

Figure 22-3 OnCE Controller

For accesses to the CPU internal state, the OnCE controller requests the CPU to enter debug mode via the CPU DBGRQ input. Once the CPU enters debug mode, as indicated by the OnCE Status Register (OSR), the processor state may be accessed through the CPU Scan Register.

320


The OnCE controller is implemented as a 16-state finite state machine, with a one-to-one correspondence to the states defined for the JTAG TAP controller.

CPU registers and the contents of memory locations are accessed by scanning instructions and data into and out of the CPU scan chain. Required data is accessed by executing the scanned instructions. Memory locations may be read by scanning in a load instruction to the CPU that references the desired memory location, executing the load instruction, and then scanning out the result of the load. Other resources are accessed in a similar manner.

Resources contained in the OnCE module that do not require the CPU to be halted for access may be controlled while the CPU is executing and do not interfere with normal processor execution. Accesses to certain resources, such as the PC FIFO and the count registers, while not part of the CPU, may require the CPU to be stopped to allow access to avoid synchronization hazards. If it is known that the CPU clock is enabled and running no slower than the TCLK input, there is sufficient synchronization performed to allow reads but not writes of these specific resources. Debug firmware may ensure that it is safe to access these resources by reading the OSR to determine the state of the CPU prior to access. All other cases require the CPU to be in the debug state for deterministic operation.

22.4.2 OnCE Controller and Serial Interface

Figure 22-4 is a block diagram of the OnCE controller and serial interface.

The OnCE Command Register (OCMR) acts as the Instruction Register (IR) for the TAP controller. All other OnCE resources are treated as data registers (DR) by the TAP controller. The Command Register is loaded by serially shifting in commands during the TAP controller shift-IR state, and is loaded during the update-IR state. The OCMR selects a OnCE resource to be accessed as a DR during the TAP controller capture-DR, shift-DR and update-DR states.

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Figure 22-4 OnCE Controller and Serial Interface

22.4.3 OnCE Interface Signals

Figure 22-8 shows the interface signals for the OnCE controller. The following paragraphs describe the OnCE interface signals to other internal blocks associated with the OnCE controller. These signals are not available externally, and descriptions are provided to improve understanding of OnCE operation.

22.4.3.1 Internal Debug Request Input (IDR)

The internal debug request input is a hardware signal which is used in some implementations to force an immediate debug request to the CPU. If present and enabled, it functions in an identical manner to the control function provided by the DR control bit in the OCR. This input is maskable by a control bit in the OCR.

22.4.3.2 CPU Debug Request (DBGRQ)

The DBGRQ signal is asserted by the OnCE control logic to request the CPU to enter the debug state. It may be asserted for a number of different conditions. Assertion of this signal causes the CPU to finish the current instruction being executed, save the instruction pipeline information, enter debug mode, and wait for further commands. Asserting DBGRQ causes the device to exit stop, doze, or wait mode.

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22.4.3.3 CPU Debug Acknowledge (DBGACK)

The CPU asserts the DBGACK signal upon entering the debug state. This signal is part of the handshake mechanism between the OnCE control logic and the CPU.

22.4.3.4 CPU Breakpoint Request (BRKRQ)

The BRKRQ signal is asserted by the OnCE control logic to signal that a breakpoint condition has occurred for the current CPU bus access.

22.4.3.5 CPU Address, Attributes (ADDR, ATTR)

The CPU address and attribute information may be used in the memory breakpoint logic to qualify memory breakpoints with access address and cycle type information.

22.4.3.6 CPU Status (PSTAT)

The trace logic uses the PSTAT signals to qualify trace count decrements with specific CPU activity.

22.4.3.7 OnCE Debug Output (DEBUG)

The DEBUG signal is used to indicate to on-chip resources that a debug session is in progress. Peripherals and other units may use this signal to modify normal operation for the duration of a debug session. This may involve the CPU executing a sequence of instructions solely for the purpose of visibility/system control. These instructions are not part of the normal instruction stream that the CPU would have executed had it not been placed in debug mode. This signal is asserted the first time the CPU enters the debug state and remains asserted until the CPU is released by a write to the OnCE Command Register with the GO and EX bits set, and a register specified as either no register selected or the CPUSCR. This signal remains asserted even though the CPU may enter and exit the debug state for each instruction executed under control of the OnCE controller.

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22.4.4 OnCE Controller Registers

This section describes the OnCE controller registers:

OnCE Command Register (OCMR)

OnCE Control Register (OCR)

OnCE Status Register (OSR)

All OnCE registers are addressed by means of the RS field in the OCMR, as shown in Table 22-1.

22.4.4.1 OnCE Command Register

The OnCE Command Register (OCMR) is an 8-bit shift register that receives its serial data from the TDI pin. This register corresponds to the JTAG IR and is loaded when the update-IR TAP controller state is entered. It holds the 8-bit commands shifted in during the shift-IR controller state to be used as input for the OnCE decoder. The OCMR contains fields for controlling access to a OnCE resource, as well as controlling single-step operation, and exit from OnCE mode.

Although the OCMR is updated during the update-IR TAP controller state, the corresponding resource is accessed in the DR scan sequence of the TAP controller, and as such, the update-DR state must be transmitted through in order for an access to occur. In addition, the update-DR state must also be transitional through in order for the single-step and/or exit functionality to be performed, even though the command appears to have no data resource requirement associated with it.

7 6 5 4 3 2 1 0

R R/W G EX RS4 RS3 RS2 RS1 RS0

W

Figure 22-5 OnCE Command Register (OCMR)

R/W — Read/Write Bit 1= Read the data in the register specified by the RS field. 0= Write the data associated with the command into the register specified

by the RS field.

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GO — Go Bit When the GO bit is set, the device executes the instruction in the IR Register in the CPUSCR. To execute the instruction, the processor leaves debug mode, executes the instruction, and if the EX bit is cleared, returns to debug mode immediately after executing the instruction. The processor resumes normal operation if the EX bit is set. The GO command is executed only if the operation is a read/write to either the CPUSCR or to “no register selected.” Otherwise, the GO bit has no effect. The processor leaves debug mode after the TAP controller update-DR state is entered.

1= Execute instruction in IR 0= Inactive (no action taken)

EX — Exit Bit When the EX bit is set, the processor leaves debug mode and resumes normal operation until another debug request is generated. The exit command is executed only if the GO bit is set and the operation is a read/write to the CPUSCR or a read/write to “no register selected.” Otherwise, the EX bit has no effect. The processor exits debug mode after the TAP controller update-DR state is entered.

1= Leave debug mode 0= Remain in debug mode

RS4–RS0 — Register Select Field The RS field defines the source for the read operation or the destination for the write operation. Table 22-1 shows OnCE register addresses.

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Table 22-1 OnCE Register Addressing RS4–RS0 Register Selected

00000 Reserved

00001 Reserved

00010 Reserved

00011 OTC — OnCE trace counter

00100 MBCA — memory breakpoint counter A

00101 MBCB — memory breakpoint counter B

00110 PC FIFO — program counter FIFO and increment counter

00111 BABA — Breakpoint Address Base Register A

01000 BABB — Breakpoint Address Base Register B

01001 BAMA — Breakpoint Address Mask Register A

01010 BAMB — Breakpoint Address Mask Register B

01011 CPUSCR — CPU Scan Chain Register

01100 Bypass — no register selected

01101 OCR — OnCE Control Register

01110 OSR — OnCE Status Register

01111 Reserved (factory test control register — do not access)

10000 Reserved (MEM_BIST — do not access)

10001-10110 Reserved (bypass, do not access)

10111 Reserved (LSRL, do not access)

11000-11110 Reserved (bypass, do not access)

11111 Bypass

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22.4.4.2 OnCE Control Register

The 32-bit OnCE Control Register (OCR) selects the events that put the device in debug mode and enables or disables sections of the OnCE logic.

31 30 29 28 27 26 25 24

R 0 0 0 0 0 0 0 0

W

Reset 0 0 0 0 0 0 0 0

23 22 21 20 19 18 17 16

R 0 0 0 0 0 0 SQC1 SQC0

W

Reset 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8

R DR IDRE TME FRZC RCB BCB4 BCB3 BCB2

W

Reset 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

R BCB1 BCB0 RCA BCA4 BCA3 BCA2 BCA1 BCA0

W

Reset 0 0 0 0 0 0 0 0


Figure 22-6 OnCE Control Register (OCR)

SQC1 and SQC0 — Sequential Control Field The SQC field allows memory breakpoint B and trace occurrences to be suspended until a qualifying event occurs. Test logic reset clears the SQC field. See Table 22-2.

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Table 22-2 Sequential Control Field Settings SQC1 and SQC0 Meaning

00 Disable sequential control operation. Memory breakpoints and trace operation are unaffected by this field.

01

Suspend normal trace counter operation until a breakpoint condition occurs for memory breakpoint B. In this mode, memory breakpoint B occurrences no longer cause breakpoint requests to be generated. Instead, trace counter comparisons are suspended until the first memory breakpoint B occurrence. After the first memory breakpoint B occurrence, trace counter control is released to perform normally, assuming TME is set. This allows a sequence of breakpoint conditions to be specified prior to trace counting.

10

Qualify memory breakpoint B matches with a breakpoint occurrence for memory breakpoint A. In this mode, memory breakpoint A occurrences no longer cause breakpoint requests to be generated. Instead, memory breakpoint B comparisons are suspended until the first memory breakpoint A occurrence. After the first memory breakpoint A occurrence, memory breakpoint B is enabled to perform normally. This allows a sequence of breakpoint conditions to be specified.

11

Combine the 01 and 10 qualifications. In this mode, no breakpoint requests are generated, and trace count operation is enabled once a memory breakpoint B occurrence follows a memory breakpoint A occurrence if TME is set.

DR — Debug Request Bit DR requests the CPU to enter debug mode unconditionally. The PM bits in the OnCE Status Register indicate that the CPU is in debug mode. Once the CPU enters debug mode, it returns there even with a write to the OCMR with GO and EX set until the DR bit is cleared. Test logic reset clears the DR bit.

IDRE — Internal Debug Request Enable Bit The internal debug request (IDR) input to the OnCE control logic may not be used in all implementations. In some implementations, the IDR control input may be connected and used as an additional hardware debug request. Test logic reset clears the IDRE bit.

1= IDR input enabled 0= IDR input disabled

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TME — Trace Mode Enable Bit TME enables trace operation. Test logic reset clears the TME bit. Trace operation is also affected by the SQC field.

1= Trace operation enabled 0= Trace operation disabled

FRZC — Freeze Control Bit This control bit is used in conjunction with memory breakpoint B registers to select between asserting a breakpoint condition when a memory breakpoint B occurs or freezing the PC FIFO from further updates when memory breakpoint B occurs while allowing the CPU to continue execution. The PC FIFO remains frozen until the FRZO bit in the OSR is cleared.

1= Memory breakpoint B occurrence freezes PC FIFO and does not assert breakpoint condition.

0= Memory breakpoint B occurrence asserts breakpoint condition.

RCB and RCA — Memory Breakpoint B and A Range Control Bits RCB and RDA condition enabled memory breakpoint occurrences happen when memory breakpoint matches are either within or outside the range defined by memory base address and mask.

1= Condition breakpoint on access outside of range 0= Condition breakpoint on access within range

BCB4–BCB0 and BCA4–BCA0 — Memory Breakpoint B and A Control Fields The BCB and BCA fields enable memory breakpoints and qualify the access attributes to select whether the breakpoint matches are recognized for read, write, or instruction fetch (program space) accesses. Test logic reset clears BCB4–BCB0 and BCA4–BCA0.

Table 22-3 Memory Breakpoint Control Field Settings BCB4–BCB0 BCA4–BCA0

Description

00000 Breakpoint disabled

00001 Qualify match with any access

00010 Qualify match with any instruction access

00011 Qualify match with any data access

00100 Qualify match with any change of flow instruction access

00101 Qualify match with any data write

00110 Qualify match with any data read

00111 Reserved

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01XXX Reserved

10000 Reserved

10001 Qualify match with any user access

10010 Qualify match with any user instruction access

10011 Qualify match with any user data access

10100 Qualify match with any user change of flow access

10101 Qualify match with any user data write

10110 Qualify match with any user data read

10111 Reserved

11000 Reserved

11001 Qualify match with any supervisor access

11010 Qualify match with any supervisor instruction access

11011 Qualify match with any supervisor data access

11100 Qualify match with any supervisor change of flow access

11101 Qualify match with any supervisor data write

11110 Qualify match with any supervisor data read

11111 Reserved

22.4.4.3 OnCE Status Register

The 16-bit OnCE Status Register (OSR) indicates the reason(s) that debug mode was entered and the current operating mode of the CPU.

15 14 13 12 11 10 9 8

R 0 0 0 0 0 0 HDRO DRO

W

RESET: 0 0

7 6 5 4 3 2 1 0

R MBO SWO TO FRZO SQB SQA PM1 PM0

W

RESET: 0 0 0 0 0 0 0 0


Figure 22-7 OnCE Status Register (OSR)

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HDRO — Hardware Debug Request Occurrence Flag HDRO is set when the processor enters debug mode as a result of a hardware debug request from the IDR signal or the DE pin. This bit is cleared on test logic reset or when debug mode is exited with the GO and EX bits set.

DRO — Debug Request Occurrence Flag DRO is set when the processor enters debug mode and the debug request (DR) control bit in the OnCE Control Register is set. This bit is cleared on test logic reset or when debug mode is exited with the GO and EX bits set.

MBO — Memory Breakpoint Occurrence Flag MBO is set when a memory breakpoint request has been issued to the CPU via the BRKRQ input and the CPU enters debug mode. In some situations involving breakpoint requests on instruction prefetches, the CPU may discard the request along with the prefetch. In this case, this bit may become set due to the CPU entering debug mode for another reason. This bit is cleared on test logic reset or when debug mode is exited with the GO and EX bits set.

SWO — Software Debug Occurrence Flag SWO bit is set when the processor enters debug mode of operation as a result of the execution of the BKPT instruction. This bit is cleared on test logic reset or when debug mode is exited with the GO and EX bits set.

TO — Trace Count Occurrence Flag TO is set when the trace counter reaches zero with the trace mode enabled and the CPU enters debug mode. This bit is cleared on test logic reset or when debug mode is exited with the GO and EX bits set.

FRZO — FIFO Freeze Occurrence Flag FRZO is set when a FIFO freeze occurs. This bit is cleared on test logic reset or when debug mode is exited with the GO and EX bits set.

SQB — Sequential Breakpoint B Arm Occurrence Flag SQB is set when sequential operation is enabled and a memory breakpoint B event has occurred to enable trace counter operation. This bit is cleared on test logic reset or when debug mode is exited with the GO and EX bits set.

SQA — Sequential Breakpoint A Arm Occurrence Flag SQA is set when sequential operation is enabled and a memory breakpoint A event has occurred to enable memory breakpoint B operation. This bit is cleared on test logic reset or when debug mode is exited with the GO and EX bits set.

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PM1 and PM0 — Processor Mode Field These flags reflect the processor operating mode. They allow coordination of the OnCE controller with the CPU for synchronization.

Table 22-4 Processor Mode Field Settings PM1 and PM0

Meaning

00 Processor in normal mode

01 Processor in stop, doze, or wait mode

10 Processor in debug mode

11 Reserved

22.4.5 OnCE Decoder (ODEC)

The ODEC receives as input the 8-bit command from the OCMR and status signals from the processor. The ODEC generates all the strobes required for reading and writing the selected OnCE registers.

22.4.6 Memory Breakpoint Logic

Memory breakpoints can be set for a particular memory location or on accesses within an address range. The breakpoint logic contains an input latch for addresses, registers that store the base address and address mask, comparators, attribute qualifiers, and a breakpoint counter. Figure 22-8 illustrates the basic functionality of the OnCE memory breakpoint logic. This logic is duplicated to provide two independent breakpoint resources.

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Figure 22-8 OnCE Memory Breakpoint Logic

Address comparators can be used to determine where a program may be getting lost or when data is being written to areas which should not be written. They are also useful in halting a program at a specific point to examine or change registers or memory. Using address comparators to set breakpoints enables the user to set breakpoints in RAM or ROM

in any operating mode. Memory accesses are monitored according to the contents of the OCR. The address comparator generates a match signal when the address on the bus matches the address stored in the Breakpoint Address Base Register, as masked with individual bit masking capability provided by the Breakpoint Address Mask Register. The address match signal and the access attributes are further qualified with the RCx4–RCx0 and BCx4–BCx0 control bits. This qualification is used to decrement the breakpoint counter conditionally if its contents are non-zero. If the contents are zero, the counter is not decremented and the breakpoint event occurs (ISBKPTx asserted).

22.4.6.1 Memory Address Latch (MAL)

The MAL is a 32-bit register that latches the address bus on every access.

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22.4.6.2 Breakpoint Address Base Registers

The 32-bit Breakpoint Address Base Registers (BABA and BABB) store memory breakpoint base addresses. BABA and BABB can be read or written through the OnCE serial interface. Before enabling breakpoints, the external command controller should load these registers.

22.4.7 Breakpoint Address Mask Registers

The 32-bit Breakpoint Address Mask Registers (BAMA and BAMB) registers store memory breakpoint base address masks. BAMA and BAMB can be read or written through the OnCE serial interface. Before enabling breakpoints, the external command controller should load these registers.

22.4.7.1 Breakpoint Address Comparators

The breakpoint address comparators are not externally accessible. Each compares the memory address stored in MAL with the contents of BABx, as masked by BAMx, and signals the control logic when a match occurs.

22.4.7.2 Memory Breakpoint Counters

The 16-bit Memory Breakpoint Counter Registers (MBCA and MBCB) are loaded with a value equal to the number of times, minus one, that a memory access event should occur before a memory breakpoint is declared. The memory access event is specified by the RCx4–RCx0 and BCx4–BCx0 bits in the OCR and by the Memory Base and Mask Registers. On each occurrence of the memory access event, the breakpoint counter, if currently non-zero, is decremented. When the counter has reached the value of zero and a new occurrence takes place, the ISBKPTx signal is asserted and causes the CPU’s BRKRQ input to be asserted. The MBCx can be read or written through the OnCE serial interface.

Anytime the breakpoint registers are changed, or a different breakpoint event is selected in the OCR, the breakpoint counter must be written afterward. This assures that the OnCE breakpoint logic is reset and that no previous events will affect the new breakpoint event selected.

22.4.8 OnCE Trace Logic

The OnCE trace logic allows the user to execute instructions in single or multiple steps before the device returns to debug mode and awaits OnCE commands from the debug serial port. The OnCE trace logic is independent of the C*CORE trace facility, which is controlled through the trace mode bits in the C*CORE Processor Status Register. The OnCE trace logic block diagram is shown in Figure 22-9.

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22.4.8.1 OnCE Trace Counter

The OnCE Trace Counter Register (OTC) is a 16-bit counter that allows more than one instruction to be executed in real time before the device returns to debug mode. This feature helps the software developer debug sections of code that are time-critical. The trace counter also enables the user to count the number of instructions executed in a code segment.

Figure 22-9 OnCE Trace Logic Block Diagram

The OTC Register can be read, written, or cleared through the OnCE serial interface. If N instructions are to be executed before entering debug mode, the trace counter should be loaded with N – 1. N must not equal zero unless the sequential breakpoint control capability is being used. In this case a value of zero (indicating a single instruction) is allowed.

A hardware reset clears the OTC.

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22.4.8.2 Trace Operation

To initiate trace mode operation:

1. Load the OTC Register with a value. This value must be non-zero, unless sequential breakpoint control operation is enabled in the OCR Register. In this case, a value of zero (indicating a single instruction) is allowed.

2. Initialize the program counter and Instruction Register in the CPUSCR with values corresponding to the start location of the instruction(s) to be executed real-time.

3. Set the TME bit in the OCR.

4. Release the processor from debug mode by executing the appropriate command issued by the external command controller.

When debug mode is exited, the counter is decremented after each execution of an instruction. Interrupts can be serviced, and all instructions executed (including interrupt services) will decrement the trace counter.

When the trace counter decrements to zero, the OnCE control logic requests that the processor re-enter debug mode, and the trace occurrence bit TO in the OSR is set to indicate that debug mode has been requested as a result of the trace count function. The trace counter allows a minimum of two instructions to be specified for execution prior to entering trace (specified by a count value of one), unless sequential breakpoint control operation is enabled in the OCR. In this case, a value of zero (indicating a single instruction) is allowed.

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22.4.9 Methods of Entering Debug Mode

The PM status field in the OSR indicates that the CPU has entered debug mode. The following paragraphs discuss conditions that invoke debug mode.

22.4.9.1 Debug Request During RESET

When the DR bit in the OCR is set, assertion of RESET causes the device to enter debug mode. In this case the device may fetch the reset vector and the first instruction of the reset exception handler but does not execute an instruction before entering debug mode.

22.4.9.2 Debug Request During Normal Activity

Setting the DR bit in the OCR during normal device activity causes the device to finish the execution of the current instruction and then enter debug mode. Note that in this case the device completes the execution of the current instruction and stops after the newly fetched instruction enters the CPU instruction latch. This process is the same for any newly fetched instruction, including instructions fetched by interrupt processing or those that will be aborted by interrupt processing.

22.4.9.3 Debug Request During Stop, Doze, or Wait Mode

Setting the DR bit in the OCR when the device is in stop, doze, or wait mode (for instance, after execution of a STOP, DOZE, or WAIT instruction) causes the device to exit the low-power state and enter the debug mode. Note that in this case, the device completes the execution of the STOP, DOZE, or WAIT instruction and halts after the next instruction enters the instruction latch.

22.4.9.4 Software Request During Normal Activity

Executing the BKPT instruction when the FDB (force debug enable mode) control bit in the Control State Register is set causes the CPU to enter debug mode after the instruction following the BKPT instruction has entered the instruction latch.

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22.4.10 Enabling OnCE Trace Mode

When the OnCE trace mode mechanism is enabled and the trace count is greater than zero, the trace counter is decremented for each instruction executed. Completing execution of an instruction when the trace counter is zero causes the CPU to enter debug mode.

NOTE: Only instructions actually executed cause the trace counter to decrement. An aborted instruction does not decrement the trace counter and does not invoke debug mode.

22.4.11 Enabling OnCE Memory Breakpoints

When the OnCE memory breakpoint mechanism is enabled with a breakpoint counter value of zero, the device enters debug mode after completing the execution of the instruction that caused the memory breakpoint to occur. In case of breakpoints on instruction fetches, the breakpoint is acknowledged immediately after the execution of the fetched instruction. In case of breakpoints on data memory addresses, the breakpoint is acknowledged after the completion of the memory access instruction.

22.4.12 Pipeline Information and Write-Back Bus Register

A number of on-chip registers store the CPU pipeline status and are configured in the CPU Scan Chain Register (CPUSCR) for access by the OnCE controller. The CPUSCR is used to restore the pipeline and resume normal device activity upon return from debug mode. The CPUSCR also provides a mechanism for the emulator software to access processor and memory contents. Figure 22-10 shows the block diagram of the pipeline information registers contained in the CPUSCR.

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Figure 22-10 CPU Scan Chain Register (CPUSCR)

22.4.12.1 Program Counter Register

The Program Counter Register (PC) is a 32-bit latch that stores the value in the CPU program counter when the device enters debug mode. The CPU PC is affected by operations performed during debug mode and must be restored by the external command controller when the CPU returns to normal mode.

22.4.12.2 Instruction Register

The Instruction Register (IR) provides a mechanism for controlling the debug session. The IR allows the debug control block to execute selected instructions; the debug control module provides single-step capability.

When scan-out begins, the IR contains the opcode of the next instruction to be executed at the time debug mode was entered. This opcode must be saved in order to resume normal execution at the point debug mode was entered.

On scan-in, the IR can be filled with an opcode selected by debug control software in preparation for exiting debug mode. Selecting appropriate instructions allows a user to examine or change memory locations and processor registers.

Once the debug session is complete and normal processing is to be resumed, the IR can be loaded with the value originally scanned out.

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22.4.12.3 Control State Register

The Control State Register (CTL) is used to set control values when debug mode is exited. On scan-in, this register is used to control specific aspects of the CPU. Certain bits reflect internal processor status and should be restored to their original values.

The CTL register is a 16-bit latch that stores the value of certain internal CPU state variables before debug mode is entered. This register is affected by the operations performed during the debug session and should be restored by the external command controller when returning to normal mode. In addition to saved internal state variables, the bits are used by emulation firmware to control the debug process.

Reserved bits represent the internal processor state. Restore these bits to their original value after a debug session is completed, for example, when a OnCE command is issued with the GO and EX bits set and not ignored. Set these bits to 1s while instructions are executed during a debug session.

15 14 13 12 11 10 9 8

R RSVD RSVD RSVD RSVD RSVD RSVD RSVD FFY

W

RESET: 0

7 6 5 4 3 2 1 0

R FDB SZ1 SZ0 TC2 TC1 TC0 RSVD RSVD

W

RESET: 0 0 0 0 0 0


Figure 22-11 Control State Register (CTL)

FFY — Feed Forward Y Operand Bit This control bit is used to force the content of the WBBR to be used as the Y operand value of the first instruction to be executed following an update of the CPUSCR. This gives the debug firmware the capability of updating processor registers by initializing the WBBR with the desired value, setting the FFY bit, and executing a MOV instruction to the desired register.

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FDB — Force Debug Enable Mode Bit Setting this control bit places the processor in debug enable mode. In debug enable mode, execution of the BKPT instruction as well as recognition of the BRKRQ input causes the processor to enter debug mode, as if the DBGRQ input had been asserted.

SZ1 and SZ0 — Prefetch Size Field This control field is used to drive the CPU SIZ1 and SIZ0 outputs on the first instruction pre-fetch caused by issuing a OnCE command with the GO bit set and not ignored. It should be set to indicate a 16-bit size, for example, 0b10. This field should be restored to its original value after a debug session is completed, for example, when a OnCE command is issued with the GO and EX bits set and not ignored.

TC — Prefetch Transfer Code This control field is used to drive the CPU TC2–TC0 outputs on the first instruction pre-fetch caused by issuing a OnCE command with the GO bit set and not ignored. It should typically be set to indicate a supervisor instruction access, for example, 0b110. This field should be restored to its original value after a debug session is completed, for example, when a OnCE command is issued with the GO and EX bits set and not ignored.

22.4.12.4 Writeback Bus Register

The Writeback Bus Register (WBBR) is a means of passing operand information between the CPU and the external command controller. Whenever the external command controller needs to read the contents of a register or memory location, it forces the device to execute an instruction that brings that information to WBBR.

For example, to read the content of processor register r0, a MOV r0,r0 instruction is executed, and the result value of the instruction is latched into the WBBR. The contents of WBBR can then be delivered serially to the external command controller.

To update a processor resource, this register is initialized with a data value to be written, and a MOV instruction is executed which uses this value as a write-back data value. The FFY bit in the CTL Register forces the value of the WBBR to be substituted for the normal source value of a MOV instruction, thus allowing updates to processor registers to be performed.

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22.4.12.5 Processor Status Register

The Processor Status Register (PSR) is a 32-bit latch used to read or write the C*CORE Processor Status Register. Whenever the external command controller needs to save or modify the contents of the C*CORE Processor Status Register, the PSR is used. This register is affected by the operations performed in debug mode and must be restored by the external command controller when returning to normal mode.

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22.4.13 Instruction Address FIFO Buffer (PC FIFO)

To ease debugging activity and keep track of program flow, a first-in-first-out (FIFO) buffer stores the addresses of the last eight instruction change-of-flow prefetches that were issued.

The FIFO is a circular buffer containing eight 32-bit registers and one 3-bit counter. All the registers have the same address, but any read access to the FIFO address causes the counter to increment and point to the next FIFO register. The registers are serially available to the external command controller through the common FIFO address.Figure 22-12 shows the structure of the PC FIFO.

Figure 22-12 OnCE PC FIFO

The FIFO is not affected by operations performed in debug mode, except for incrementing the FIFO pointer when the FIFO is read. When debug mode is entered, the FIFO counter points to the FIFO register containing the address of the oldest of the eight change-of-flow pre-fetches. The first FIFO read obtains

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the oldest address, and the following FIFO reads return the other addresses from the oldest to the newest, in order of execution.

To ensure FIFO coherence, a complete set of eight reads of the FIFO must be performed. Each read increments the FIFO pointer, causing it to point to the next location. After eight reads, the pointer points to the same location as before the start of the read procedure.

The data in the FIFO is not affected by the read operations.

22.4.14 Reserved Test Control Registers

The reserved test control registers (MEM_BIST, FTCR, and LSRL) are reserved for factory testing.

To prevent damage to the device or system, do not access these registers during normal operation.

22.4.15 Serial Protocol

The serial protocol permits an efficient means of communication between the OnCE external command controller and the MCU. Before starting any debugging activity, the external command controller must wait for an acknowledgment that the device has entered debug mode. The external command controller communicates with the device by sending 8-bit commands to the OnCE Command Register and 16 to 128 bits of data to one of the other OnCE registers. Both commands and data are sent or received LSB first. After sending a command, the external command controller must wait for the processor to acknowledge execution of certain commands before it can properly access another OnCE Register.

22.4.16 OnCE Commands

The OnCE commands can be classified as:

Read commands (the device delivers the required data)

Write commands (the device receives data and writes the data in one of the OnCE registers)

Commands with no associated data transfers

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22.4.17 Target Site Debug System Requirements

A typical debug environment consists of a target system in which the MCU resides in the user-defined hardware.

The external command controller acts as the medium between the MCU target system and a host computer. The external command controller circuit acts as a serial debug port driver and host computer command interpreter. The controller issues commands based on the host computer inputs from a user interface program which communicates with the user.

22.4.18 Interface Connector for JTAG/OnCE Serial Port

Figure 22-13 shows the recommended connector pinout and interface requirements for debug controllers that access the JTAG/OnCE port. The connector has two rows of seven pins with 0.1-inch center-to-center spacing between pins in each row and each column.

Figure 22-13 Recommended Connector Interface to JTAG/OnCE Port

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Section 23 Pulse Width Modulator (PWM)

23.1 Introduction

PWM module consists of a simple free-running counter with two compare registers. Each compare register performs a particular task when it matches the count value. The period comparator causes the output pin to be set and the free-running counter to reset when period latch’s value matches the counter’s. The width comparator causes the output pin to reset when width latch’s value matches the counter’s. With a suitable lowpass filter, the PWM module can be used as a digital-to-analog converter.

23.2 Features

The Pulse Width Modulator includes these distinctive features:

Programmable period

Programmable duty cycle

Periodic interrupt capability

Pins can be configured as general-purpose I/O

346


23.3 Block Diagram

Figure 23-1 PWM Block Diagram

347



This subsection describes the three low-power modes and the debug mode.

23.4.1 Wait Mode

In wait mode, the PWM module continues to operate normally.

23.4.2 Doze Mode

When DOZE bit in control register is set, PWM can enter doze mode when CPU executes doze instruction. Otherwise, it is no effect to PWM. In doze mode, PWM still can generate interrupt if it is not disabled. PWM do not enter doze mode until the current send cycle is finished. In doze mode, PWM’s clock works always. Period, width registers and latches and counter are cleared. And control register, prescaler register are not effected.

23.4.3 Stop Mode

When CPU executes stop instruction, PWM enter mode instantly. Period, width registers and latches and counter are cleared. And control register and presecaler register are not effected.


Table 23-1 PWM Signal Description

Name I/O Width Reset State Description

PWMO I/O 1 0 PWMO pin

PWMO is used as a general-purpose input/output or as the PWM send output.

In default state, it is used as general-purpose input port.

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23.6.1 Memory Map


Address Bit[15:8] Bit[7:0] Access(34

0x00d6_0000

)

PWM control register (PWMCR) S/U

0x00d6_0002 PWM period register (PWMPR) S/U

0x00d6_0004 PWM width register (PWMWR) S/U

0x00d6_0006 PWM counter register (PWMCNTR) S/U

0x00d6_0008 PWM prescaler register (PWMPRESR) S/U

23.6.2 Registers

The PWM programming model consists of these registers:

The PWM Control Register (PWMCR) controls the function of the module. See 23.6.2.1 PWM Control Register.

The PWM Period Register (PWMPR) holds the value of period. See 23.6.2.2 PWM Period Register.

The PWM Width Register (PWMWR) holds the value of width. See 23.6.2.3 PWM Width Register.

The PWM Counter Register (PWMCNTR) is the counter of PWM. See 23.6.2.4 PWM Counter Register.

The PWM Prescaler Register (PWMPRESR) is used to configure the presacler. See 23.6.2.5 PWM Prescaler Register.

34S/U = CPU supervisor or user mode access.

349


23.6.2.1 PWM Control Register

The register (PWMCR) is used to control the PWM.

Address : 0x00d6_0000 and 0x00d6_0001

15 14 13 12 11 10 9 8

R 0 ISEL

DRIF DRIE SMDS DATA DIR MODE

W

RESET: 0 1 0 0 0 0 0 0

7 6 5 4 3 2 1 0

R 0 LOAD DOZE POL CNEN PREEN

0 0

W

RESET: 0 0 0 0 0 1 0 0


Figure 23-2 PWM Control Register (PWMCR)

ISEL — Interrupt Mode Select Bit The read/write ISEL bit selects the PWM interrupt modes. An interrupt request will occur when the width register is empty if DRIE is set.

1= The width register is full before any write access to PWMWR. 0= The width register is empty before any write access to PWMWR.

DRIF — Data Request Interrupt Flag The read-only DRIF bit is set when the width register is empty. When a period compare matched, the period and width comparator latches load new data from theirs corresponding registers, and the width register PWMWR becomes empty. This bit is cleared after any write to the PWMWR’s low byte.

1= PWMWR register is empty, new data is requested. 0= PWMWR register is full.

DRIE — Data Request Interrupt Enable Bit This bit allows the DRIF flag to generate interrupt request.

1= DRIF interrupt request enabled 0= DRIF interrupt request disabled

350


SMDS — Send Mode Select Bit The read/write bit selects the PWM send modes: single send mode, and continual send mode. In single send mode, the data is only sent in one period. After the sending, the period, width registers, theirs comparator latches and the counter are cleared. In the continued send mode, the same data will be sent repeatedly until the new data are loaded into the period register or the width register.

1= Continued send mode 0= Single send mode

DATA — PWM data bit This bit indicates or controls the current state of the PWM pin. When the PWM pin is configured as a general-purpose output, the logical value written to this bit is used to drive the pin. When the PWM pin is configured as a general-purpose input, the current pin status is reflected by this bit. When the PWM pin is configured in PWM mode, the bit reflects the value being driven on the pin by the PWM logic.

DIR — Direction bit The read/write bit controls the direction of the pin when used as a GPIO pin. This bit has no effect when MODE indicates PWM mode.

1= Pin is an output pin 0= Pin is an input pin

MODE — Mode select bit The read/write MODE bit selects whether the PWMO pin is used as GPIO or as the PWM function.

1= PWM mode 0= General-purpose I/O mode

LOAD — Force load bit The bit forces a load of period and width data from registers to latches. Also, it resets the counter. When the bit is set, an interrupt occurs because the registers’ data is loaded to latches and PWM can receive new data. The bit is cleared automatically after it is set. So, it is always read as zero. The actual loading occurs some time delay after the bit is set, because the loading occurs on the next count pulse edge following internal synchronization. Forcing a load of the comparator latches and counter in this manner must be done with caution to avoid unexpected pin behavior.

351


DOZE — Doze enable bit The bit determines whether responding the doze instruction. When it is zero, PWM does not respond CPU’s doze. When it is set, PWM can enter doze mode after finishing current send cycle, if CPU gives a doze signal. And an interrupt can still be generated if interrupt enable bit is set.

1= Respond doze mode 0= No respond doze mode

POL — Polarity Select Bit This bit controls the polarity of the pin when used as a PWM output pin. Normally, the output pin is set high at period boundaries and goes low when a width compare event occurs. This bit is ignored if the pin is being used as a GPIO pin.

1= Inverted PWM output polarity 0= Normal PWM output polarity

CNEN — Counter enable bit This bit enables the PWM counter which is the comparison source of the period and width. The counter is actually enabled or disabled some time delay after the operation to the bit, because of the internal synchronization. When it is set, the PWM works normally. When it is zero, the counter stops count after sending all data which have been written in and then the period, width registers and latches are cleared. The period and width can not be written until the bit is set again.

1= The counter is enabled 0= The counter is disabled

PREEN — Prescaler enable bit This bit enables the PWM prescaler. When it is set, the prescaler works normally. When it is clear, the prescaler is stopped. The PWM logical can not work normally.

1= Prescaler enabled 0= Prescaler disabled

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23.6.2.2 PWM Period Register

The PWM period register (PWMPR) controls the period of the PWM by defining the number of the count_pulse in the period. When the counter value matches the value in this register, an interrupt is posted and the counter is reset to start another period.

Address : 0x00d6_0002 and 0x00d6_0003

15 14 13 12 11 10 9 8

R 0 0 0 0 0 0 PERIOD9 PERIOD8

W

RESET: 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

R PERIOD7 PERIOD6 PERIOD5 PERIOD4 PERIOD3 PERIOD2 PERIOD1 PERIOD0

W

RESET: 0 0 0 0 0 0 0 0

= Writes have no effect and the access terminates without a transfer error

excePERIODtion.

Figure 23-3 PWM Period Register (PWMPR)

PERIOD[9:0] — Period data bit [9:0] The PERIOD bits define the period of the PWM.

NOTE:

The PWMPR can be set from 0 to 1023. And the register is not writable until CNEN bit in the PWM control register is set.

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23.6.2.3 PWM Width Register

The PWM width register (PWMWR) defines the width of the pulse. When the counter matches the value in this register, the output is reset for the duration of the period.

NOTE:

If the value in PWMWR is not less than the period register, the output will never be reset, resulting in a 100% duty cycle.

Address : 0x00d6_0004 and 0x00d6_0005

15 14 13 12 11 10 9 8

R 0 0 0 0 0 0 WIDTH9 WIDTH8

W

RESET: 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

R WIDTH7 WIDTH6 WIDTH5 WIDTH4 WIDTH3 WIDTH2 WIDTH1 WIDTH0

W

RESET: 0 0 0 0 0 0 0 0


Figure 23-4 PWM Width Register(PWMWR)

WIDTH[9:0] — Width data bit [9:0] The WIDTH bits define the pulse width.

NOTE:

The PWMWR register is readable at any time. The register value can be set from 0 to 1023. And it is not writable until the CNEN bit in the PWM control register is set.

When WIDTH[7:0] bits are written, the new data in the width and period registers are loaded into their corresponding comparator latches after current cycle finished

354


23.6.2.4 PWM Counter Register

The read-only PWM counter register (PWMCTR) holds the current count value. It can be read at any time without disturbing the counter.

Address : 0x00d6_0006 and 0x00d6_0007

15 14 13 12 11 10 9 8

R 0 0 0 0 0 0 CNT9 CNT8

W

RESET: 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

R CNT7 CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 CNT0

W

RESET: 0 0 0 0 0 0 0 0


Figure 23-5 PWM Counter Register (PWMCNTR)

CNT[9:0] — Counter bit [9:0] The read-only CNT bits hold the current count value.

355


23.6.2.5 PWM Prescaler Register

This register (PWMPRESR) is used to set prescaler.

Address : 0x00d6_0008 and 0x00d6_0009

15 14 13 12 11 10 9 8

R 0 0 0 0 0 0 PRE9 PRE8

W

RESET: 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

R PRE7 PRE6 PRE5 PRE4 PRE3 PRE2 PRE1 PRE0

W

RESET: 0 0 0 0 1 0 0 0


excePREtion.

Figure 23-6 PWM Prescaler Register (PWMPRESR)

PRE[9:0] — Prescaler bit [9:0] The data is used to configure the prescaler to generate proper count pluse. It can be set to n. (n is between 1 and 1023). Tcount_pluse = (n + 1) * Tsys

Here, Tsys is the system clock period. Tcount_pluse is a internal count pluse signal, which is used by PWM counter. When it is zero, the count pluse holds high always.

NOTE:

The prescaler is enable by the PREEN bit. And only when the P[7:0] bits is written, the setting is valid.

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23.7 Functional Descriptions

This subsection describes the PWM functional operation.

23.7.1 Prescaler

The prescaler of PWM clocks by system clock. It can be set by prescaler register. And it generates periodic count pulse.

When setting a new date to the prescaler register, the comparator in prescaler is not updated at once until prescaler’s counter reaches zero.

It can divide frequency by 2 to 1024.

It can be set through 10 bits prescaler set register. Only after the low byte of the set register is written, the setting is valid.

When it is set to zero, the output holds high. And when it is disabled, its output holds low.

23.7.2 PWM Core

The PWM CORE generates PWM logic mainly. Within which, there are one counter, period and width registers, period and width latches.

It can generate pulse-width modulation wave with 0 ~ 100% duty cycle. And the duty cycle is defined as (WIDTH / PERIOD). When WIDTH is zero, it is zero duty cycle. When WIDTH is not smaller than PERIOD, it is 100% duty cycle.

In normal mode, when width latch matches the counter, the output is pulled down; when period latch matches the counter, the output is pulled up if the following width data is not zero.

The period and width latches are contacted with the counter directly. And these latches are updated by their corresponding registers. Using one group of latches can ensure the continuous send without data losing.

The latches are updated by their registers when a send cycle is finished and width register has new data. So, it is convenient to send a group of data with the same period and you only need change the width register every cycle.

And it is commended that writing period register first and then writing width register. When writing in 8-bit mode, writing high byte of width register first and then low byte. This can ensure period and width updated to latches correctly.

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In single send mode, if width register is still empty after current cycle, no any update occurs and all registers and latches are cleared.

In continuous send mode, if width register is empty after current cycle, no update occurs, and registers and latches are not cleared, so PWM sends the last data over and over.

23.7.3 PWM Interrupt

Table 23-3 lists the interrupt requests generated by the PWM.

Table 23-3 PWM Interrupt Requests Interrupt Request Flag Enable Bit

Data Request DRIF DRIE

The DRIF flag is set when the width register is empty. The DRIE bit enables the DRIF flag to generate interrupt requests. Clear DRIF by writing a new data to the width register (PWMWR).

358


Section 24 Serial Peripheral Interface Modules

(SPI1/2)

24.1. Introduction

The serial peripheral interface (SPI) module allows full-duplex, synchronous, serial communication between the microcontroller unit (MCU) and peripheral devices. Software can poll the SPI status flags or SPI operation can be interrupt driven.

24.2. Features

Features include:

Master mode and slave mode

Word, half-word and byte transfer

Slave-select output

Mode fault error flag with central processor unit (CPU) interrupt capability

Double-buffered operation

Serial clock with programmable polarity and phase

Control of SPI operation during doze mode

Reduced drive control for lower power consumption

Support interrupt each 8, 16 or 32 bit transfer

359


24.3. Modes of Operation

The SPI functions in these three modes:

Run mode — Run mode is the normal mode of operation.

Doze mode — Doze mode is a configurable low-power mode.

Stop mode — The SPI is inactive in stop mode.

24.4. Block Diagram

Figure 24-1 SPI Block Diagram

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An overview of the signals is provided in Table 24-1.


Name Port Function35 Reset State

MISO1 SPIPORT1[0] Master Data In / Slave Data Out 0

MOSI1 SPIPORT1[1] Master Data Out / Slave Data In 0

SCK1 SPIPORT1[2] Serial Clock 0

SS1 SPIPORT1[3] Slave Select 0

MISO2 SPIPORT2[0] Master Data In / Slave Data Out 0

MOSI2 SPIPORT2[1] Master Data Out / Slave Data In 0

SCK2 SPIPORT2[2] Serial Clock 0

SS2 SPIPORT2[3] Slave Select 0

24.5.1 MISO (Master In/Slave Out)

MISO is one of the two SPI data pins.

In master mode, MISO is the data input.

In slave mode, MISO is the data output and is three-stated until a master drives the SS input pin low.

In bidirectional mode, a slave MISO pin is the SISO pin (slave in/slave out).

In a multiple-master system, all MISO pins are tied together.

24.5.2 MOSI (Master Out/Slave In)

MOSI is one of the two SPI data pins.

In master mode, MOSI is the data output.

In slave mode, MOSI is the data input.

In bidirectional mode, a master MOSI pin is the MOMI pin (master out/master in).

In a multiple-master system, all MOSI pins are tied together.

35The specific SPI ports (MISO,MOSI,SCK,SS) are GP I/O ports when the SPI is disabled (SPE=0).

361


24.5.3 SCK (Serial Clock)

The SCK pin is the serial clock pin for synchronizing transmissions between master and slave devices.

In master mode, SCK is an output.

In slave mode, SCK is an input.

In a multiple-master system, all SCK pins are tied together.

24.5.4 SS (Slave Select)

In master mode, the SS pin can be:

A mode-fault input

A general-purpose input

A general-purpose output

A slave-select output

In slave mode, the SS pin is always a slave-select input.

362



Table 24-2 shows the SPI memory map.

NOTE:

Reading reserved addresses (0x00d7(8)_004, 0x00d7(8)_005and 0x00d7(8)_0009 through 0x00d7(8)_000b) returns 0s. Writing to unimplemented addresses has no effect. Accessing unimplemented addresses does not generate an error response.

Table 24-2 SPI Memory Map

SPI1 Address

SPI2 Address

Bits 7–0 Access36

0x00d7_0000

0x00d8_0000 SPI Control Register 1 (SPICR1) S/U

0x00d7_0001 0x00d8_0001 SPI Control Register 2 (SPICR2) S/U

0x00d7_0002 0x00d8_0002 SPI Baud Rate Register (SPIBR) S/U

0x00d7_0003 0x00d8_0003 SPI Status Register (SPISR) S/U

0x00d7_0004 to

0x00d7_0005

0x00d8_0004 to

0x00d8_0005 Reserved S/U

0x00d7_0006 0x00d8_0006 SPI Pullup and Reduced Drive Register

(SPIPURD)37 S/U

0x00d7_0007 0x00d8_0007 SPI Port Data Register (SPIPORT) S/U

0x00d7_0008 0x00d8_0008 SPI Port Data Direction Register (SPIDDR) S/U

0x00d7_0009 to

0x00d7_000b

0x00d8_0009 to

0x00d8_000b Reserved S/U

0x00d7_000c to

0x00d7_000f

0x00d8_000c to

0x00d8_000f SPI Data Register (SPIDR) S/U

36S/U = CPU supervisor or user mode access. User mode accesses to supervisor only addresses

have no effect and result in a cycle termination transfer error. 37No effect in this part.

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24.6.1 SPI Control Register 1

Address: SPI1 --- 0x00d7_0000 SPI2 --- 0x00d8_0000

Bit 7 6 5 4 3 2 1 Bit 0

Read: SPIE SPE SPIM MSTR CPOL CPHA SSOE LSBFE

Write:

RESET: 0 0 0 0 0 1 0 0

Figure 24-2 SPI Control Register 1 (SPICR1)

Read: Anytime

Write: Anytime

SPIE — SPI Interrupt Enable Bit The SPIE bit enables the SPIF and MODF flags to generate interrupt requests. Reset clears SPIE.

1= SPIF and MODF interrupt requests enabled 0= SPIF and MODF interrupt requests disabled

SPE — SPI System Enable Bit The SPE bit enables the SPI and dedicates SPI port pins [3:0] to SPI functions. When SPE is clear, the SPI system is initialized but in a low-power disabled state. Reset clears SPE.

1= SPI enabled 0= SPI disabled

SPIM — SPI Mode Bit The SPIM bit configures the output buffers of SPI port pins [3:0] as open-drain outputs. SPIM controls SPI port pins [3:0] whether they are SPI outputs or general-purpose outputs. Reset clears SPIM.

1= Output buffers of SPI port pins [3:0] open-drain 0= Output buffers of SPI port pins [3:0] CMOS drive

MSTR — Master Bit The MSTR bit selects SPI master mode or SPI slave mode operation. Reset clears MSTR.

1= Master mode 0= Slave mode

364


CPOL — Clock Polarity Bit The CPOL bit selects an inverted or non-inverted SPI clock. To transmit data between SPI modules, the SPI modules must have identical CPOL values. Reset clears CPOL.

1= Active-low clock; SCK idles high 0= Active-high clock; SCK idles low

CPHA — Clock Phase Bit The CPHA bit delays the first edge of the SCK clock. Reset sets CPHA.

1= First SCK edge at start of transmission 0= First SCK edge 1/2 cycle after start of transmission

SSOE — Slave Select Output Enable Bit The SSOE bit and the DDRSP3 bit configure the SS pin as a general-purpose input or a slave-select output. Reset clears SSOE.

Table 24-3 SS Pin I/O Configurations

DDRSP3 SSOE Master Mode Slave Mode

0 0 Mode-fault input Slave-select input

0 1 General-purpose input Slave-select input

1 0 General-purpose output Slave-select input

1 1 Slave-select output Slave-select input

NOTE: Setting the SSOE bit disables the mode fault detect function.

LSBFE — LSB-First Enable Bit The LSBFE enables data to be transmitted LSB first. Reset clears LSBFE.

Data transmitted LSB first. Data transmitted MSB first

NOTE: In SPIDR, the MSB is always bit 31 regardless of the LSBFE bit.

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24.6.2 SPI Control Register 2


Bit7 6 5 4 3 2 1 Bit0

Read: WS[3:0] TSIZE[1:0] SPISDOZ SPC0

Write:

RESET: 0 0 0 0 0 0 0 0


Figure 24-3 SPI Control Register 2 (SPICR2)

Read: Anytime

Write: Anytime; writing to unimplemented bits has no effect

WS[3:0]— Wait States Field The WS field determines the number of wait states between every SPI byte transfer when SPI tsize is word/half-word in master mode. One wait state is equal to one SCK clock cycle. If WS is configured to zero wait states, then the time between SPI byte transfer is equal to one SCK cycle. A WS configured to one wait state means that the time between SPI byte transfer is (n+1) SCK cycle. Since the cycle between every SPI byte transfer is inserted by SPI internal logic after programming the number of wait states, software can adjust the bus timing to accommodate the access speed of the external device. With up to sixteen possible wait states, even slow devices can be interfaced with the MCU.

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Table 24-4 SPI Wait States Encoding

WS[3:0] Number of Wait

States(SCK)

0000 1

0001 2

0010 3

0011 4

0100 5

0101 6

0110 7

0111 8

1000 9

1001 10

1010 11

1011 12

1100 13

1101 14

1110 15

1111 16

TSIZE— SPI Transfer Size Bit The TSIZE[1:0] bits determines the transfer size of the bus cycle.

Table 24-5 Transfer Size Encoding

TSIZE[1:0] Transfer Size

0 0 Byte

0 1 Word

1 0 Halfword

1 1 Reserved

SPISDOZ — SPI Stop in Doze Bit

367


The SPIDOZ bit stops the SPI clocks when the CPU is in doze mode. Reset clears SPISDOZ.

1= SPI inactive in doze mode 0= SPI active in doze mode

SPC0 — Serial Pin Control Bit 0 The SPC0 bit enables the bidirectional pin configurations shown in Table 24-6. Reset clears SPC0.

Table 24-6 Bidirectional Pin Configurations

Pin Mode SPC0 MSTR MISO Pin38

MOSI Pin 39

SCK Pin 40 SS Pin

41

A

Normal 0

0 Slave data output

Slave data input

SCK input

Slave-select input

B 1 Master data input

Master data output

SCK output

MODF/GP input (DDRSP3 = 0) or GP output (DDRSP3 = 1)

C

Bidirectional 1

0 Slave data I/O

GP42 SCK input

I/O Slave-select input

D 1 GP I/O Master data I/O

SCK output

MODF/GP input (DDRSP3 = 0) or GP output (DDRSP3 = 1)

38Slave output is enabled if SPIDDR bit 0 = 1, SS = 0, and MSTR = 0 (A, C).

39Master output is enabled if SPIDDR bit 1 = 1 and MSTR = 1 (B, D).

40SCK output is enabled if SPIDDR bit 2 = 1 and MSTR = 1 (B, D).

41SS output is enabled if SPIDDR bit 3 = 1, SPICR1 bit 1 (SSOE) = 1, and MSTR = 1 (B, D). MODF

input is enabled

if SPI DDR bit 3 = 0 and SSOE = 0. GP input is enabled if SPI DDR bit 3 = 0 and SSOE = 1.

42GP = General-purpose

368


24.6.3 SPI Baud Rate Register


Bit 7 6 5 4 3 2 1 Bit 0

Read: 0 SPPR6 SPPR5 SPPR4

0 SPR2 SPR1 SPR0

Write:

RESET: 0 0 0 0 0 0 0 0


Figure 24-4 SPI Baud Rate Register (SPIBR)

Read: Anytime


SPPR[6:4] — SPI Baud Rate Preselection Bits The SPPR[6:4] and SPR[2:0] bits select the SPI clock divisor as shown in Table 24-7. Reset clears SPPR[6:4] and SPR[2:0], selecting an SPI clock divisor of 2.

SPR[2:0] — SPI Baud Rate Bits The SPPR[6:4] and SPR[2:0] bits select the SPI clock divisor as shown in Table 24-7. Reset clears SPPR[6:4] and SPR[2:0], selecting an SPI clock divisor of 2.

NOTE:

Writing to SPIBR during a transmission may cause spurious results.

Table 24-7 SPI Baud Rate Selection (33-MHz Module Clock)

SPPR[6:4]

SPR[2:0]

SPI Clock Divisor

Baud Rate SPPR[6:4

] SPR[2:0]

SPI Clock Divisor

Baud Rate

000 000 2 16.5 MHz 100 000 10 3.3 MHz

000 001 4 8.25 MHz 100 001 20 1.65 MHz

000 010 8 4.125 MHz 100 010 40 825 MHz

369


000 011 16 2.06 MHz 100 011 80 412.5 KHz

000 100 32 1.03 MHz 100 100 160 206.25 KHz

000 101 64 515.62

KHz 100 101 320 103.13 KHz

000 110 128 257.81

KHz 100 110 640 51.56 KHz

000 111 256 128.9 KHz 100 111 1280 25.78 KHz

001 000 4 8.25 MHz 101 000 12 2.75 MHz

001 001 8 4.12 MHz 101 001 24 1.375 MHz

001 010 16 2.06 MHz 101 010 48 687.5 KHz

001 011 32 1.03 MHz 101 011 96 343.75 KHz

001 100 64 515.62

KHz 101 100 192 171.88 KHz

001 101 128 257.81

KHz 101 101 384 85.94 KHz

001 110 256 128.9 KHz 101 110 768 42.97 KHz

001 111 512 64.45 KHz 101 111 1536 21.48 KHz

010 000 6 5.5 MHz 110 000 14 2.36 MHz

010 001 12 2.75 MHz 110 001 28 1.18 MHz

010 010 24 1.375 MHz 110 010 56 589.29 KHz

010 011 48 687.5 KHz 110 011 112 296.64 KHz

010 100 96 343.75

KHz 110 100 224 147.32 KHz

010 101 192 171.88

KHz 110 101 448 73.66 KHz

010 110 384 85.94 KHz 110 110 896 36.83 KHz

010 111 768 42.97 KHz 110 111 1792 18.42 KHz

370


011 000 8 4.13 MHz 111 000 16 2.06 MHz

011 001 16 2.06 MHz 111 001 32 1.03 MHz

011 010 32 1.03 MHz 111 010 64 515.63 KHz

011 011 64 515.63

KHz 111 011 128 257.81 KHz

011 100 128 257.81

KHz 111 100 256 128.91 KHz

011 101 256 128.91

KHz 111 101 512 64.45 KHz

011 110 512 64.45 KHz 111 110 1024 32.23 KHz

011 111 1024 32.23 KHz 111 111 2048 16.11 KHz

24.6.4 SPI Status Register


Bit 7 6 5 4 3 2 1 Bit 0

Read: SPIF WCOL 0 MODF 0 0 0 0

Write:

RESET: 0 0 0 0 0 0 0 0


Figure 24-5 SPI Status Register (SPISR)

Read: Anytime Write: Has no meaning or effect

371


SPIF — SPI Interrupt Flag The SPIF flag is set when received data transfers from the shift register to SPIDR, including 8bit,16bit or 32bit determined by tsize. If the SPIE bit is also set, SPIF generates an interrupt request. Once SPIF is set, no new data can be transferred into SPIDR until SPIF is cleared. Clear SPIF by reading SPISR with SPIF set and then accessing SPIDR. Reset clears SPIF.

1= New data available in SPIDR 0= No new data available in SPIDR

WCOL — Write Collision Flag The WCOL flag is set when software writes to SPIDR during a transmission. Clear WCOL by reading SPISR with WCOL set and then accessing SPIDR. Reset clears WCOL.

1= Write collision 0= No write collision

MODF — Mode Fault Flag The MODF flag is set when the SS pin of a master SPI is driven low and the SS pin is configured as a mode-fault input. If the SPIE bit is also set, MODF generates an interrupt request. A mode fault clears the SPE, MSTR, and DDRSP[2:0] bits. Clear MODF by reading SPISR with MODF set and then writing to SPICR1. Reset clears MODF.

1= Mode fault 0= No mode fault

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24.6.5 SPI Pullup and Reduced Drive Register


Bit 7 6 5 4 3 2 1 Bit 0

Read: 0 0 RSVD5

0 0 0 RSVD1 PUPSP

Write:

RESET: 0 0 0 0 0 0 0 0

Figure 24-6 SPI Pullup and Reduced Drive Register (SPIPURD)

Read: Anytime;


RSVD5 and RSVD1 — Reserved Writing to these read/write bits updates their values but has no effect on functionality.

PUPSP — SPI Port Pullup Enable Bit 1= Pullup devices enabled for SPIPORT bits [3:0] 0= Pullup devices disabled for SPIPORT bits [3:0]

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24.6.6 SPI Port Data Register


Bit 7 6 5 4 3 2 1 Bit 0

Read: RSVD7 RSVD6 RSVD5 RSVD4 PORTSP3 PORTSP2 PORTSP1 PORTSP0

Write:

RESET: 0 0 0 0 0 0 0 0

Pin function:

SS SCK MOSI/ MISO/

MOMI SISO

Figure 24-7 SPI Port Data Register (SPIPORT)

Read: Anytime

Write: Anytime

RSVD[7:4] — Reserved

Writing to these read/write bits updates their values but has no effect on functionality.

PORTSP[3:0] — SPI Port Data Bits

Data written to SPIPORT drives pins only when they are configured as general-purpose outputs.

Reading an input (DDRSP bit clear) returns the pin level; reading an output (DDRSP bit set) returns the pin driver input level.

Writing to any of the PORTSP[3:0] pins does not change the pin state when the pin is configured for SPI output.

SPIPORT I/O function depends upon the state of the SPE bit in SPICR1 and the state the DDRSP bits in SPIDDR.

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24.6.7 SPI Port Data Direction Register


Bit 7 6 5 4 3 2 1 Bit 0

Read: RSVD7 RSVD6 RSVD5 RSVD4 DDRSP3 DDRSP2 DDRSP1 DDRSP0

Write:

RESET: 0 0 0 0 0 0 0 0

Pin function: SS SCK MOSI/ MISO/

MOMI SISO

Figure 24-8 SPI Port Data Direction Register (SPIDDR)

Read: Anytime

Write: Anytime

RSVD[7:4] — Reserved

Writing to these read/write bits updates their values but has no effect on functionality.

DDRSP[3:0] — Data Direction Bits The DDRSP[3:0] bits control the data direction of SPIPORT pins. Reset clears DDRSP[3:0].


In slave mode, DDRSP3 has no meaning or effect. In master mode, the DDRSP3 and the SSOE bits determine whether SPI port pin 3 is a mode-fault input, a general-purpose input, a general-purpose output, or a slave-select output.

NOTE:

When the SPI is enabled (SPE = 1), the MISO, MOSI, and SCK pins:

• Are inputs if their SPI functions are input functions regardless of the state of their DDRSP bits.

• Are outputs if their SPI functions are output functions only if their DDRSP bits are set

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24.6.8 SPI Data Register

Address: SPI1 --- 0x00d7_000c~0x00d7_000f SPI2 --- 0x00d8_000c~0x00d8_000f

Bit 31 30 29 28 27 26 25 Bit 24

Read: SPIDR[31:24]

Write:

RESET: 0 0 0 0 0 0 0 0

Bit 23 22 21 20 19 18 17 Bit 16

Read: SPIDR[23:16]

Write:

RESET: 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 Bit 8

Read: SPIDR[15:8]

Write:

RESET: 0 0 0 0 0 0 0 0

Bit7 6 5 4 3 2 1 Bit 0

Read: SPIDR[7:0]

Write:

RESET: 0 0 0 0 0 0 0 0

Figure 24-9 SPI Data Register (SPIDR)

Read: Anytime; normally read only after SPIF is set

Write: Anytime; see WCOL

SPIDR is both the input and output register for SPI data. Writing to SPIDR while a transmission is in progress sets the WCOL flag and disables the attempted write. Read SPIDR after the SPIF flag is set and before the end of the next transmission. If the SPIF flag is not serviced before a new data enters the shift register, the new data and any successive data are lost. The data already in the SPIDR remains there until SPIF is serviced.

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The SPI module allows full-duplex, synchronous, serial communication between the MCU and peripheral devices. Software can poll the SPI status flags or SPI operation can be interrupt driven.

Setting the SPE bit in SPICR1 enables the SPI and dedicates four SPI port pins to SPI functions:

Slave select (SS)

Serial clock (SCK)

Master out/slave in (MOSI)

Master in/slave out (MISO)

When the SPE bit is clear, the SS, SCK, MOSI, and MISO pins are general-purpose I/O pins controlled by SPIDDR.

The 8-bit shift register in a master SPI is linked by the MOSI and MISO pins to the 8-bit shift register in the slave. The linked shift registers form a distributed 16-bit register. In an SPI transmission, the SCK clock from the master shifts the data in the 16-bit register eight bit positions, and the master and slave exchange data. Data written to the master SPIDR register is the output data to the slave. After the exchange, data read from the master SPIDR is the input data from the slave.

Figure 24-10 Full-Duplex Operation

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24.7.1 Master Mode

Setting the MSTR bit in SPICR1 puts the SPI in master mode. Only a master SPI can initiate a transmission. Writing to the master SPIDR begins a transmission. If the shift register is empty, the data transfers to the shift register and begins shifting out on the MOSI pin under the control of the master SCK clock. The SCK clock starts one-half SCK cycle after writing to SPIDR.

The SPR[2:0] and SPPR[6:4] bits in SPIBR control the baud rate generator and determine the speed of the shift register. The SCK pin is the SPI clock output. Through the SCK pin, the baud rate generator of the master controls the shift register of the slave.

The MSTR bit in SPICR1 and the SPC0 bit in SPICR2 control the function of the data pins, MOSI and MISO.

The SS pin is normally an input that remains in the inactive high state. Setting the DDRSP3 bit in SPIDDR configures SS as an output. The DDRSP3 bit and the SSOE bit in SPICR1 can configure SS for general-purpose I/O, mode fault detection, or slave selection. See Table 24-3

The SS output goes low during each transmission and is high when the SPI is in the idle state. Driving the master SS input low sets the MODF flag in SPISR, indicating a mode fault. More than one master may be trying to drive the MOSI and SCK lines simultaneously. A mode fault clears the data direction bits of the MISO, MOSI (or MOMI), and SCK pins to make them inputs. A mode fault also clears the SPE and MSTR bits in SPICR1. If the SPIE bit is also set, the MODF flag generates an interrupt request.

24.7.2 Slave Mode

Clearing the MSTR bit in SPICR1 puts the SPI in slave mode. The SCK pin is the SPI clock input from the master, and the SS pin is the slave-select input. For a transmission to occur, the SS pin must be driven low and remain low until the transmission is complete.

The MSTR bit and the SPC0 bit in SPICR2 control the function of the data pins, MOSI and MISO. The SS input also controls the MISO pin. If SS is low, the MSB in the shift register shifts out on the MISO pin. If SS is high, the MISO pin is in a high impedance state, and the slave ignores the SCK input.

NOTE:

When using peripherals with full-duplex capability, do not simultaneously enable two receivers that drive the same MISO output line.

As long as only one slave drives the master input line, it is possible for several slaves to receive the same transmission simultaneously.

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If the CPHA bit in SPICR1 is clear, odd-numbered edges on the SCK input latch the data on the MOSI pin. Even-numbered edges shift the data into the LSB position of the SPI shift register and shift the MSB out to the MISO pin.

If the CPHA bit is set, even-numbered edges on the SCK input latch the data on the MOSI pin. Odd-numbered edges shift the data into the LSB position of the SPI shift register and shift the MSB out to the MISO pin.

The transmission is complete after the eighth shift. The received data transfers to SPIDR, setting the SPIF flag in SPISR.

24.7.3 Transmission Formats

The CPHA and CPOL bits in SPICR1 select one of four combinations of serial clock phase and polarity. Clock phase and polarity must be identical for the master SPI device and the communicating slave device.

24.7.3.1 Transfer Format When CPHA = 1

Some peripherals require the first SCK edge to occur before the slave MSB becomes available at its MISO pin. When the CPHA bit is set, the master SPI waits for a synchronization delay of one-half SCK clock cycle. Then it issues the first SCK edge at the beginning of the transmission. The first edge causes the slave to transmit its MSB to the MISO pin of the master. The second edge and the following even-numbered edges latch the data. The third edge and the following odd-numbered edges shift the latched slave data into the master shift register and shift master data out on the master MOSI pin.

After the 16th and final SCK edge:

Data that was in the master SPIDR register is in the slave SPIDR. Data that was in the slave SPIDR register is in the master SPIDR.

The SCK clock stops and the SPIF flag in SPISR is set, indicating that the transmission is complete. If the SPIE bit in SPCR1 is set, SPIF generates an interrupt request.

Figure 24-11shows the timing of a transmission with the CPHA bit set. The SS pin of the master must be either high or configured as a general-purpose output not affecting the SPI.

When CPHA = 1, the slave SS line can remain low between bytes. This format is good for systems with a single master and a single slave driving the MISO data line.

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Writing to SPIDR while a transmission is in progress sets the WCOL flag to indicate a write collision and inhibits the write. WCOL does not generate an interrupt request; the SPIF interrupt request comes at the end of the transfer that was in progress at the time of the error.

Figure 24-11 SPI Clock Format 1 (CPHA = 1)

24.7.3.2 Transfer Format When CPHA = 0

In some peripherals, the slave MSB is available at its MISO pin as soon as the slave is selected. When the CPHA bit is clear, the master SPI delays its first SCK edge for half a SCK cycle after the transmission starts. The first edge and all following odd-numbered edges latch the slave data. Even-numbered SCK edges shift slave data into the master shift register and shift master data out on the master MOSI pin.

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After the 16th and final SCK edge:

Data that was in the master SPIDR is in the slave SPIDR. Data that was in the slave SPIDR is in the master SPIDR.

The SCK clock stops and the SPIF flag in SPISR is set, indicating that the transmission is complete. If the SPIE bit in SPCR1 is set, SPIF generates an interrupt request.

Figure 24-12 shows the timing of a transmission with the CPHA bit clear. The SS pin of the master must be either high or configured as a general-purpose output not affecting the SPI.

When CPHA = 0, the slave SS pin must be negated and reasserted between bytes.

Figure 24-12 SPI Clock Format 0 (CPHA = 0)

NOTE:

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Clock skew between the master and slave can cause data to be lost when:

CPHA = 0, and,

The baud rate is the SPI clock divided by two, and

The master SCK frequency is half the slave SPI clock frequency, and

Software writes to the slave SPIDR just before the synchronized SS signal goes low.

The synchronized SS signal is synchronized to the SPI clock. Figure 24-13 shows an example with the synchronized SS signal almost a full SPI clock cycle late. While the synchronized SS of the slave is high, writing is allowed even though the SS pin is already low. The write can change the MISO pin while the master is sampling the MISO line. The first bit of the transfer may not be stable when the master samples it, so the byte sent to the master may be corrupted.

Figure 24-13 Transmission Error Due to Master/Slave Clock Skew

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Also, if the slave generates a late write, its state machine may not have time to reset, causing it to incorrectly receive a byte from the master.

This error is most likely when the SCK frequency is half the slave SPI clock frequency. At other baud rates, the SCK skew is no more than one SPI clock, and there is more time between the synchronized SS signal and the first SCK edge. For example, with a SCK frequency one-fourth the slave SPI clock frequency, there are two SPI clocks between the fall of SS and the SCK edge.

As long as another late SPIDR write does not occur, the following bytes to and from the slave are correctly transmitted.

24.7.4 SPI Baud Rate Generation

The baud rate generator divides the SPI clock to produce the SPI baud clock. The SPPR[6:4] and SPR[2:0] bits in SPIBR select the SPI clock divisor:

where:

SPPR = the value written to bits SPPR[6:4]

SPR = the value written to bits SPR[2:0]

The baud rate generator is active only when the SPI is in master mode and transmitting. Otherwise, the divider is inactive to reduce IDD current.

24.7.5 Slave-Select Output

The slave-select output feature automatically drives the SS pin low during transmission to select external devices and drives it high during idle to deselect external devices. When SS output is selected, the SS output pin is connected to the SS input pin of the external device.

In master mode only, setting the SSOE bit in SPICR1 and the DDRSP[3] bit in SPIDDR configures the SS pin as a slave-select output.

Setting the SSOE bit disables the mode fault feature.

NOTE:

Be careful when using the slave-select output feature in a multimaster system. The mode fault feature is not available for detecting system errors between masters.

24.7.6 Bidirectional Mode

Setting the SPC0 bit in SPICR1 selects bidirectional mode (see Table 24-8). The SPI uses only one data pin for the interface with external device(s). The MSTR bit determines which pin to use. In master mode, the MOSI pin is the

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master out/master in pin, MOMI. In slave mode, the MISO pin is the slave out/slave in pin, SISO. The MISO pin in master mode and MOSI pin in slave mode are general-purpose I/O pins.

The direction of each data I/O pin depends on its data direction register bit. A pin configured as an output is the output from the shift register. A pin configured as an input is the input to the shift register, and data coming out of the shift register is discarded.

The SCK pin is an output in master mode and an input in slave mode.

The SS pin can be an input or an output in master mode, and it is always an input in slave mode.

In bidirectional mode, a mode fault does not clear DDRSP0, the data direction bit for the SISO pin.

Table 24-8 Normal Mode and Bidirectional Mode

SPE = 1 Master Mode, MSTR = 1 Slave Mode, MSTR = 0

Normal Mode SPC0 = 0

SPIM enables open drain output.

SPIM enables open drain output.

Bidirectional Mode SPC0 = 1

SPIM enables open drain output. SPI port pin 0 is general-purpose I/O.

SPIM enables open drain output. SPI port pin 1 is general-purpose I/O.

24.7.7 Error Conditions

The SPI has two error conditions:

Write collision error

Mode fault error

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24.7.7.1 Write Collision Error

The WCOL flag in SPISR indicates that a serial transfer was in progress when the MCU tried to write new data to SPIDR. Valid write times are listed below (see Figure 24-11 and Figure 24-12 for definitions of tT and tI):

In master mode, a valid write is within tI (when SS is high).

In slave phase 0, a valid write is within tI (when SS is high).

In slave phase 1, a valid write is within tT or tI (after the last SCK edge and before SS goes low), excluding the first two SPI clocks after the last SCK edge (the beginning of tT is an illegal write).

A write during any other time causes a WCOL error. The write is disabled to avoid writing over the data being transmitted. WCOL does not generate an interrupt request because the WCOL flag can be read upon completion of the transmission that was in progress at the time of the error.

24.7.7.2 Mode Fault Error

If the SS input of a master SPI goes low, it indicates a system error in which more than one master may be trying to drive the MOSI and SCK lines simultaneously. This condition is not permitted in normal operation; it sets the MODF flag in SPISR. If the SPIE bit in SPICR1 is also set, MODF generates an interrupt request.

Configuring the SS pin as a general-purpose output or a slave-select output disables the mode fault function.

A mode fault clears the SPE and MSTR bits and the DDRSP bits of the SCK, MISO, and MOSI (or MOMI) pins. This forces those pins to be high-impedance inputs to avoid any conflict with another output driver. If the mode fault error occurs in bidirectional mode, the DDRSP bit of the SISO pin is not affected, since it is a general-purpose I/O pin.

24.7.8 Low-Power Mode Options

This subsection describes the low-power mode options.

24.7.8.1 Run Mode

Clearing the SPE bit in SPICR1 puts the SPI in a disabled, low-power state. SPI registers are accessible, but SPI clocks are disabled.

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24.7.8.2 Doze Mode

SPI operation in doze mode depends on the state of the SPISDOZ bit in SPICR2.

If SPISDOZ is clear, the SPI operates normally in doze mode.

If SPISDOZ is set, the SPI clock stops, and the SPI enters a low-power state in doze mode.

- Any master transmission in progress stops at doze mode entry and resumes at doze mode exit.

- Any slave transmission in progress continues if a master continues to drive the slave SCK pin. The slave stays synchronized to the master SCK clock.

NOTE:

Although the slave shift register can receive MOSI data, it cannot transfer data to SPIDR or set the SPIF flag in doze or stop mode. If the slave enters doze mode in an idle state and exits doze mode in an idle state, SPIF remains clear and no transfer to SPIDR occurs.

24.7.8.3 Stop Mode

SPI operation in stop mode is the same as in doze mode with the SPISDOZ bit set.

24.8 Reset

Reset initializes the SPI registers to a known startup state as described in 24.6 Memory Map and Registers. A transmission from a slave after reset and before writing to the SPIDR register is either indeterminate or the byte last received from the master before the reset. Reading the SPIDR after reset returns 0s.

24.9 Interrupts

SPI Interrupt Request Sources

Interrupt Request Flag Enable Bit

Mode fault MODF SPIE

Transmission complete SPIF

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24.9.1 Mode Fault (MODF) Flag

MODF is set when the SS pin of a master SPI is driven low and the SS pin is configured as a mode-fault input. If the SPIE bit is also set, MODF generates an interrupt request. A mode fault clears the SPE, MSTR, and DDRSP[2:0] bits. Clear MODF by reading SPISR with MODF set and then writing to SPICR1. Reset clears MODF.

24.9.2 SPI Interrupt Flag (SPIF)

SPIF is set after the eighth SCK cycle in a transmission when received data transfers from the shift register to SPIDR. If the SPIE bit is also set, SPIF generates an interrupt request. Once SPIF is set, no new data can be transferred into SPIDR until SPIF is cleared. Clear SPIF by reading SPISR with SPIF set and then accessing SPIDR. Reset clears SPIF.

24.9.3 SPI Word/Half- word Transfer in master mode

Figure 24-14 SPI Word/Half-word Transfer in master mode

When the TSIZE bit in SPICR2 is configured to 2’b01(word) or 2’b10(half-word), the data (word or half-word) is separated into 4 or 2 bytes to transfer. The WS field determines the number of wait states between every SPI byte transfer in master mode. One wait state is equal to one SCK clock cycle. See Figure 24-14 SPI Word/Half-word Transfer in master mode, If WS is configured to zero wait states, then the time between SPI byte transfer is equal to one SCK cycle, which means the SS keep high for one SCK. When WS is one, then the time between SPI byte transfer is two SCK cycle. The WS can be configured up to sixteen possible wait states, please refer to Table 24-4 SPI Wait States Encoding.

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Section 25 Encryption Module Wrapper

25.1 Introduction

The encryption module wrapper is responsible for typical encryption modules to speed up the encryption process. When the encryption wrapper (EW) is enabled, EW will control the encryption devices instead of CPU.

25.2 Features

Features of the encryption wrapper include:

Reduced system complexity — No external glue logic required for typical systems if encryption selection enable is set.

Programmable encryption length (up to 64K).

Programmable interrupt mechanism, according to the encryption devices.

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25.3 Block Diagram

Figure25-1 Encryption Wrapper Diagram


The Encryption Wrapper can be configured to control SM1, 3DES and other encryption devices. Normally, when the preconfiguration process is finished, the Encryption Wrapper will be enabled to execute encryption process automatically.


Table 25-1 Encryption Wrapper Memory Map

Address Bits 31-0 Access (1)

0x00da_0000 Encryption Wrapper Control Register (EWCR) S/U

0x00da_0004 Encryption Wrapper State Register (EWSR) S/U

1. S = CPU supervisor mode access only. U=User mode accesses to supervisor-only address

locations have no effect and result in a cycle termination transfer error.

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25.6 Register Description

25.6.1 Encryption Wrapper Control Register (EWCR)

Register address : 0x00da_0000

31 30 29 28 27 26 25 24

R SUM15 SUM14 SUM13 SUM12 SUM11 SUM10 SUM9 SUM8

W

RESET: 0 0 0 0 0 0 0 0

23 22 21 20 19 18 17 16

R SUM7 SUM6 SUM5 SUM4 SUM3 SUM2 SUM1 SUM0

W

RESET: 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8

R 0 0 0 0 SRAM_FIFO_SEL

W

RESET: 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

R ENCR1 ENCR0

0 0 0 0 EN IE

W

RESET: 0 0 0 0 0 0 0 0


Figure25-2 Encryption Wrapper Control Register (EWCR)

SUM[15:0] — Encryption Data Total Number The SUM field controls the encryption counter of the Encryption Wrapper.

SRAM_FIFO_SEL[11:8] — Set FIFO Index Number The SRAM_FIFO_SEL field sets the FIFO index number, there’re 16 FIFOs for EW to read/write data. When choose one of the FIFOs, the encryption process will be operated in this chosen FIFO.

ENCR[1:0] — Choose Encryption Device Module The ENCR field configures the encryption device module chip enable.

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Table 25-2 Corresponding Encryption Device Module Choose ENCR[1:0] 2’b00 2’b01 2’b10

Choose Module SM1 3DES SMS4

NOTE: ENCR[1:0] only supports three encryption devices in TF32A09 chip.

EN — Enable Bit This bit enables the Encryption Wrapper function. When EWDONE set, this bit will be cleared to 0 automatically.

1= Enable the encryption wrapper 0= Disable the encryption wrapper

IE — Interrupt Enable Bit The IE bit enables the EW to generate interrupt requests.

1= Enable the encryption wrapper Interrupt 0= Disable the encryption wrapper Interrupt

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25.6.2 Encryption Wrapper State Register (EWSR)

Register address : 0x00da_0004

31 30 29 28 27 26 25 24

R 0 0 0 0 0 0 0 0

W

RESET: 0 0 0 0 0 0 0 0

23 22 21 20 19 18 17 16

R 0 0 0 0 0 0 0 0

W

RESET: 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8

R 0 0 0 0 0 0 0 0

W

RESET: 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

R 0 0 0 0 0 0 EWDONE 0

W

RESET: 0 0 0 0 0 0


EWDONE — Encryption Wrapper Is Done EWDONE is set when encryption wrapper finishes corresponding encryption process. When EWDONE is set, the target data is encrypted/decrypted. EWDONE will generate interrupt to C*Core if IE bit is set in EWCR. Clear EWDONE by writing "1" to it.

1= Finish encryption process 0= Not finish encryption process

NOTE:

To begin a new encryption process, CPU should set EN bit in EWCR again.

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Section 26KeyPad Port Module (KPP)

26.1 Introduction

The Keypad Port is a 32-bit peripheral which can be used either for keypad matrix scanning or as general purpose I/O. The block diagram of the KPP is shown in the following (see Figure 26-1 KPP Block Diagram).

KEYPAD MATRIX UP TO 20x10

KDDR[19]PUCR[19]

KDDR[18]PUCR18]

KDDR[17]PUCR[17]

KDDR[0]PUCR[0]

KDDR:Data direction control registerPUCR: PULLUP enable control registerKPCR: Keypad Control RegisterKPDR: Keypad Data RegisterKPSR: Keypad Status Register

KPD

R[1

9:0]

KPC

R[1

9:0]

KD

DR

[29]

PUC

R[2

9]

KD

DR

[28]

PUC

R[2

8]

KD

DR

[20]

PUC

R[2

0]

KPDR[29:20]

DEB

OU

NC

EC

HA

IN

32khz

KPSR

TO INTERRUPTCONTROLLER

Figure26-1 KPP Block Diagram

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This subsection describes the operation of the KPP module in low-power modes.

26.2.1 Wait and Doze mode

In wait and doze modes, the KPP module continues to operate normally and may be configured to exit the low-power modes by generating an interrupt request on a key depress.

26.2.2 Stop Mode

In stop mode, there are no clocks available to perform the normal function. Only the level-detect logic is active (if configured) to allow the assigned level on the external pin or a key depress to generate an interrupt (if enabled) to exit stop mode.

26.3 KPP Peripheral Pin Direction

Thirty pins are dedicated to the KPP. Keypads of any configuration up to 20 rows and 10 columns are supported through software configuration of the peripheral pins. Any pins not used for the keypad are available as general purpose input/output. The registers are configured such that the pins can be treated as an I/O port up to 30 bits wide.

26.3.1 Input Pins

Any of the 30 pins associated with the KPP can be configured as inputs by writing a 0 to the appropriate bits in the KDDR. Additionally, each pin of the 20 bit rows and 10 bit columns can be configured to have internal pull-ups respectively by writing a 1 to the appropriate bits in PUCR (Keypad Input Pins Pull-up Control Register). After power up, the reset value of PUCR bit will be 1 as default.

26.3.2 Output Pins

Any of the 30 pins associated with the KPP can be configured as outputs by writing the appropriate bits in the KDDR to 1. Additionally, the 10 most significant bits (29-20) can be designated as open drain outputs by writing a 1 into the appropriate bits in KPCR. The lower 20 bits(19-0) are always totem-pole style drive when configured as outputs (see Table 26-1 Keypad Port Column Modes).

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Table 26-1 Keypad Port Column Modes

KDDR[29:20] KPCR[29:20] Pin Function 0 x Input 1 0 Totem-Pole Output 1 1 Open-Drain Output



26.4.1 Memory Map

Refer to Table 26-2 for a description of the KPP memory map. The KPP has a base address of 0x00dc_0000.


Address Bit s31 - 0 Access(43

0x00dc_0000

)

KPCR1 (Keypad Control Register 1) S/U

0x00dc_0004 KPCR2 (Keypad Control Register 2) S/U

0x00dc_0008 KPSR (Keypad Status Register S/U

0x00dc_000c KDDR (Keypad Data Direction Register S/U

0x00dc_0010 KPDR (Keypad Data Register S/U

0x00dc_0014 KICR1 (Keypad Input Interrupt Register 1 S/U

0x00dc_0018 KICR2 (Keypad Input Interrupt Register 2 S/U

0x00dc_001c KIMR (Keypad Input Interrupt Mask Register S/U

0x00dc_0020 KISR (Keypad Input Interrupt Status Register S/U

0x00dc_0024 PUCR Keypad Input Pin Pullup Control Register S/U



error.

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26.4.2 Registers

26.4.2.1 Keypad Control Register 1 (KPCR1)

The Keypad Control Register 1 determines which of the ten possible column strobes are to be open drain when configured as outputs and which of the twenty row sense lines are considered in generating an interrupt to the core.

Setting a column open drain enable bit (KCO9-KCO0) disables the pullup driver on that pin. Clearing the bit allows the pin to drive the high state. This bit has no effect when the pin is configured as an input.

Setting a row enable control bit in this register enables the corresponding row line to participate in interrupt generation. Likewise, clearing a bit disables that row from being used to generate an interrupt. This register is cleared by reset, disabling all rows. The row enable logic is independent of the programmed direction of the pin. Writing a 0 to the data register of pins configured as outputs will cause a keypad interrupt to be generated if the row enable associated with that bit is set. It is up to the programmer to ensure that pins being used for functions other than the keypad are properly disabled.

The KPCR1 register is byte, halfword or word addressable (see Figure 26-2 Keypad Control Register 1 (KPCR1)).

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Address : 0x00dc_0000 through 0x00dc_0003

31 30 29 28 27 26 25 24

R 0 0 KCO9 KCO8 KCO7 KCO6 KCO5 KCO4

W

RESET: 0 0 0 0 0 0 0 0

23 22 21 20 19 18 17 16

R KCO3 KCO2 KCO1 KCO0 KRE19 KRE18 KRE17 KRE16

W

RESET: 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8

R KRE15 KRE14 KRE13 KRE12 KRE11 KRE10 KRE9 KRE8

W

RESET: 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

R KRE7 KRE6 KRE5 KRE4 KRE3 KRE2 KRE1 KRE0

W

RESET: 0 0 0 0 0 0 0 0


Figure26-2 Keypad Control Register 1 (KPCR1)

KCO[9:0] — Keypad Column Strobe Open Drain Enable 1= Column strobe output is totem-pole drive (P-Channel enabled). 0= Column strobe is open drain (P-Channel disabled).

KRE[19:0] — Keypad Row Enable 1= Row is not included in keypad press detect. 0= Row is included in keypad press detect.

26.4.2.2 Keypad Control Register 2 (KPCR2)

Keypad Control Register 2 controls the keypad press interrupt, key release interrupt and keypad port input interrupt when the row or column is used for a general purpose I/O port but not for keypad detection.

397


KDIE is keypad depress interrupt enable bit. When the KPKD of KPSR (Keypad Status Register) asserted and KDIE enabled, a keypad depress interrupt will be generated.

KRIE is keypad release interrupt enable bit. When the KPKR of KPSR (Keypad Status Register) asserted and KRIE enabled, a keypad release interrupt will be generated.

KIIE is keypad port input interrupt enable bit when the port or some bits of the port are used as general purpose I/O port.

KRSS is keypad release synchronizer set bit. Write logic 1 to this bit will set the release synchronization chain (see Figure 26-12 Keypad Synchronizer Function Diagram).

KDSC is keypad depress synchronizer clear bit. Write logic 1 to this bit will clear the depress synchronization chain and if the key keep pressed and KPDR cleared, a repeated keypad depress interrupt will be generated. The KPCR2 register is byte or half-word addressable(see Figure 26-3 Keypad Control Register 2 (KPCR2)).

KSWR is keypad software reset bit. Write logic 1 to this bit will reset the module to its default state. This bit is clear automatically after the reset process. Read this bit will return logic 0.

398



31 30 29 28 27 26 25 24

R 0 0 0 0 0 0 0 0

W

RESET

0 0 0 0 0 0 0 0

23 22 21 20 19 18 17 16

R 0 0 0 0 PRESCALER[3:0]

W

RESET

0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8

R 0 0 0 0 0 KIIE KRIE KDIE

W

RESET

0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

R 0 0 0 0 KRSS KDSC

0 KSWR

W

RESET

0 0 0 0 0 0 0 0


Figure26-3 Keypad Control Register 2 (KPCR2)

KDSC — Key Depress Synchronizer Clear The Key depress synchronizer is cleared by writing a logic one into this bit. Read returns a value of 0.

KRSS — Key Release Synchronizer Set The Key release synchronizer is set by writing a logic one into this bit. Read returns a value of 0.

KDIE — Key Depress Interrupt Enable 1= No interrupt request is generated when KPKD or KPKDS is set. 0= An interrupt request is generated when KPKD or KPKDS is set.

KRIE — Key Release Interrupt Enable 1= No interrupt request is generated when KPKR is set. 0= An interrupt request is generated when KPKR is set.

399


KIIE — Keypad Port Input Interrupt Enable 1= No interrupt request is generated when KISR is set. 0= An interrupt request is generated when KISR is set.

KSWR — Keypad Software Reset bit. Write logic 1 to reset keypad to its default state

PRESCALER — Keypad prescaler Synchronizer chain clock prescaler. Here list the relationship between the value of PRESCALER and the frequency of synchronization clock (Fsyn). Fsyn = Fxtal/2(PRESCALER+1), when PRESCALER is 00 : Fsyn = Fxtal/2; 01 : Fsyn = Fxtal/4; 02 : Fsyn = Fxtal/8; 0F : Fsyn = Fxtal/65536, and the reset value of PRESCALER is 9.

NOTE: Fxtal is the frequency of crystal (XTALI).

26.4.2.3 Keypad Status Register (KPSR)

The Keypad Status Register reflects the state of the key press detect circuit.

The keypad key depress (KPKD) status bit is set when one or more enabled rows are detected low after synchronization. The KPKD status bit remains set until cleared by software. The KPKD bit may be used to generate a maskable key depress interrupt. If desired, software may clear the key press synchronizer chain to allow a repeated interrupt to be generated while a key remains pressed. In this case, a new interrupt will be generated after the synchronizer delay elapses if a key remains pressed.

The keypad key release (KPKR) status bit is set when all enabled rows are detected high after synchronization. The KPKR status bit remains set until cleared by software. The bit will typically not be set again until the detect circuit senses a key depressed followed by all keys released. The KPKR bit may be used to generate a maskable key release interrupt. The key release synchronizer may be set high by software after scanning the keypad to ensure a known state.

Due to the logic function of the release and depress synchronizer chains, it is possible to see the re-assertion of a status flag (KPKD or KPKR) if it is cleared by software prior to the system exiting the state fit represents. Software should ensure that the interrupt for a Key Release event is masked until it has entered the Key Pressed state (and vice-versa) unless this activity is desired, as might be the case when a repeated interrupt is to be generated. The synchronizer

400


chains are capable of being initialized to detect repeated key presses or releases. If they are not initialized when the corresponding event flag is cleared, false interrupt may be generated for depress (or release) events shorter than the length of the corresponding chain.

The KPSR register is byte or half-word addressable(see Figure 26-4 Keypad Status Register (KPSR)).

Address : 0x00dc_0008 through 0x00dc_000b

31 30 29 28 27 26 25 24

R 0 0 0 0 0 0 0 0

W

RESET

: 0 0 0 0 0 0 0 0

23 22 21 20 19 18 17 16

R 0 0 0 0 0 0 0 0

W

RESET

: 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8

R 0 0 0 0 0 0 0 0

W

RESET

: 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

R 0 0 0 0 0 KPKDS KPKR KPKD

W

RESET

: 0 0 0 0 0 0 0 0


Figure26-4 Keypad Status Register (KPSR)

KPKD — Keypad Key Depress KPKD is cleared by writing a logic one back into the bit.

1= No key presses detected. 0= A key has been depressed.

401


KPKR - Keypad Key Release KPKR is cleared by writing a logic one back into the bit.

1= No key release detected. 0= All keys have been released.

KPKDS - Keypad Key Depress in Stop mode KPKDS is cleared by writing a logic one back into the bit

1= No key presses detected in stop mode 0= A key has been depressed in stop mode.

26.4.2.4 Keypad Data Direction Register (KDDR)

The bits in the KDDR control the direction of the keypad port pins. The upper ten bits in the register affect the pins designated as column strobes, while the lower twenty bits affect the row sense pins. Setting any bit in this register configures the corresponding pin as an output. Clearing any bit in this register configures the corresponding pin as an input. This register is cleared by reset, configuring all pins as inputs.

The KDDR register is byte, halfword or word addressable(see Figure 26-5 Keypad Data Direction Register (KDDR)).

402


Address : 0x00dc_000c through 0x00dc_000f

31 30 29 28 27 26 25 24

R 0 0 KCDD9 KCDD8 KCDD7 KCDD6 KCDD5 KCDD4

W

RESET: 0 0 0 0 0 0 0 0

23 22 21 20 19 18 17 16

R KCDD3 KCDD2 KCDD1 KCDD0 KRDD19 KRDD18 KRDD17 KRDD16

W

RESET: 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8

R KRDD15 KRDD14 KRDD13 KRDD12 KRDD11 KRDD10 KRDD9 KRDD8

W

RESET: 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

R KRDD7 KRDD6 KRDD5 KRDD4 KRDD3 KRDD2 KRDD1 KRDD0

W

RESET: 0 0 0 0 0 0 0 0


Figure26-5 Keypad Data Direction Register (KDDR)

KCDD[9:0] — Column direction definition 1= Column n pin is configured as input (n= 0..9). 0= Column n pin is configured as output (n= 0..9).

KRDD[19:0] — Row direction definition 1= Row n pin is configured as input (n= 0..19). 0= Row n pin is configured as output (n= 0..19).

26.4.2.5 KPDR Keypad Data Register (KPDR)

This 32-bit register is used to access the column and row data. Data written to this register is stored in an internal latch, and for each pin configured as an output, the stored data is driven onto the pin. Reading of this register returns the value on the pin for those bits configured as inputs. Otherwise, the read is the value stored in the register.

403


The KPDR register is byte, halfword or word addressable.


31 30 29 28 27 26 25 24

R 0 0 KCD9 KCD8 KCD7 KCD6 KCD5 KCD4

W

RESET: 0 0 0 0 0 0 0 0

23 22 21 20 19 18 17 16

R KCD3 KCD2 KCD1 KCD0 KRD19 KRD18 KRD17 KRD16

W

RESET: 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8

R KRD15 KRD14 KRD13 KRD12 KRD11 KRD10 KRD9 KRD8

W

RESET: 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

R KRD7 KRD6 KRD5 KRD4 KRD3 KRD2 KRD1 KRD0

W

RESET: 0 0 0 0 0 0 0 0


Table 26-6 KPDR Keypad Data Register (KPDR)

KCD[9:0] — Keypad Column Data (n=0..9) Column Data bits.

KRD[19:0] — Keypad Row Data (n=0..19) Row Data bits. This register is not initialized by reset. Valid data should be written to this registers before any bits are configured as outputs.

404


26.4.2.6 Keypad Input Interrupt Configured Register 1 (KICR1)

This 32-bit register is used to control the external interrupt from 20-bit row or 10-bit column configured as input but not included in key press detect.


31 30 29 28 27 26 25 24

R ICR31 ICR30 ICR29 ICR28 ICR27 ICR26 ICR25 ICR24

W

RESET: 0 0 0 0 0 0 0 0

23 22 21 20 19 18 17 16


W

RESET: 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8


W

RESET: 0 0 0 0 0 0 0 0

6 5 4 3 2 1 0


W

RESET: 0 0 0 0 0 0 0 0


Figure26-7 Keypad Input Interrupt Configured Register 1 (KICR1)

ICR[2*m+1:2*m] (m=0..15) — Keypad Interrupt Configuration 00: Row m input interrupt is positive edge sensitive. 01: Row m input interrupt is negative edge sensitive. 10: Row m input interrupt is positive level sensitive. 11: Row m input interrupt is negative level sensitive.

405


26.4.2.7 Keypad Input Interrupt Configured Register 2 (KICR2)

This 32-bit register is used to control the external interrupt from 20-bit row or 10-bit column configured as inputs but not included in key press detect.

Address : 0x00dc_0018 through 0x00dc_001b

31 30 29 28 27 26 25 24

R 0 0 0 0 ICR59 ICR58 ICR57 ICR56

W

RESET: 0 0 0 0 0 0 0 0

23 22 21 20 19 18 17 16


W

RESET: 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8


W

RESET: 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0


W

RESET: 0 0 0 0 0 0 0 0


Figure26-8 Keypad Input Interrupt Configured Register 2 (KICR2)

ICR[32+2*m+1:32+2*m] (m=0..3) — Keypad Interrupt Configuration 00: Row m input interrupt is positive edge sensitive. 01: Row m input interrupt is negative edge sensitive. 10: Row m input interrupt is positive level sensitive. 11: Row m input interrupt is negative level sensitive.

406


ICR[40+2*n+1:40+2*n] (n=0..9) — Keypad Interrupt Configuration 00: Column n input interrupt is positive edge sensitive. 01: Column n input interrupt is negative edge sensitive. 10: Column n input interrupt is positive level sensitive. 11: Column n input interrupt is negative level sensitive.

26.4.2.8 Keypad Input Interrupt Mask Register (KIMR)

This 32-bit register make the keypad input interrupt maskable for each row and column bit.

Address : 0x00dc_001c through 0x00dc_001f

31 30 29 28 27 26 25 24

R 0 0 CIM9 CIM8 CIM7 CIM6 CIM5 CIM4

W

RESET: 0 0 0 0 0 0 0 0

23 22 21 20 19 18 17 16

R CIM3 CIM2 CIM1 CIM0 RIM19 RIM18 RIM17 RIM16

W

RESET: 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8

R RIM15 RIM14 RIM13 RIM12 RIM11 RIM10 RIM9 RIM8

W

RESET: 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

R RIM7 RIM6 RIM5 RIM4 RIM3 RIM2 RIM1 RIM0

W

RESET: 0 0 0 0 0 0 0 0


Figure26-9 Keypad Input Interrupt Mask Register (KIMR)

CIM[9:0] — Keypad Input Interrupt Column Mask 1= Column n input interrupt not masked. 0= Column n input interrupt masked.

RIM[19:0] — Keypad Input Interrupt Row Mask 1= Row n input interrupt not masked. 0= Row n input interrupt masked.

407


26.4.2.9 Keypad Input Interrupt Status Register (KISR)

This 32-bit register save the status of respective row or column input interrupt. Address : 0x00dc_0020 through 0x00dc_0023

31 30 29 28 27 26 25 24

R 0 0 CISR9 CISR8 CISR7 CISR6 CISR5 CISR4

W

RESET: 0 0 0 0 0 0 0 0

23 22 21 20 19 18 17 16

R CISR3 CISR2 CISR1 CISR0 RISR19 RISR18 RISR17 RISR16

W

RESET: 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8

R RISR15 RISR14 RISR13 RISR12 RISR11 RISR10 RISR9 RISR8

W

RESET: 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

R RISR7 RISR6 RISR5 RISR4 RISR3 RISR2 RISR1 RISR0

W

RESET: 0 0 0 0 0 0 0 0


Figure26-10 Keypad Input Interrupt Status Register (KISR)

CISR[9:0] — Keypad Input Interrupt Column Status 1= Column n input interrupt flag. Write logic 1 to the bit will clear it.. 0= No column n input interrupt.

RISR[19:0] — Keypad Input Interrupt Column Status When the respective bit is configured as level trigger input interrupt, the status bit can only be cleared when the input is deasserted. When corresponding input interrupt detected but the according bit in KIMR is disabled, the bit in KISR won’t be set.

1= Row n input interrupt flag. Write logic 1 to the bit will clear it. 0= No row n input interrupt.

408


26.4.2.10 Keypad Input Pin Pullup Control Register


31 30 29 28 27 26 25 24

R 0 0 CPUE9 CPUE8 CPUE7 CPUE6 CPUE5 CPUE4

W

RESET: 0 0 1 1 1 1 1 1

23 22 21 20 19 18 17 16

R CPUE3 CPUE2 CPUE1 CPUE0 RPUE19 RPUE18 RPUE17 RPUE16

W

RESET: 1 1 1 1 1 1 1 1

15 14 13 12 11 10 9 8

R RPUE15 RPUE14 RPUE13 RPUE12 RPUE11 RPUE10 RPUE9 RPUE8

W

RESET: 1 1 1 1 1 1 1 1

7 6 5 4 3 2 1 0

R RPUE7 RPUE6 RPUE5 RPUE4 RPUE3 RPUE2 RPUE1 RPUE0

W

RESET: 1 1 1 1 1 1 1 1


Figure26-11 Keypad Input Pin Pullup Control Register (PUCR)

CPUE[9:0] — Column Input Pin Pullup Enable Column n input pin is pullup internally. Column n input pin is not pullup internally.

RPUE[19:0] — Row Input Pin Pullup Enable

Row n input pin is pullup internally. Row n input pin is not pullup internally.

NOTE: The CPUEn and RPUEn reset value after power-up will be 1.

409


26.5 Keypad Operation

The Keypad Port is designed to simplify the software task of scanning a keypad matrix. With appropriate software support, the KPP is capable of detecting, debouncing and decoding one or two keys pressed simultaneously in the keypad.

Logic in the KPP is capable of detecting a key press even while the processor is in one of the low power standby modes. The KPP may generate a CPU interrupt any time a key press or key release is detected. This interrupt is capable of forcing the processor out of a low power mode.

Rows or columns not selected for keypad key press detect can be as general purpose I/O, and if the rows or columns are defined as inputs but not included in key press detect, the inputs can be configured as maskable interrupts and each interrupt can be defined as positive or negative edge triggered, level sensitive.

26.5.1 Keypad Matrix Construction

The Keypad Port is designed to interface to a keypad matrix which shorts the intersecting row and column lines together whenever a key is depressed. The interface is not optimized for any other switch configuration.

26.5.2 Keypad Port Configuration

Software must initialize the Keypad Port for the size of the keypad matrix. Pins connected to the keypad columns should be configured as open-drain outputs. Pins connected to the keypad rows should be configured as inputs. On-chip pullup resistors are implemented for active keypad rows.

Row inputs must also be enabled in the Keypad control register to be active in the interrupt generation circuit.

Discrete switches which are not part of the matrix may be connected to any unused row inputs. The second terminal of the discrete switch is connected to ground. The hardware will detect closures of these switches without the need for software polling.

26.5.3 Keypad Matrix Scanning

Keypad scanning is performed by a software loop which walks a zero across each of the keypad columns, reading the value on the rows at each step. The process is repeated several times in succession, with the results of each pass optionally compared with those from the previous pass. When several (3 or 4) consecutive scans yield the same key closures, a valid key press has been

410


detected. Software then can decode exactly which switch was depressed and pass the value up to the next higher software layer.

The basic debouncing period which has to be defined in the software routine (the basic period is the period between the scan of two consecutive columns, so the debounce time between two consecutive scans of the whole matrix shall be the number of columns multiplied by the basic period) may be controlled with an internal timer.

26.5.4 Keypad Standby

There is no need for the CPU to continually scan the keypad. Between key presses, the keypad can be left in a state which requires no software intervention until the next key press is detected. To place the keypad in a standby state, software should write all column outputs low. Row inputs are left enabled. At this point the CPU can attend to other tasks or revert to a low power standby mode. The Keypad Port will interrupt the CPU if any key is pressed.

Upon receiving a keypad interrupt, the CPU should set all the column strobes high, and begin a normal keypad scanning routine to determine which key was pressed. It is important that open-drain drivers should be used when scanning to prevent a possible DC path between power and ground through two or more switches.

26.5.5 Glitch Suppression on Keypad Inputs

A glitch suppression circuit qualifies the keypad inputs to prevent noise from inadvertently interrupting the CPU. The circuit is a 4 state synchronizer clocked from a 32KHz clock source. This clock must continue to run in any low power mode that the keypad is a wakeup source, as the CPU interrupt is generated from the synchronized input. An interrupt is not generated until all 4 synchronizer state have latched a valid key assertion, effectively filtering out any noise less than 125us in duration. The interrupt output is latched in an SR latch and remains asserted until cleared by software. The input of the latch is rising edge clocked(see Figure 26-12 Keypad Synchronizer Function Diagram).

411


KEYPAD MATRIX

S

R

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Set KPKR Synchronizer

Clear KPKD Synchronizer

S

R

S

R

Clear KPKR Status Flag

Clear KPKD Status Flag

KPKD

KPKR

32KHZ

KPKD

Figure26-12 Keypad Synchronizer Function Diagram

26.5.6 Multiple Key Closures

One or two keys pressed simultaneously are easily detected by the software. When three or more keys are pressed, however, it is possible that errant key closures may be detected. As can be seen, three pressed simultaneously can short between the column currently scanned by software and another column. Depending on the location of the third key pressed, a ghost press may be detected(see Figure 26-13 Decoding wrong three-key presses).

412


Column pulled down

Column not pulled down

Pulled down row

Pulled down row

The path of the zero pull down that reaches the wrong row and so generates a ghost key press

Three real key presses

Ghost key press

Figure26-13 Decoding wrong three-key presses

26.5.7 Typical Keypad Configuration and Scanning Sequence

Configure Keypad:

1. Enable number of rows in keypad (KPCR1[19:0])

2. Write 0ís to KPDR[29:20]

3. Configure keypad columns as open-drain (KPCR1[29:20])

4. Configure columns as output, rows as input (KDDR[29:0])

5. Clear the KPKD Status Flag and Synchronizer chain

6. Set the KDIE control bit, clear the KRIE control bit (avoid false release events)

(now in standby mode, awaiting a keypress)

Keypress Interrupt Detected

Begin Keypad Scanning Routine

1. Disable keypad interrupts

2. Write 1s to KPDR[29:20] setting column data to 1’s

3. Write a single column to 0, others to 1

4. Sample row inputs and save data. Multiple key presses can be detected on

413


a single column

5. Repeat steps 3-4 for remaining columns

6. Return all columns to 0 in preparation for standby mode

7. Set the KPKR synchronizer chain, clear the KPKD synchronizer chain, then clear KPKD and KPKR status bit(s) by writing to 1.

8. Re-enable the appropriate keypad interrupt(s), KDIE to detect a key hold condition, or KRIE to detect a key release event.

Note: KPKD flag should be clear when exit key depress interrupt, otherwise KPKR flag won’t be set when all depressed keys release.

414


Section 27 FIFO Controller

27.1 Introduction

The FIFO controller module is responsible for controlling FIFO interface.


The FIFO Controller continues working in low-power mode. In stop mode, the system clock is absent, and FIFO Controller module stops.

FIFO Controller clock can be stopped by setting the corresponding module stop bit in Clock Module.

415



This subsection describes the memory map (see Table 27-1 FIFO Controller Module Memory Map) and registers.

27.3.1 Memory Map

Table 27-1 FIFO Controller Module Memory Map

Address Bits 31-24 Bits 23-16 Bits 15-8 Bits 7-0 Access(

44

0x00d9_0000

)

FSZCR FPER FPCR Reserved S/U

0x00d9_0004 FPR0 S/U

0x00d9_0008 FPR1 S/U

0x00d9_000c FPR2 S/U

0x00d9_0010 FSR0 FSR1 Reserved Reserved S/U

27.3.2 Registers

This subsection contains a description of the FIFO controller module registers.

27.3.2.1 FIFO Size Control Register

The 8-bit FIFO size control register (FSZCR) determines the FIFO size.


31 30 29 28 27 26 25 24

R 0 0 0 0 0 0 FIFOSIZ[1:0]

W

RESET: 0 0 0 0 0 0 0 0


Figure27-1 FIFO Size Control Register (FSZCR)

FIFOSIZ[1:0]— The size of FIFO



error.

416


The FIFOSIZ bits define the size of the FIFO (See Table 27-2). Table 27-2 FIFO SIZE

FIFOSIZE The SIZE of FIFO

00 2K

10 2K

01 4K

11 8K

NOTE: If the system data path is USB device-->Encryption-->USB host or USB host-->Encryption-->USB device, the FIFOSIZ[0] should be clear.

417


27.3.2.2 FIFO Pointer Enable Register

There are different pointers for DMA, USB (host/device) and encryption devices (See FPR0, FPR1, FPR2) to show the relative owner’s running state. FIFO Pointer Enable Register can enable/disable the increment of different pointer.


23 22 21 20 19 18 17 16

R 0 0 0 DPTREN

0 EPTREN HUPTREN DUPTREN

W

RESET: 0 0 0 0 0 0 0 0


Figure27-2 FIFO Pointer Enable Register (FPER)

DPTREN — DMAC Pointer Increment Enable Register 1= The increment of DMAC pointer will be enabled. 0= The increment of DMAC pointer will be disabled.

EPTREN — Encryption Pointer Increment Enable Register 1= The increment of Encryption pointer will be enabled. 0= The increment of Encryption pointer will be disabled.

HUPTREN — USB Host Pointer Increment Enable Register 1= The increment of USB host pointer will be enabled. 0= The increment of USB host pointer will be disabled.

DUPTREN — USB Device Pointer Increment Enable Register 1= The increment of USB device pointer will be enabled. 0= The increment of USB device pointer will be disabled.

418


27.3.2.3 FIFO Pointer Clear Register

The FIFO Point Clear Register is used to clear different pointers that belong to DMAC, BCH, Encryption devices and USB (host/device).


15 14 13 12 11 10 9 8

R 0 0 0 0 0 0 0 0

W DCLR BCLR ECLR HUCLR DUCLR

RESET: 0 0 0 0 0 0 0 0


Figure27-3 FIFO Point Clear Register (FPCR)

DCLR — DMAC Pointer Clear Register Set DCLR to "1" will clear DMAC pointer register.

BCLR — BCH Pointer Clear Register Set BCLR to "1" will clear BCH pointer register.

ECLR — Encryption Pointer Clear Register Set ECLR to "1" will clear DMAC pointer register.

HUCLR — USB Host Pointer Clear Register Set HUCLR to "1" will clear USB host pointer register.

DUCLR — USB Device Pointer Clear Register Set DUCLR to "1" will clear USB device pointer register.

419


27.3.2.4 FIFO Point Register


31 30 29 28 27 26 25 24

R 0 0 0 0 0 0 DUPTR[9:8]

W

RESET: 0 0 0 0 0 0 0 0

23 22 21 20 19 18 17 16

R DUPTR[7:0]

W

RESET: 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8

R 0 0 0 0 0 0 HUPTR[9:8]

W

RESET: 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

R HUPTR[7:0]

W

RESET: 0 0 0 0 0 0 0 0


Figure27-4 FIFO Point Register 0 (FPR0)

420


Address : 0x00d9_0008 through 0x00d9_000b

31 30 29 28 27 26 25 24

R 0 0 0 0 0 0 EPTR[9:8]

W

RESET: 0 0 0 0 0 0 0 0

23 22 21 20 19 18 17 16

R EPTR[7:0]

W

RESET: 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8

R 0 0 0 0 0 0 BPTR[9:8]

W

RESET: 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

R BPTR[7:0]

W

RESET: 0 0 0 0 0 0 0 0



421


Address : 0x00d9_000c through 0x00d9_000f

31 30 29 28 27 26 25 24

R 0 0 0 0 0 0 PN[9:8]

W

RESET: 0 0 0 0 0 0 0 0

23 22 21 20 19 18 17 16

R PN[7:0]

W

RESET: 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8

R 0 0 0 0 0 0 DPTR[9:8]

W

RESET: 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

R DPTR[7:0]

W

RESET: 0 0 0 0 0 0 0 0



DPTR — DMAC Pointer Register The DMAC pointer will increase after the completion of a transfer by DMA.

EPTR — Encryption Pointer Register The Encryption pointer will increase after the encryption or decryption process by Encryption Wrapper Moduel.

HUPTR — USB Host Pointer Register The USB host pointer will increase after the completion of receiving or transmitting a package through the USB Host port.

DUPTR — USB Device Pointer Register The USB Device pointer will increase after the completion of receiving or transmitting a package through the USB Device port.

422


BPTR — BCH Pointer Register This register is a read-only register, please see Section 21 BCH for detail.

PN — Procedure Number Register PN register stores the procedure number during transaction.

27.3.2.5 FIFO Status Register

FIFO Status Register (FSR) reflects the state of the FIFO (FULL or EMPTY for application). Writting to this register has no effect and will be terminated normally.


31 30 29 28 27 26 25 24

R EEHU HUEDU HUCDU EEDU DUCD DEDU DEE DUEB

W

RESET: 1 1 0 1 0 1 1 1


Figure27-7 FIFO Status Register 0 (FSR0)

EEHU — Encryption Pointer Equals to USB Host Pointer 1= Encryption pointer equals to USB host pointer 0= Encryption pointer does not equal to USB host pointer

HUEDU — USB Host Pointer Equals to USB Device Pointer 1= USB host pointer equals to USB device pointer 0= USB host pointer does not equal to USB device pointer

HUCDU — USB-Host/Device Pointer Catches Up USB-Device/Host Pointer 1= USB host pointer catches up USB device pointer or USB device

pointer catches up USB host pointer 0= USB host pointer does not catch up USB device pointer or USB

device pointer does not catches up USB host pointer

EEDU — Encryption Pointer Equals to USB Device Pointer 1= Encryption pointer equals to USB device pointer 0= Encryption pointer does not equal to USB device pointer

DUCD — USB-Device/DMA Pointer Catches Up DMAC/USB-Device Pointer 1= USB device pointer catches up DMAC pointer or DMA pointer catches

up USB device pointer. 0= USB device pointer does not catch up DMAC pointer or DMA pointer

does not catches up USB device pointer.

423


DEDU — DMAC Pointer Equals to USB Device Pointer 1= DMAC pointer equals to USB device pointer 0= DMAC pointer does not equal to USB device pointer

DEE — DMAC Pointer Equals to Encryption Pointer 1= DMAC pointer equals to encryption pointer 0= DMAC pointer does not equal to encryption pointer

DUEB — USB Device Pointer Equals to BCH Pointer 1= USB device pointer equals to BCH pointer 0= USB device pointer does not equal to BCH pointer


23 22 21 20 19 18 17 16

R 0 0 0 EEB DEP DUEP HUEP DMABUSY

W

RESET: 0 0 0 1 1 1 1 0


Figure27-8 FIFO Status Register 1 (FSR1)

EEB — Encryption Pointer Equals to BCH Pointer 1= Encryption pointer equals to BCH pointer 0= Encryption pointer does not equal to BCH pointer

DEP — DPTR Equals to PN 1= DPTR equals to PN 0= DPTR and PN are not equal

DUEP — DUPTR Equals to PN 1= DUPTR equals to PN 0= DUPTR and PN are not equal

HUEP — HUPTR Equals to PN 1= HUPTR equals to PN 0= HUPTR and PN are not equal

DMABUSY — DMA Busy 1= DMAC is busy 0= DMAC is not busy

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27.4.1 FIFO Controller Purpose

In some scenarios, the packets from outside will be stored in the system buffer first, then be encrypted/decrypted, and transmitted outside at last. In the situation above mentioned, the software can deal with the system buffer as a set of FIFOs, and the FIFO Controller will control the state of FIFOs.

27.4.2 FIFO Operation

When the data path is USB device --> Encryption --> USB host (WRITE), the operation is as flowing:

1. If the USB device pointer does not catch up the USB host pointer (HUCDU), the buffer is available for USB device to store a packet (DUAW).

2. If the encryption pointer does not equal to the USB device pointer (EEDU), the buffer is available for encryption wrapper to encrypt a packet (EAW).

3. If the encryption pointer does not equal to the USB host pointer (EEHU), the buffer is available for USB host to read a packet (HUAW).

When the data path is USB host --> Decryption --> USB device (READ), the operation is as flowing:

1. If the USB host pointer does not catch up the USB device pointer (HUCDU), the buffer is available for USB host to reading a packet (HUAR).

2. If the encryption pointer does not equal to the USB host pointer (EEHU), the buffer is available for encryption wrapper to decrypt a packet (EAR).

3. If the encryption pointer does not equal to the USB device pointer (EEDU), the buffer is available for USB device to read a packet (DUAR).

When the data path is USB device --> Encryption --> DMAC-->NANFLASH (WRITE), the operation is as flowing:

1. If the USB device pointer does not catch up the DMAC pointer (DUCD), the buffer is available for USB device to writing a packet (DUAW).

2. If the encryption pointer does equal to the USB device pointer (EEDU), the buffer is available for encryption wrapper to encrypt a packet (EAW).

3. If the encryption does not equal to the DMAC pointer (EEDU), the buffer is available for DMAC to transfer a packet (DAW) to NANDFLASH.

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When the data path is NANDFLASH-->DMAC--> BCH-->Decryption -->USB device (READ), the operation is as flowing:

1. If the DMAC pointer does not catch up the USB device pointer (DUCD), the buffer is available for DMAC to read a packet (DAR).

2. If the encryption pointer does not equal to the BCH pointer (EEB), the buffer is available for encryption wrapper to decrypt a packet (EAR).

3. If the encryption pointer does not equal to the USB device pointer (DUEE), the buffer is available for USB device to read a packet (DUAR).

When the data path is USB device --> DMAC-->NANFLASH (WRITE), the operation is as flowing:

1. If the USB device pointer does not catch up the DMAC pointer (DUCD), the buffer is available for USB device to write a packet (DUAW).

2. If the USB device does not equal to the DMAC pointer (DEDU), the buffer is available for DMAC to send a packet (DAW) to NANDFLASH.

When the data path is NANDFLASH-->DMAC--> BCH--> USB device (READ), the operation is as flowing:

1. If the DMAC pointer does not catch up the USB device pointer (DUCD), the buffer is available for DMAC to read a packet (DAR) from NANDFLASH.

2. If the BCH pointer does not equal to the USB device pointer (DUEB), the buffer is available for USB device to read a packet (DUAR).

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Section 28 SMS4

28.1 Introduction

The SMS4 module is the cryptographic module that achieves the block cipher SMS4 encryption algorithm.

28.2 Features

Support SMS4 module encryption/decryption algorithm

128bits data unit for encryption and decryption

Support Electronic Code Book (ECB) mode

Support SMS4 module algorithm with 128 bits key

Data process speed up to 40MBps@80MHz


The SMS4 controller is not affected by any low-power modes. CPU can stop SMS4 by setting the corresponding module stop bit in Clock Module.

427


28.4 Block Diagram

Figure28-1 SMS4 Block Diagram

428



Table 28-1 shows the SMS4 register memory map.



0x00de_0000

SMSDIN0R S

0x00de_0004 SMSDIN1R S

0x00de_0008 SMSDIN2R S

0x00de_000c SMSDIN3R S

0x00de_0010 SMSKEY0R S



0x00de_001c SMSKEY3R S

0x00de_0020 SMSDOUT0R S



0x00de_002c SMSDOUT3R S

0x00de_0030 Reversed SMSCSR S




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This subsection provides a description of the SMS4 module registers.

28.6.1 SMSDIN0R

Address :0x00de_0000 to0x00de_0003

Bit31 Bit0

Read: SMSDIN0R

Write:

RESET: 0 0 0 0


Figure28-8 Input Data Register0

SMSDIN0R[31:0] — Input Data Register0 A 32-bit input data register for SMS4. Reset clears SMSDIN0R.

28.6.2 SMSDIN1R


Bit31 . . . Bit0

Read: SMSDIN1R

Write:

RESET: 0 0 . . . 0 0




430


28.6.3 SMSDIN2R

Address :0x00de_0008 to0x00de_000b

Bit31 . . . Bit0

Read: SMSDIN2R

Write:

RESET: 0 0 . . . 0 0




28.6.4 SMSDIN3R

Address :0x00de_000c to0x00de_000f

Bit31 . . . Bit0

Read: SMSDIN3R

Write:

RESET: 0 0 . . . 0 0




431


28.6.5 SMSKIN0R


Bit31 . . . Bit0

Read: SMSKIN0R

Write:

RESET: 0 0 . . . 0 0


Figure28-8 Input Key Register0

SMSKIN0R[31:0] — Input Key Register0 A 32-bit input key register for SMS4. Reset clears SMSKIN0R.

28.6.6 SMSKIN1R


Bit31 . . . Bit0

Read: SMSKIN1R

Write:

RESET: 0 0 . . . 0 0




432


28.6.7 SMSKIN2R


Bit31 . . . Bit0

Read: SMSKIN2R

Write:

RESET: 0 0 . . . 0 0




28.6.8 SMSKIN3R


Bit31 . . . Bit0

Read: SMSKIN3R

Write:

RESET: 0 0 . . . 0 0




433


28.6.9 SMSDOUT0R


Bit31 . . . Bit0

Read: SMSDOUT0R

Write:

RESET: 0 0 . . . 0 0


Figure28-10 Output Data Register0

SMSDOUT0R[31:0] — Output Data Register0 A 32-bit output data register for SMS4. Reset clears SMSDOUT0R.

28.6.10 SMSDOUT1R


Bit31 . . . Bit0

Read: SMSDOUT1R

Write:

RESET: 0 0 . . . 0 0




434


28.6.11 SMSDOUT2R


Bit31 . . . Bit0

Read: SMSDOUT2R

Write:

RESET: 0 0 . . . 0 0




28.6.12 SMSDOUT3R


Bit31 . . . Bit0

Read: SMSDOUT3R

Write:

RESET: 0 0 . . . 0 0




435


28.6.13 SMSCSR

Address :0x00de_0033

Bit7 6 5 4 3 2 1 Bit0

Read: BUSY CMODE

Write:

RESET: 0 0 0 0 0 0 0 0


Figure28-14 Control Status Register

BUSY — SMS4 Module Busy Flag SMS4 module sets the busy flag when encryption/decryption operation is processing. Reset Clears BUSY

1= SMS4 module encryption/decryption is doing. 0= SMS4 module encryption/decryption is not doing.

CMODE — SMS4 Module Finish Running The CMODE bit selects encryption or decryption operation. Reset Clears CMODE.

1= Decrypt mode 0= Encrypt mode

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SMS4 module supports SMS4 ECB Mode operation. Soft reset will clear the operation.

The process for the operation is described as following:

1. Set CMODE bit in SMSCSR to set the operation mode.

2. Write 128-bit Key to SMSKINxR (x=0, 1, 2, 3).

3. Write 128-bit Data to SMSDINxR (x=0, 1, 2, 3), then SMS4 module starts to run , when BUSY bit in SMSCSR is "0", SMS4 module finish the encryption process.

4. Read SMSDOUTxR (x=0, 1, 2, 3) for 128-bit Result.

437


Section 29 Mini BCH ECC Controller

29.1 Introduction

The Mini BCH ECC Controller provides an Error Correction Capability (ECC) for protecting 36 bits of data against up to 5 bits of errors. The Mini BCH ECC Controller employs a 63 bit Hocquenghem-Bose-Chaudhury (BCH) code, wherein 36 bits are data, and 27 bits are ECC code (the remaining 64th bit is redundant).

The Mini BCH ECC Controller contains only one set of register shared by encoding and decoding, which is done in hardware. If the encoding or decoding sequence has not finished before subsequent accesses are requested, the bus is wait-stated. If the decoded data is too corrupted and cannot be fixed, an interrupt may be generated.

29.2 Features

The Mini BCH ECC Controller features include:

Hocquenghem-Bose-Chaudhury (BCH) Algorithm

Hardware ’on the fly’ Encoding/Decoding

Transparent, high-speed pipe-line operation

Simple write-read-back functionality

Can correct up to 5 single bit errors in 63 bit of code (data plus ECC)

Can detect47

6 or more single bit errors in 63 bit of code (data plus ECC)

47The ECC is guaranteed to detect and correct 5 bit errors. Codes with 6 or more errors can usually

also be detected (not corrected) but this is not 100% guaranteed, due to inherent limitations of the

BCH algorithm. If code is expected to be extremely corrupted (i.e. more than 5 bit errors) then the

code should be decoded twice (using the FCE bit, see Section 29.5.3) to increase the chance of

detecting the corruption.

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The Mini BCH ECC Controller design includes high degree of local clock gating, so that its power consumption is minimal both during normal operation and idle state.

Whether the Mini BCH ECC Controller operates in wait, doze and stop modes depends on how the clocks are configured in the Clock Module in the chip.

Typically, blocks like the Mini BCH ECC Controller continue to work in wait and doze mode, while in stop mode, the system clock is gated-off and operation halts. The CPU can disable the Mini BCH ECC Controller by setting the corresponding stop bit in the Clock Module.

29.4 Block Diagram

A Block Diagram of the Mini BCH ECC Controller is shown in Table 29-1. Actually, the encode register and decode register share the same register, whether it works as encode or decode register only based on SDIR in ECR register. The module is accessed via the IP Bus, supporting byte, halfword and word tranfers.

Figure 29-1 Mini BCH Controller Block Diagram

The Mini BCH ECC Controller is intended to be used as follows:

1. When SDIR is 0, data that needs to be encoded is written to the (first part of the) Encode/Decode Register by the CPU. Writing data causes the ’On The Fly’ Encoder to activate. After five bytes are written (additional bytes are ignored), the ECC code is stored in the second part of the Encode/Decode Register.

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2. At some later time, the whole Encode/Decode Register is read (e.g. via DMA) and the data is stored elsewhere (e.g. in a Flash memory).

3. When SDIR is 1, data that needs to be decoded is written to the Encode/Decode Register (e.g. via DMA). Writing bytes causes the ’On The Fly’ Decoder to activate. If there are errors detected in the decoded data, the Equation Solver and Error Finder automatically find and fix the data in the Encode/Decode Register. If there were too many errors (more than 5 bits were corrupted) then an interrupt may be asserted to let the CPU know.

4. The CPU can read the (fixed) data from the Encode/Decode Register after decode has finished.


Table 29-1 shows the Mini BCH Controller memory map.

Table 29-1 Mini BCH Register Memory Map

Address Bits 31-24 Bits 23-16 Bits 15-8 Bits 7-0 Access48,49,50

0x00db_0000

D00,D01 D02,D03 D04,D05 D06,D07 S

0x00db_0004 D08,C09 C10,C11 C12,C13 C14,C15 S

0x00db_0008 ECR ESR ERRCR Reserved51 S

0x00db_000c Reserved S




50 The Supervisor-only access and User-access-error features are only enabled if the

ips_supervisor_access pin is connected on the Mini BCH ECC controller module. If these features

(S-only access, U-error) are not needed, the ips_supervisor_access pin should be tied high,

allowing both User and Supervisor access to the Mini BCH ECC controller.

51Reserved locations should not be accessed. Writing has no effect, and reading returns 0.

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29.5.1 Encode/Decode Data Symbol Registers (D00-D08)

The Encode/Decode Data Symbol Registers (D00-D08) are shown in Figure 29-2 to Figure 29-6 below. The contents of the nine 4-bit52

Address : 0x00

Data Symbol Registers D00 to D08 will be protected via the ECC code.

7 6 5 4 3 2 1 0

R D00[3:0] D01[3:0]

W

RESET: 0 0 0 0 0 0 0 0

Figure 29-2 Encode/Decode Data Symbol Register D00/D01

Address : 0x01

7 6 5 4 3 2 1 0

R D02[3:0] D03[3:0]

W

RESET: 0 0 0 0 0 0 0 0


Address : 0x02

7 6 5 4 3 2 1 0

R D04[3:0] D05[3:0]

W

RESET: 0 0 0 0 0 0 0 0


Address : 0x03

7 6 5 4 3 2 1 0

R D06[3:0] D07[3:0]

W

RESET: 0 0 0 0 0 0 0 0


52The protected data string is 4.5 bytes (36 bits) long, and the Data Symbol Registers may be

accessed via byte, Halfword or Word size access, however, the Mini BCH ECC controller itself is

organized to process data in 4-bit units (this is transparent to the user/software).

441


Address : 0x04

7 6 5 4 3 2 1 0

R D08[3:0]

C09[3:0]

W

RESET: 0 0 0 0 0 0 0 0

Figure 29-6 Encode/Decode Data Symbol Register D08

NOTE: The Encode/Decode Data Symbol Register D08 is shared with the ECC Symbol Register C09 at address 0x04.

29.5.2 Encode/Decode ECC Symbol Registers (C09-C15)

The Encode/Decode ECC Symbol Registers (C09-C15) are shown in Figure 29-8 to Figure 29-10 below.

These registers contain the ECC code symbols that protect the data in the Data Symbol Registers (see Section 29.5.1).

The contents of the ECC code symbol registers is only valid after five (4.5) bytes have been written to the Encode/Decode Data Symbol Registers (D00-D08) when SDIR is 0.

NOTE: Hardware does not prevent reading the ECC code symbol registers while their contents is not valid.

Address : 0x04

7 6 5 4 3 2 1 0

R D08[3:0]

C09[3:0]

W

RESET: 0 0 0 0 0 0 0 0

Figure 29-7 Encode/Decode ECC Symbol Register C09

NOTE: The Encode/Decode ECC Symbol Register C09 is shared with the Data Symbol Register D08 at address 0x04.

442


Address : 0x05

7 6 5 4 3 2 1 0

R C10[3:0] C11[3:0]

W

RESET: 0 0 0 0 0 0 0 0


Figure 29-8 Encode/Decode ECC Symbol Register C10/C11

Address : 0x06

7 6 5 4 3 2 1 0

R C12[3:0] C13[3:0]

W

RESET: 0 0 0 0 0 0 0 0



Address : 0x07

7 6 5 4 3 2 1 0

R C14[3:0] C15[3:1] Reserved

W

RESET: 0 0 0 0 0 0 0 0



NOTE: bytes written to Encode/Decode register must in the right order, otherwise, it will result in unexpected result for encoding/decoding.

29.5.3 ECC Control Register (ECR)

The ECC Control Register (ECR) is shown in Figure 29-11. Most of the function of the Mini BCH ECC Controller is transparent (i.e. just store data bytes, copy to flash, copy back from flash, read data bytes), but some

443


functions of the Controller may be changed to accommodate different software implementations.

Address : 0x08

7 6 5 4 3 2 1 0

R Reserved Reserved SDIR

Reserved TMEIE

Reserved

W RST FCE

RESET: 0 0 0 0 0 0 0 0


Figure 29-11 ECC Control Register (ECR)

RST — Reset When written with one (1), this bit forces a synchronous reset of the Mini BCH ECC Controller, setting the internal state-machines and status flags back to their default values.

1= Reset the Controller 0= No effect

The RST bit is not required when the Controller is used as intended.

FCE — Force Encode/Decode When written with one (1), this bit forces an encode or decode sequence to be started with the data that is already contained in the Encode/Decode Registers based on SDIR bit.

1= Force an encode/decode sequence 0= No effect

When SDIR is 0, if the data previously written to the Encode/Decode Registers is almost the same as the next data, rather than writing all five bytes again, only the changed byte(s) could be written and then an encode sequence could be forced using the FCE. When SDIR is 1, The FCE bit should normally not be needed, but if the Mini BCH ECC Controller is intended to be used with (Flash) memory that contains more errors than expected (i.e. more than five error bits), then the

444


FCE bit could be used to increase the probability of detecting53

29.5.4 ECC Status Register (ESR)

a Too Many Errors (TME) condition.

SDIR — Shared Direction This bit determines the mode of the Controller (Encode or Decode).

1= Data written to 0x00 to 0x07 is decoded 0= Data written to 0x00 to 0x04 is encoded

TMEIE — Too Many Errors Interrupt Enable This bit allows an interrupt to be generated when too many errors (i.e. more than five bits) were detected in the decoded data.

1= TMEI Interrupt enabled 0= TMEI Interrupt disabled

Note that the RST bit overrides the FCE bit, i.e. writing one (1) to both of these two bits at the same time will cause the most significant bit’s function to activate.

The other bits in the ECR take effect in the next clock cycle (after writing), so it isn’t allowed to change SDIR at the same time as forcing FCE.

SDIR isn’t supposed to be changed while busy encoding or decoding, otherwise, it will result in unexpected result.

The ECC Status Register (ESR) is shown in Figure 29-12.

Address : 0x09

7 6 5 4 3 2 1 0

R DBUSY Reserved TME EBUSY DOK AB1 AB0 EOK

W

RESET: 0 0 0 0 0 0 0 0

53The Mini BCH ECC controller is designed to detect and correct up to five bit errors in decode data

plus ECC. If more than five errors are introduced, it is not guaranteed that this is always detected.

It is possible that the errors change one valid BCH code into another valid BCH code. In that case,

the most likely scenario is that the Mini BCH ECC controller will decode the data and ECC string

and ’fix’ some errors. However, if the ’fixed’ data plus ECC is decoded once more, there are even

more errors in the code (previous errors plus changes introduced by ’fixing’ the code during the

first decoding). If the first decode didn’t detect the Too Many Errors (TME) condition, the second

(or a subsequent) decode may detect the TME condition. Note that in any case, TME means that

the data is too corrupted to allow it to be fixed and must be considered lost. If the FCE bit is used

with a code that contains five or less errors, the errors would have been fixed, and a subsequent

decode would result in a normal ’Decode OK’ (DOK) condition.

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Figure 29-12 ECC Status Register (ESR)

DBUSY — Busy Decoding This bit is set when the Mini BCH ECC Controller has started a decode sequence, either by writing to the FCE bit (see Section 29.5.3) or by writing to the first byte of the Encode/Decode Register when SDIR is 1. This bit is cleared when the Mini BCH ECC Controller is reset via the RST bit (see Section 29.5.3) or when a new encode sequence is started (by writing to the first byte of the Encode/Decode Register when SDIR is 0) or when the decode sequence has finished (in either TME or DOK states).

1= The Mini BCH ECC Controller is busy decoding 0= The Mini BCH ECC Controller is not busy decoding

TME — Too Many Errors (Decode Failed) This bit is set when after decoding, more errors were detected than the Mini BCH ECC Controller can handle, i.e. more than five bits were changed. In this case, the data cannot be recovered. This bit is cleared when the Mini BCH ECC Controller is reset via the RST bit (see Section 29.5.3) or when a new encode or decode sequence is started (by writing the first byte of the Encode/Decode Registers). An interrupt may be generated if the TMEIE bit is set (see Section 29.5.3). The interrupt can be negated by clearing the TMEIE bit or by clearing the TME bit (e.g. via RST).

1= Too Many Errors 0= No errors

EBUSY — Busy Encoding This bit is set when the Mini BCH ECC Controller has started an encode sequence, either by writing to the FCE bit (see Section 29.5.3) or by writing to the first byte of the Encode/Decode Register when SDIR is 0. This bit is cleared when the Mini BCH ECC Controller is reset via the RST bit (see Section 29.5.3) or when a new decode sequence is started (by writing to the first byte of the Encode/Decode Register when SDIR is 1) or when the encode sequence has finished (in EOK states).

1= The Mini BCH ECC Controller is busy encoding 0= The Mini BCH ECC Controller is not busy encoding

DOK — Decode OK This bit is set when after decoding when no errors were detected, or when there were errors that have all been fixed. This bit is cleared when the Mini BCH ECC Controller is reset via the RST bit (see Section 29.5.3) or when a new encode or decode sequence is started (by writing the first byte of the Encode/Decode Registers).

1= Decode completed without errors 0= Idle, Busy or other state

446


AB1 — All bytes One (0xFF) This bit sets if all bytes54

This bit sets if all bytes1 read from Flash were 0x00, indicating an empty page. This bit is cleared when the Mini BCH ECC Controller is reset via the RST bit (see Section 29.5.3) or when a new encode or decode sequence is started (by writing the first byte of the Encode/Decode Registers).

1= All bytes read from Flash were 0x00 0= Not all bytes read from Flash were 0x00

EOK — Encode OK

decoded were 0xFF, indicating an empty page. This bit is cleared when the Mini BCH ECC Controller is reset via the RST bit (see Section 29.5.3) or when a new encode or decode sequence is started (by writing the first byte of the Encode/Decode Registers).

1= All bytes read from Flash were 0xFF 0= Not all bytes read from Flash were 0xFF

AB0 — All bytes Zero (0x00)

This bit is set when 5 bytes of data have been encoded and the ECC code bytes/symbols can be read from the C09-C15 registers (see Section 29.5.2). This bit is cleared when the Mini BCH ECC Controller is reset via the RST bit (see Section 29.5.3) or when a new encode or decode sequence is started (by writing the first byte of the Encode/Decode Registers).

1= Encode completed (C09-C15 registers contain valid ECC code bytes) 0= Mini BCH ECC Controller Busy, Idle, or other state

29.5.5 ECC Error Count Register (ERRCR)

The ECC Error Count Register (ERRCR) is shown in Figure 29-13. It counts the error number found in decoding.

Address : 0x0a

7 6 5 4 3 2 1 0

R Reserved ERRCR

W

RESET: 0 0 0 0 0 0 0 0


Figure 29-13 ECC Error Count Register (ERRCR)

54The last bit at address 0x07 is reserved and this bit is ignored when determining the AB1/AB0

conditions.

447


ERRCR — Error Count Number This bit indicates the error number found in decoding, it’s only valid after decode has finished. This bit is cleared when the Mini BCH ECC Controller is reset via the RST bit (see Section 29.5.3) or when a new encode or decode sequence is started (by writing the first byte of the Encode/Decode Registers).

448


Section 30 USB2.0 OTG Controller Modules

(USBCO1/2)

30.1 Introduction

The USBC (USB 2.0 Controller) controls the USB transfer. It operates as a USB peripheral or as the host/peripheral in point-to-point communications with another USB function (which can be either high-speed, full-speed or low-speed).

30.2 Features

The USBC performs these operations.

USBC1 supports six endpoints

USBC2 supports three endpoints

Encodes, decodes, checks and directs all USB packets sent and received.

- IN transactions are handled through its Tx FIFO,

- OUT transactions are handled through its Rx FIFO.

Soft connect/disconnect option

Support suspend and resume signaling.

449



This subsection provides a description of the memory map and registers.

30.3.1 Memory Map

There are two USBCs in TF32A09 Chip, and each has its base address, USBC1 is of 0x00e0_0000, USBC2 is of 0x00e1_0000.

Table 30-1 USBC Memory Map USBC REGISTER MAP: Common USB register

Offset Name Description Access(1)

0x00 FADDRR Function address register S

0x01 UCSR USB control and status register S

0x02~0x03 IntrTx Interrupt register for Endpoint0 plus Tx Endpoint1 to 5 S

0x04~0x05 IntrRx Interrupt register for Rx Endpoint S

0x06~0x07 IntrTxE Interrupt enable register for IntrTx S

0x08~0x09 IntrRxE Interrupt enable register for IntrRx S

0x0a IntrUSB Interrupt register for common USB interrupts S

0x0b IntrUSBE Interrupt enable register for IntrUSB S

0x0c~0x0d FNUMR Frame number S

0x0e Eindex Index register for selecting the endpoint status and control register

S

0x0f Testmode Enables the USB 2.0 test modes. S

0x10~0x11 TXPSZR Maximum packet size for peripheral Tx endpoint. S

0x12~0x13 E0CSR Control status register for Endpoint0. S

TxCSR Control Status register for peripheral Tx endpoint S

0x14~0x15 RXPSZR Maximum packet size for peripheral Rx endpoint S

0x16~0x17 RxCSR Control Status register for peripheral Rx endpoint S

0x18~0x19 E0COUNTR Number of received bytes in Endpoint0 FIFO S

RxCount Number of bytes in peripheral Rx endpoint FIFO S

0x1a TxType Transaction protocol and peripheral endpoint number for the host Tx endpoint.

S

0x1b NAKLimit0 Sets the NAK response timeout on Endpoint 0. S

450


TxInterval

Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Tx endpoint.(Index register does not set select Endpoint 0)

S

0x1c RxType Transaction protocol and peripheral endpoint number for the host Rx endpoint.

S

0x1d RxInterval Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Rx endpoint.

S

0x1e Reserved Unused, always returns 0. S

0x1f Reserved Unused, always returns 0. S

0x20~0x34 FIFOx FIFO Entry for endpoint0, 1, 2, 3, 4, 5 S

0x40 EP1_TX_LEN Endpoint 1 Transfer Length (Only valid for half-word access)

S

0x44 EP2_TX_LEN

Endpoint 2 Transfer Length (Only valid for half-word access)

S

0x48 EP3_TX_LEN


S

0x4c EP4_TX_LEN


S

0x50 EP5_TX_LEN


S

0x54 Reserved Unused, always returns 0. S


0x58 EP0_LEN Endpoint 0 Length (Only valid for byte access) S

0x60 OTGCtrl OTG device control register S


0x62 TxFIFOsz Tx Endpoint FIFO size S

0x63 RxFIFOsz Rx Endpoint FIFO size S

0x64~0x65 TxFIFOadd Tx Endpoint FIFO address S

0x66~0x67 RxFIFOadd Rx Endpoint FIFO address S

NOTES:

1. S = CPU supervisor mode access only. S/U = CPU supervisor or user mode access. User mode


error.

451


30.3.2 COMMON REGISTERS

30.3.2.1 FADDRR (Function Address Register)

Address : USBC1:0x00e0_0000; USBC2:0x00e1_0000

7 6 5 4 3 2 1 0

FADDR[7:0]

From CPU rw rw rw rw rw rw rw rw

From USB r r r r r r r r

RESET 0 0 0 0 0 0 0 0


Figure 30-1 Function Address Register

FADDR[7:0] — Function Address When the USBCx is being used in peripheral mode, this register should be written with the address received through a SET_ADDRESS command, which will then be used for decoding the function address in sub sequent token packet. When the USBCx is being used in peripheral mode, this register should be set to the value sent in a SET_ADDRESS command during device enumeration as the address for the peripheral device.

30.3.2.2 USB Control and Status Register (UCSR Register)


7 6 5 4 3 2 1 0

0 Soft Conn HS Enab Speed

Mode

Reset

Status Resume

SuspendM

ode

Enable

SuspendM

From CPU r rw rw r r rw r rw

From USB r r r rw rw r rw r

RESET 0 0 1 0 0 0 0 0


Figure 30-2 USB Control and Status Register

452


Soft Conn — Soft Connect/Disconnect If Soft Connect/Disconnect feature is enabled, then the USB D+/D- lines are enabled when this bit is set by the CPU and tri-stated when this bit is cleared by the CPU.

1= USB D+/D- lines are enables. 0= USB D+/D- lines are tri-stated.

NOTE: Only valid in peripheral mode.

HS Enab — High-Speed Enable 1= USBC will negotiate High-speed mode when the device is reset by the

host 0= USBC only operate in Full-speed mode

Speed Mode — Speed Mode Status This read-only bit indicates whether the high-speed mode has been successfully negotiated during USB reset, and become valid when USB reset completes (as indicated by USB reset interrupt).

1= work in high-speed mode 0= not work in high-speed mode

Reset Status This bit is set when Reset signaling is present on the bus.

1= received Reset signaling 0= no Reset signal

NOTE: This bit is Read/Write from CPU in host mode, but Read-Only in peripheral mode.

Resume This bit is set by the CPU to generate Resume signaling when the device is in Suspend mode.

1= set by the CPU to generate Resume signaling when the device is in Suspend mode. The CPU should clear this bit after 10ms (a maximum of 15ms) to end Resume signaling.

0= normal

Suspend Mode This bit is set when the device enters into Suspend mode. It is cleared if the CPU reads the interrupt register, or sets the Resume bit above.

1= USBC in suspend mode 0= USBC not in suspend mode

453


Enable SuspendM This bit is set by the CPU to enable the SUSPENDM signal.

1= The SUSPENDM output is enabled 0= The SUSPENDM output is disabled

30.3.2.3 INTRTX

IntrTx is a 16-bit read-only register that indicates which interrupts are currently active for Endpoint0 and the Tx Endpoints. All Active interrupts are cleared when this register is read.

Address : USBC1:0x00e0_0002 and 0x00e0_0003; USBC2:0x00e1_0002 and 0x00e1_0003

15 14 13 12 11 10 9 8

0 0 EPT5 EPT4 EPT3 EPT2 EPT1 EPT0

From CPU r r r r r r r r

From USB - - set set set set set set

RESET 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0


From USB - - - - - - - -

RESET 0 0 0 0 0 0 0 0


exception.

Figure 30-3 Interrupts of Tx Endpoints Register

EPTx (x is not 0) — Endpoint x transmit interrupt status bit The corresponding Endpoint generate Tx interrupt The corresponding Endpoint has no Tx interrupt generate

EPT0 — Endpoint 0 transmit interrupt status bit Endpoint 0 interrupt No Endpoint0 interrupt

454


30.3.2.4 INTRRX

IntrRx is a 16-bit read-only register that indicates which interrupts are currently active for the Rx Endpoints. All active interrupts are cleared when this register is read.


15 14 13 12 11 10 9 8

0 0 EPR5 EPR4 EPR3 EPR2 EPR1 0


From USB - - set set set set set -

RESET 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0


From USB - - - - - - - -

RESET 0 0 0 0 0 0 0 0


exception.

Figure 30-4 Interrupts of Rx Endpoints Register

EPREx — Endpoint x Receive interrupt status bit 1= The corresponding Endpoint generate Rx interrupt 0= The corresponding Endpoint no Rx interrupt generate

455


30.3.2.5 INTRTXE

IntrTxE is a 16 bit register that provides interrupt enable bits for the interrupts in IntrTx.


15 14 13 12 11 10 9 8

0 0 EPTE5 EPTE4 EPTE3 EPTE2 EPTE1 EPTE0

From CPU r r rw rw rw rw rw rw

From USB - - r r r r r r

RESET 0 0 0 0 0 1 1 1

7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0


From USB - - - - - - - -

RESET 0 0 0 0 0 0 0 0


exception.

Figure 30-5 Interrupts Enable register of Tx Endpoints

EPTEx — Endpointx Transmit interrupt enable bits. 1= Enable the corresponding Endpoint Tx interrupt 0= Disable the corresponding Endpoint Tx interrupt

NOTE: On reset, the bits corresponding to Endpoint0 and the Tx endpoints included in the design are set to 1, while the remaining bits are set to 0.

456


30.3.2.6 INTRRXE

IntrRxE is a 16 bit register that provides interrupt enable bits for the interrupts in IntrRx.


15 14 13 12 11 10 9 8

0 0 EPRE5 EPRE4 EPRE3 EPRE2 EPRE1 0

From CPU r r rw rw rw rw rw r

From USB - - r r r r r -

RESET 0 0 0 0 0 0 1 0

7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0


From USB - - - - - - - -

RESET 0 0 0 0 0 0 0 0


exception.

Figure 30-6 Interrupts Enable register of Rx Endpoints

EPREx — Endpoint x receive interrupt enable bit 1= Enable the corresponding Endpoint Rx interrupt 0= Disable the corresponding Endpoint Rx interrupt

NOTE: On reset, the bits corresponding to the Rx endpoints included in the design are set to 1, while the remaining bits are set to 0.

457


30.3.2.7 INTRUSB

IntrUSB is an 8-bit read-only register that indicates which USB interrupts are currently active. All Active interrupts will be cleared when this register is read.

7 6 5 4 3 2 1 0

VBUS_Err Sess_Req Discon Conn SOF Reset Resume Suspend


From USB set set set set set set set set

RESET 0 0 0 0 0 0 0 0


Address : USBC1:0x00e0_000A; USBC2:0x00e1_000A

Figure 30-7 Interrupt of USB

VBUS_Err — VBUS error during a session 1= VBus drops below the VBus Valid threshold during a session 0= VBus not drops below the VBus Valid threshold during a session.

Sess_Req — Session Request (Valid in Host Mode Only) 1= Session Request signaling has been detected 0= Session Request signaling has not been detected

Discon — USB peripheral is disconnect (Valid in Host Mode Only) 1= a session ends 0= normal USB connection

SOF — Start of Frame 1= SOF token is detected on the bus 0= No SOF token is detected on the bus

Reset 1= Reset signaling is detected on the bus 0= No reset signaling is detected on the bus

Conn (Valid in Host Mode Only) 1= Device connection is detected. 0= No Device connection is detected

Resume 1= Resume signaling is detected on the bus while the USBC is in

Suspend mode 0= No resume signaling is detected on the bus

458


Suspend 1= Suspend signaling is detected on the bus 0= No suspend signaling is detected on the bus

NOTE: Only valid in peripheral mode.

30.3.2.8 INTRUSBE

IntrUSBE is an 8-bit register that provides interrupt enable bits for each of the interrupts in IntrUSB.

Address : USBC1:0x00e0_000B; USBC2:0x00e0_000B

7 6 5 4 3 2 1 0

VBUS_Err Sess_Req Discon Conn SOF Reset Resume Suspend


From USB r R r r r r r r

RESET 0 0 0 0 0 1 1 0


Figure 30-8 Interrupt Enable Register of USB

Each bit set to 1 means enable the corresponding interrupt.

459


30.3.2.9 FRAME Number Register (FNUMR)

Frame is a 16-bit read-only register that holds the last received frame number.

Address : USBC1:0x00e0_000C and 0x00e0_000D; USBC2:0x00e1_000C and 0x00e1_000D

15 14 13 12 11 10 9 8

rsv rsv rsv rsv rsv Frame Number[10:8]


From USB w w w w w w w w

RESET 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

Frame Number[7:0]



RESET 0 0 0 0 0 0 0 0


exception.

Figure 30-9 Frame Number register

30.3.2.10 Endpoint INDEX Register (EINDEXR)

Each Tx endpoint and Rx endpoint have their own set of control/status registers. The Endpoint INDEX register is 4-bit register that determines which endpoint control/status registers are accessed.

Address : USBC1:0x00e0_000E; USBC2:0x00e0_000E

7 6 5 4 3 2 1 0

0 0 0 0 Endpoint be selected



RESET 0 0 0 0 0 0 0 0


Figure 30-10 Endpoints INDEX register

460


30.3.2.11 TESTMODE

Testmode is a 7-bit register is used to put the USBC into one of the four test modes for High-speed operation described in the USB2.0 specification - in response to a SET FEATURE:TESTMODE command. It is not used in normal operation.

Address : USBC1:0x00e0_000F; USBC1:0x00e0_000F

7 6 5 4 3 2 1

FIFO_Acce

ss(selfclear) Force_FS Force_HS Test_Packet Test_K Test_J

Test_SE0_

NAK

From CPU set rw rw rw rw rw rw

From USB r r r r r r r

RESET 0 0 0 0 0 0 0


Figure 30-11 Testmode register

FIFO_Access The CPU sets this bit to transfer the packet in the Endpoint0 Tx FIFO to the Endpoint0 Rx FIFO. It is cleared automatically.

1= transfer the packet in the EP0 Tx FIFO to the EP0 Rx FIFO 0= normal

Force_FS The CPU sets this bit to force the USBC into Full-speed mode when it receives a USB reset.

1= Force USBC into Full-speed mode 0= normal

Force_HS The CPU sets this bit to force the USBC into High-speed mode when it receives a USB reset

1= Force USBC into High-speed mode 0= normal

Test_Packet (High-speed mode) The CPU sets this bit to enter the Test_Packet test mode. In this mode, the USBC repetitively transmits on the bus a 53- byte test packet, the form of which is defined in the USB 2.0 Specification Section 7.1.20. The test packet has a fixed format and must be loaded into the EP0 FIFO before the test mode is entered.

461


1= In the Test_Packet test mode 0= normal

Test_K (High-speed mode) The CPU sets this bit to enter the Test_K test mode. In this mode, the USBC transmits a continuous K on the bus.

1= In the Test_K test mode 0= normal

Test_J (High-speed mode) The CPU sets this bit to enter the Test_J test mode. In this mode, the USBC transmits a continuous J on the bus.

1= In the Test_J test mode 0= normal

Test_SE0_NAK (High-speed mode) The CPU sets this bit to enter the Test_SE0_NAK test mode. In this mode, the USBC remains in High-speed mode but responds to any valid IN token with a NAK.

1= In the Test_SE0_NAK test mode 0= normal

30.3.2.12 OTGCTL

OtgCtl is a 7-bit register used to select whether the USBCx is operating in peripheral mode or in host mode, and for controlling and monitoring the USB VBus line.


7 6 5 4 3 2 1 0

B-Dev FSDev LSDev VBus[1:0] Host Mode Host Req Session

From CPU r r r r r rw rw

From USB rw rw rw rw rw r/clr rw

RESET 0 0 0 0 0 0 0 0


Figure 30-12 OTG Controller Register

B-Dev This Read-only bit indicates whether the USBC is operating as the ‘A’ device or the ‘B’ device.

1= ’A’ device 0= ’B’ device

462


FSDev This bit is set when a full-speed or high-speed device has been detected being connected to the port.

1= HS device is connected 0= No HS device is connected

NOTE: Only valid in host mode.

LSDev This bit is set when a low-speed has been detected being connected to the port.

1= LS device is connected 0= No LS device is connected

NOTE: Only valid in host mode.

VBus[1:0] These Read-only bits encode the current VBus level

0x0 = Below SessionEnd 0x1 = Above SessionEnd, below AValid 0x2 = Above AValid, below VBusValid 0x3 = Above VBusValid

Host Mode This bit is set when USBCx is acting as a Host.

1= USBCx is host 0= USBCx is peripheral

Host Req When set, the USBCx will initiate the host negotiation when suspend mode is entered. It is cleared when host negotiation is completed.

1= USBCx initiates the host negotiation 0= USBCx does not initiate the host negotiation

Session When operating as an ‘A’ device, this bit is set or cleared by the CPU to start or end a session. When operating as a ‘B’ device, this bit is set/cleared by the USBC when a session starts/ends.

463


30.3.3 INDEXED REGISTERS

30.3.3.1 Endpoint0 Control and Status Register(E0CSR)

E0CSR0 in Peripheral Mode:

E0CSR is a 16-bit register that provides control and status bits for Endpoint0.


15 14 13 12 11 10 9 8

Flush

FIFO

From CPU r r r r r r r set


RESET 0 0 0 0 0 0 0 0

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Service

SetupEnd

(selfclear)

Serviced

RxPktRdy

(selfclear)

SendStall

(selfclear) SetupEnd

DataEnd

(selfclear) SentStall

TxPktRdy

(selfclear) RxPktRdy

From CPU set set set r set r/clear r/set r

From USB r r r set r set r set

RESET 0 0 0 0 0 0 0 0


exception.

Figure 30-13 Endpoint0 Control and Status Register

ServicedSetupEnd — SetupEnd is serviced. The CPU writes a 1 to this bit to clear the SetupEnd bit. It is cleared automatically.

1= Clear the SetupEnd bit. 0= normal

ServicedRxPktRdy — RxPktRdy is serviced. The CPU writes a 1 to this bit to clear the RxPktRdy bit. It is cleared automatically.

1= Clear the RxPktRdy bit. 0= normal

464


SendStall The CPU writes a 1 to this bit to terminate the current transaction. The STALL handshake will be transmitted and then this bit will be cleared automatically.

1= The STALL handshake will be transmitted 0= normal

SetupEnd This bit will be set when a control transaction ends before the DataEnd bit has been set. An interrupt will be generated and the FIFO flushed at this time. The bit is cleared by the CPU writing a 1 to the ServicedSetupEnd bit.

1= a control transaction ends 0= normal

DataEnd The CPU sets this bit when setting TxPktRdy for the last data packet; when clearing RxPktRdy after unloading the last data packet; when setting TxPktRdy for a zero length data packet. It is cleared automatically.

1= Data phase of a control transfer end 0= normal

SentStall This bit is set when a STALL handshake is transmitted. The CPU should clear this bit.

1= a STALL handshake is transmitted. 0= normal

TxPktRdy The CPU sets this bit after loading a data packet into the FIFO. It is cleared automatically when the data packet has been transmitted. An interrupt is also generated (if enabled) when the bit is set.

1= a data packet has loaded into the FIFO 0= no data packet in the FIFO

RxPktRdy This bit is set when a data packet has been received. An interrupt is generated when this bit is set. The CPU clears this bit by setting the ServicedRxPktRdy bit.

1= a data packet has been received 0= normal

FlushFIFO This bit is used to flush the next packet to be transmitted/read from the Endpoint 0 FIFO. The FIFO pointer is reset and the TxPkRdy/RxPktRdy bit is cleared by writing a 1 to this bit.

465


1= FIFO is flushed and cleared automatically. Only valid when TxPkRdy/RxPktRdy is set.

0= No effect

E0CSR0 in Host Mode:

E0CSR is a 16-bit register that provides control and status bits for Endpoint0.


15 14 13 12 11 10 9 8

Flush

FIFO

From CPU r r r r r r r set


RESET 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

NAK

Timeout Status Pkt ReqPkt Error SetupPkt RxStall TxPktRdy RxPktRdy

From CPU r/clear rw rw r/clear r/clear r/clear r/set r/clear

From USB set r rw set rw set clear rw

RESET 0 0 0 0 0 0 0 0


exception.

Figure 30-14 Endpoint0 Control and Status Register

FlushFIFO — SetupEnd is serviced. This bit is used to flush the next packet to be transmitted/read from the Endpoint 0 FIFO. The FIFO pointer is reset and the TxPkRdy/RxPktRdy bit is cleared by writing a 1 to this bit.

1= FIFO is flushed and cleared automatically. Only valid when TxPkRdy/RxPktRdy is set.

0= No effect

NAK Timeout This bit will be set when Endpoint0 is halted following the receipt to NAK response for longer than the time set by the NAKLimit0 register. The CPU should clear this bit to allow the endpoint to continue.

1= Allow NAK timeout 0= Not allow NAK timeout

466


StatusPkt The CPU sets this bit at the same time as the TxPktRdy or ReqPkt bit is set, to perform a status stage transaction. Setting this bit ensures that the data toggle is set to 1 so that a DATA1 packet is used for the Status Stage transaction.

ReqPkt The CPU sets this bit to request an IN transaction. It is cleared when RxPktRdy is set.

Error This bit will be set when three attempts have been made to perform a transaction with no response from the peripheral. The CPU should clear this bit. An interrupt is generated when this bit is set.

SetupPkt The CPU sets this bit, at the same time as the TxPktRdy bit is set, to send a SETUP token instead of an OUT token for the transaction.

RxStall This bit is set when a STALL handshake is received. The CPU should clear this bit.

TxPktRdy The CPU sets this bit after loading a data packet into the FIFO. It is cleared automatically when the data packet has been transmitted. An interrupt is generated (if enabled) when the bit is cleared.

RxPktRdy This bit is set when a data packet has been received. An interrupt is generated (if enabled) when this bit is set. The CPU should clear this bit when the packet has been read from the FIFO.

467


30.3.3.2 Endpoint0 Counter Register (E0COUNTR)

Endpoint0 Counter Register (E0COUNTR) is a 7-bit read-only register that indicates the number of received data bytes in the Endpoint0 FIFO.


7 6 5 4 3 2 1 0

0 Endpoint be selected

From CPU 0 r r r r r r r

From USB 0 w w w w w w w

RESET 0 0 0 0 0 0 0 0


exception.

Figure 30-15 Endpoint0 Counter Register

Endpoint0 Rx Counter The value will be changed as the contents of the FIFO change and is only valid while RxPktRdy (E0CSR.Bit0) is set. While valid, it indicates the number of received data bytes in the Endpoint0 FIFO.

30.3.3.3 TxType (Host Mode Only)

TxType is a 6-bit register that should be written with the endpoint number to be targeted by the endpoint in the lower 4 bits, and the transaction protocol to use for the currently-selected Tx endpoint in the upper 2 bits. There is a TxType register for each configured Tx endpoint (except Endpoint 0).

Address: USBC1:0x00e0_001A; USBC2:0x00e1_001A

7 6 5 4 3 2 1 0

0 0 Protocol Target Endpoint Number[3:0]

From CPU rw rw rw rw rw rw

From USB r r r r r r

RESET: 0 0 0 0 0 0 0 0


468


Protocol The CPU should set this to select the required protocol for the Tx endpoint: 00: Illegal 01: Isochronous 10: Bulk 11: Interrupt

Target Endpoint Number The CPU should set this value to the endpoint number contained in the Tx endpoint descriptor returned to the MUSBHDRC during device enumeration.

30.3.3.4 NAKLimit0 (Host Mode Only)

Address: USBC1:0x00e0_001B; USBC2:0x00e1_001B

7 6 5 4 3 2 1 0

0 0 0 Endpoint 0 NAK Limit (m)

From CPU rw rw rw rw rw


RESET: 0 0 0 0 0 0 0 0


NAKLimit0 is a 5-bit register that sets the number of frames/microframes (High-Speed transfers) after which Endpoint 0 should timeout on receiving a stream of NAK responses. (Equivalent settings for other endpoints can be made through their TxInterval and RxInterval registers).

The number of frames/microframes selected is 2(m-1) (where m is the value set in the register, valid values 2 – 16). If the host receives NAK responses from the target for more frames than the number represented by the Limit set in this register, the endpoint will be halted.

NOTE: A value of 0 or 1 disables the NAK timeout function.

30.3.3.5 TxInterval (Host Mode Only)

TxInterval is an 8-bit register that, for Interrupt and Isochronous transfers, defines the polling interval for the currently-selected Tx endpoint. For Bulk endpoints, this register sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. There is a TxInterval register for each configured Tx endpoint (except Endpoint 0).

469


Address: USBC1:0x00e0_001B; USBC2:0x00e1_001B

7 6 5 4 3 2 1 0

Tx Polling Interval/NAK Limit (m)



RESET: 0 0 0 0 0 0 0 0


In each case the value that is set defines a number of frames/microframes (High Speed transfers), as follows (Table 30-2) :

Table 30-2 TxInterVal Definition Transfer

Type Speed Valid Values(m) Interpretation

Interrupt Low Speed or Full Speed 1 – 255 Polling interval is m frames.

High Speed 1 – 16 Polling interval is 2(m-1) microframes.

Isochronous Full Speed or High Speed 1 – 16 Polling interval is 2(m-1) frames/microframes.

Bulk Full Speed or High Speed 2 – 16 NAK Limit is 2(m-1) frames/microframes.

Note: A value of 0 or 1 disables the NAK timeout

function.

30.3.3.6 Tx Payload Size Register (TXPSZR)

The Tx Payload Size Register defines the maximum amount of data bytes that can be transferred through the selected Tx(x=1) endpoints in a single operation excluding endpoint0.


15 14 13 12 11 10 9 8

0 0 0 0 0 TXMAXP[10:8]

From

CPU rw rw rw rw rw rw rw rw


RESET 0 0 0 0 0 0 0 0

470


7 6 5 4 3 2 1 0

TXMAXP[7:0]

From



RESET 0 0 0 0 0 0 0 0


Figure 30-16 Tx Payload Size Register

TXMAXP — Maximum Payload/transaction Bit[10:0] This defines the maximum payload transmitted in a single transaction. The value can be up to 1024 bytes but should match the USB Specification on packet sizes for different transfers and different speed.

30.3.3.7 Tx Control and Status Register (TXCSR)

The Tx Control and Status Register is a 16-bit register that provides control and status bits for transfers through the currently-selected Tx endpoint. There is a TxCSR register (selected by the EINDEXR register) for each configured Tx(x=1) endpoint (not including Endpoint0).

TXCSR in Peripheral Mode:


15 14 13 12 11 10 9 8

AutoSet 0 0 0 FrcDataTo

g 0 0 0

From CPU rw r r r rw r r r


RESET 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

0 ClrDataTo

g SentStall SendStall

FlushFIFO

(selfclear) UnderRun

FIFO

NotEmpty TxPktRdy

From CPU r set r/clear rw set r/clear r/clear r/set

From USB r r/clear set r r set set clear

RESET 0 0 0 0 0 0 0 0

471



Figure 30-17 Endpointx Tx Control and Status Register

Autoset If the CPU sets this bit, TxPktRdy will be automatically set when data of the maximum packet size (value in TXPSZR) is loaded into the Tx FIFO. If a packet of less than the maximum packet size is loaded, then TxPktRdy will have to be set manually.

1= TxPktRdy will be automatically set 0= TxPktRdy will be set manually

FrcDataTog The CPU sets this bit to force the endpoint data toggle to switch and the data packet to be cleared from the FIFO, regardless of whether an ACK was received.

1= Force the endpoint data toggle to switch and the data packet to be cleared from the FIFO.

0= normal

ClrDataTog The CPU writes a 1 to this bit to reset the endpoint data toggle to 0.

1= reset the endpoint data toggle to 0 0= normal

SentStall This bit is set when a STALL handshake is transmitted. The FIFO is flushed and the TxPktRdy bit is cleared. The CPU should clear this bit.

1= a STALL handshake is transmitted 0= normal

SendStall The CPU writes a 1 to this bit to issue a STALL handshake to an IN token. The CPU clears this bit to terminate the stall condition.

1= issue a STALL handshake to an IN token 0= no stall condition

FlushFIFO The CPU writes a 1 to this bit to flush the next packet to be transmitted from the endpoint Tx FIFO. The FIFO pointer is reset and the TxPktRdy bit is cleared. This bit has no effect unless TxPktRdy is set. Also note that, if the FIFO is double-buffered, FlushFIFO may need to be set twice to completely clear the FIFO.

1= Flush the next packet to be transmitted from the endpoint Tx FIFO. 0= normal

472


UderRun The USB sets this bit if an IN token is received when TxPktRdy is not set. The CPU should clear this bit.

1= an IN token is received when TxPktRdy is not set 0= normal

FIFONotEmpty The USB sets this bit when there is at least 1 packet in the Tx FIFO.

1= at least 1 packet in the Tx FIFO 0= no packet in the Tx FIFO

TxPktRdy The CPU sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet has been transmitted. An interrupt is generated when the bit is cleared.

1= a data packet has been loaded into the FIFO 0= no data packet has been loaded into the FIFO

TXCSR in Host Mode:


15 14 13 12 11 10 9 8

AutoSet 0 0 0 FrcDataTo

g 0 0 0

From CPU rw r r r rw r r r


RESET 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

NAK

Timeout

ClrDataTo

g RxStall -

FlushFIFO

(selfclear) Error

FIFO

NotEmpty TxPktRdy

From CPU r/clear set r/clear r set r/clear r/clear r/set

From USB set r/clear set r r rw set clear

RESET 0 0 0 0 0 0 0 0


exception.

Figure 30-18 Endpointx Tx Control and Status Register

473


Autoset If the CPU sets this bit, TxPktRdy will be automatically set when data of the maximum packet size (value in TXPSZR) is loaded into the Tx FIFO. If a packet of less than the maximum packet size is loaded, then TxPktRdy will have to be set manually.

1= TxPktRdy will be automatically set 0= TxPktRdy will be set manually

FrcDataTog The CPU sets this bit to force the endpoint data toggle to switch and the data packet to be cleared from the FIFO, regardless of whether an ACK was received.

1= Force the endpoint data toggle to switch and the data packet to be cleared from the FIFO.

0= normal

NAK Timeout This bit will be set when Tx endpoint is halted following the receipt of NAK response for longer than the time set by the NAKLimit by the TxInterval register. The CPU should clear this bit to allow the endpoint to continue. This bit is only valid for bulk endpoint.

1= Allow NAK timeout 0= Not allow NAK timeout


1= reset the endpoint data toggle to 0 0= normal

RxStall This bit is set when a STALL handshake is received. The FIFO is flushed and the TxPktRdy bit is cleared. The CPU should clear this bit.

1= a STALL handshake is received 0= normal

FlushFIFO The CPU writes a 1 to this bit to flush the next packet to be transmitted from the endpoint Tx FIFO. The FIFO pointer is reset and the TxPktRdy bit is cleared. This bit has no effect unless TxPktRdy is set. Also note that, if the FIFO is double-buffered, FlushFIFO may need to be set twice to completely clear the FIFO.

1= Flush the next packet to be transmitted from the endpoint Tx FIFO. 0= normal

474


Error The USB sets this bit when 3 attempts have been made to send a packet and no handshake packet has been received. The CPU should clear this bit. An interrupt is generated when the bit is set. This bit is only valid in bulk or interrupt mode.

FIFONotEmpty The USB sets this bit when there is at least 1 packet in the Tx FIFO.

1= at least 1 packet in the Tx FIFO 0= no packet in the Tx FIFO

TxPktRdy The CPU sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet has been transmitted. An interrupt is generated when the bit is cleared.

1= a data packet has been loaded into the FIFO 0= no data packet has been loaded into the FIFO

30.3.3.8 Rx Payload Size Register (RXPSZR)

The Rx Payload Size Register defines the maximum amount of data that can be transferred through the selected Rx(x=1) endpoint in a single operation excluding endpoint0. There is a RXPSZR register for each Rx endpoint selected by index register. RxMaxP defines the maximum amount of data that can be transferred trough the selected Rx endpoint in a single operation.


15 14 13 12 11 10 9 8

0 0 0 0 0 RXMAXP[10:8]

From



RESET 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

RXMAXP[7:0]

From



RESET 0 0 0 0 0 0 0 0

475



Figure 30-19 Rx Payload Size Register

Maximum Payload/transaction Bit[10:0] This defines the maximum payload transmitted in a single transaction. The value can be up to 1024 bytes but should match the USB Specification on packet sizes for different transfers and different speed.

30.3.3.9 Rx Control and Status Register (RXCSR)

The Rx Control and Status Register is a 16-bit register that provides control and status bits for transfers through the currently-selected Rx(x=1) endpoint. There is a RxCSR register for each configured Rx endpoint (not including Endpoint0).

RXCSR in Peripheral Mode:


15 14 13 12 11 10 9 8

AutoClear Rsv Rsv DisNyet Rsv Rsv Rsv Rsv

From CPU rw r r rw r r r r


RESET 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

ClrDataTo

g SentStall SendStall

FlushFIFO

(selfclear) - -

FIFO Full


From CPU set r/clear rw set r r r r/clear

From USB r/clear set r r r r set set

RESET 0 0 0 0 0 0 0 0


Figure 30-20 Endpoint Rx Control and Status Register

476


AutoClear If the CPU sets this bit then the RxPktRdy bit will be automatically cleared when a packet of packet size are unloaded, RxPktRdy will have to be cleared manually.

1= RxPktRdy bit automatically cleared when a packet of packet size are unloaded

0= RxPktRdy bit have to be cleared manually

DisNyet The CPU sets this bit to disable the sending of NYET handshakes. When set, all successfully received Rx packets are ACK’d including at the point at which the FIFO becomes full. This bit only has any effect in High-speed mode, in which mode it should be set for all Interrupt endpoints.

1= disable the sending of NYET handshakes 0= enable the sending of NYET handshakes


1= the endpoint data toggle is 0 0= normal

SentStall This bit is set when a STALL handshake is transmitted. The CPU should clear this bit.

1= a STALL handshake is transmitted 0= normal

SendStall The CPU writes a 1 to this bit to issue a STALL handshake. The CPU clears this bit to terminate the stall condition.

1= issue a STALL handshake 0= normal

FlushFIFO The CPU writes a 1 to this bit to flush the next packet to be read from the endpoint Rx FIFO. The FIFO pointer is reset and the RxPktRdy bit is cleared. FlushFIFO has no effect unless RxPktRdy is set. Also if the FIFO is double-buffered, Flush FIFO may need to be set twice to completely clear the FIFO.

1= Flush the next packet to be read from the endpoint Rx FIFO 0= normal

FIFOFull This bit is set when no more packets can be loaded into the Rx FIFO.

1= FIFO is full

477


0= normal

RxPktRdy This bit is set when a data packet has been received. The CPU should clear this bit when the packet has been unloaded from the Rx FIFO. An interrupt is generated when the bit is set.


RXCSR in Host Mode:


15 14 13 12 11 10 9 8

AutoClear AutoReq Rsv PID Error Rsv Rsv Rsv Rsv

From CPU rw rw r r r r r r

From USB r r r rw r r r r

RESET 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

ClrDataTo

g RxStal ReqPkt

FlushFIFO

(selfclear) Rsv Error

FIFO Full


From CPU set r/clear rw set r r/clear r r/clear

From USB r/clear set rw r r set set set

RESET 0 0 0 0 0 0 0 0


Figure 30-21 Endpoint Rx Control and Status Register

AutoClear If the CPU sets this bit then the RxPktRdy bit will be automatically cleared when a packet of packet size are unloaded, RxPktRdy will have to be cleared manually.

1= RxPktRdy bit automatically cleared when a packet of packet size are unloaded

0= RxPktRdy bit have to be cleared manually

AutoReq If the CPU sets this bit, the ReqPkt bit will be automatically set when the RxPktRdy bit is cleared.

478


DisNyet The CPU sets this bit to disable the sending of NYET handshakes. When set, all successfully received Rx packets are ACK’d including at the point at which the FIFO becomes full. This bit only has any effect in High-speed mode, in which mode it should be set for all Interrupt endpoints.

1= disable the sending of NYET handshakes 0= enable the sending of NYET handshakes


1= the endpoint data toggle is 0 0= normal

RxStall When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit.

1= a STALL handshake is received 0= normal

ReqPkt The CPU writes a 1 to this bit to request an IN transaction. It is cleared when RxPktRdy is set.

1= request an IN transaction 0= normal

FlushFIFO The CPU writes a 1 to this bit to flush the next packet to be read from the endpoint Rx FIFO. The FIFO pointer is reset and the RxPktRdy bit is cleared. FlushFIFO has no effect unless RxPktRdy is set. Also if the FIFO is double-buffered, Flush FIFO may need to be set twice to completely clear the FIFO.

1= Flush the next packet to be read from the endpoint Rx FIFO 0= normal

Error The USB sets this bit when 3 attempts have been made to send a packet and no handshake packet has been received. The CPU should clear this bit. An interrupt is generated when the bit is set. This bit is only valid in bulk or interrupt mode.

FIFOFull This bit is set when no more packets can be loaded into the Rx FIFO.

1= FIFO is full 0= normal

RxPktRdy

479


This bit is set when a data packet has been received. The CPU should clear this bit when the packet has been unloaded from the Rx FIFO. An interrupt is generated when the bit is set.


30.3.3.10 Rx Counter Register (RXCOUNTR)

The Rx Counter Register is a 13-bit read-only register that holds the number of received data bytes in the packet in the Rx(x=1) endpoint FIFO. The value returned changes as the FIFO is unloaded and is only valid while RxPktRdy (RxCSR.Bit0) is set.

Address : USBC1:0x00e0_0018~0x00e0_0019; USBC2:0x00e1_0018~0x00e1_0019

15 14 13 12 11 10 9 8

Rsv Rsv Rsv Rx_count[12:8]


From USB r r r w w w w w

RESET 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

Rx_count[7:0]



RESET 0 0 0 0 0 0 0 0


exception.

Figure 30-22 Rx Counter Register

30.3.3.11 TXFIFOSZ

TXFIFOSZ controls the size of the selected Tx endpoint FIFO.

Address: USBC1:0x00e0_0062; USBC2:0x00e1_0062

7 6 5 4 3 2 1 0

0 0 0 Rsv SZ3 SZ2 SZ1 SZ0

From CPU r r r r rw rw rw rw


480


RESET: 0 0 0 0 0 0 0 0


Figure 30-23 Tx Endpoint FIFO Size Register

SZ[3:0] — Packet Size Selects The SZ bits defines the maximum packet size to be allowed.

Table 30-3 Packet Size Selection SZ[3:0] Packet Size ( byte)

0 0 0 0 8

0 0 0 1 16

0 0 1 0 32

0 0 1 1 64

0 1 0 0 128

0 1 0 1 256

0 1 1 0 512

0 1 1 1 1024

1 0 0 0 2048

1 0 0 1 4096

30.3.3.12 RXTYPE (Host Mode Only)

RxType is a 6-bit register that should be written with the endpoint number to be targeted by the endpoint in the lower 4 bits, and the transaction protocol to use for the currently-selected Rx endpoint in the upper 2 bits. There is an RxType register for each configured Rx endpoint (except Endpoint 0).

481


Address: USBC1:0x00e0_001C; USBC2:0x00e1_001C

7 6 5 4 3 2 1 0

0 0 Protocol Target Endpoint Number (TEN)

From CPU rw rw rw rw rw rw


RESET: 0 0 0 0 0 0 0 0


exception.

Figure 30-24 RxType Register

Protocol The CPU should set this to select the required protocol for the Rx endpoint.

00= illegal 01= illegal 10= bulk 11= interrupt

TEN[3:0] The CPU should set this value to the endpoint number contained in the Rx endpoint descriptor returned to the USBCx during device enumeration.

30.3.3.13 RXINTERVAL (Host Mode Only)

RxInterval is an 8-bit register that, for Interrupt transfer, defines the polling interval for the currently-selected Rx endpoint. For Bulk endpoint, this register sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK response. There is a RxInterval register for each configured Rx endpoint (except Endpoint 0). In each case the value that is set defines a number of frames/microframes (high speed transfer).

482


Address: USBC1:0x00e0_001D; USBC2:0x00e1_001D

7 6 5 4 3 2 1 0

Rx Polling Interval/NAK Limit (m)



RESET: 0 0 0 0 0 0 0 0


Figure 30-25 RxInterval Register

Table 30-4

Transfer Type

Speed Valid

values (m)

Interpretation

Interrupt Low Speed or Full Speed 1-255 Polling interval is m frames

High Speed 1-16 Polling interval is 2(m-1) microframes

Bulk Full Speed or High

Speed 2-16

NAK Limit is (舩2(m-1) frames/microframes. Note: A value of 0 or 1 disables the NAK

timeout function.

30.3.3.14 RXFIFOSZ

RXFIFOSZ controls the size of the selected Rx endpoint FIFO.

Address: USBC1:0x00e0_0063; USBC2:0x00e1_0063

7 6 5 4 3 2 1 0

0 0 0 DPB SZ3 SZ2 SZ1 SZ0


From USB r r r r r

RESET: 0 0 0 0 0 0 0 0


Figure 30-26 Rx Endpoint FIFO Size Register

DPB — Double-Packet Buffering The DPB bit defines whether double-packet buffering supported.

1= Double-packet buffering is supported.

483


0= Only single-packet buffering is supported

SZ[3:0] — Packet Size Selects The SZ bits defines the maximum packet size to be allowed.

Table 30-5 Packet Size Selection SZ[3:0] Packet Size( byte)

0 0 0 0 8

0 0 0 1 16

0 0 1 0 32

0 0 1 1 64

0 1 0 0 128

0 1 0 1 256

0 1 1 0 512

0 1 1 1 1024

1 0 0 0 2048

1 0 0 1 4096

484


30.3.3.15 TXFIFOADD

TXFIFOADD controls the start address of the selected Tx endpoint FIFO.

Address: USBC1:0x00e0_0064~0x00e0_0065; USBC2:0x00e1_0064~0x00e1_0065D

15 14 13 12 11 10 9 8

0 0 0 AD[12:8]



RESET: 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

AD[7:0]



RESET: 0 0 0 0 0 0 0 0


exception.

Figure 30-27 Tx Endpoint FIFO Address Register

AD[12:0] — Start Address of the Tx endpoint FIFO The start address selection is in units of 8 bytes as follows.

Table 30-6 Tx Endpoint FIFO Start Address Selection AD[12:0] Start Address

0 0 0 0 皔0x0000

0 0 0 1 0x0008

0 0 0 2 0x0010

… …

1 F F F 0xFFF8

485


30.3.3.16 RXFIFOADD

RXFIFOADD controls the start address of the selected Rx endpoint FIFO.

Address: USBC1:0x00e0_0066~0x00e0_0067; USBC2:0x00e1_0066~0x00e1_0067

15 14 13 12 11 10 9 8

0 0 0 AD[12:8]



RESET: 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

AD[7:0]



RESET: 0 0 0 0 0 0 0 0


exception.

Figure 30-28 Rx Endpoint FIFO Address Register

AD[12:0] — Start Address of the Rx endpoint FIFO The start address selection is in units of 8 bytes as follows.

Table 30-7 Rx Endpoint FIFO Start Address Selection

AD[12:0] Start Address

0 0 0 0 !a0x0000

0 0 0 1 0x0008

0 0 0 2 0x0010

… …

1 F F F 0xFFF8

486


30.3.3.17 FIFO0 Entry (Address: USBC1:0x00e0_0020; USBC2:0x00e1_0020)

This address provides the entry for CPU access to the FIFO of endpoint 0. Writing to the address loads data into the TxFIFO for endpoint 0. Reading from the address unloads data from the RxFIFO for endpoint 0.





30.3.3.20 FIFO3 Entry (Address: USBC1:0x00e0_002c; USBC2:0x00e1_002c)


30.3.3.21 FIFO4 Entry (Address: USBC1:0x00e0_0030)


30.3.3.22 FIFO5 Entry (Address: USBC1:0x00e0_0034)


30.3.3.23 Endpoint 1 Transfer Length (EP1_TX_LEN)

This Register sets the current transfer length of Endpoint1.

487


NOTE: FIFOx Entry and EP1_TX_LEN shall be used alternatively. EP1_TX_LEN register must be configured before set relative TxPktRdy (Configure EINDEXR and TXCSR).


15 14 13 12 11 10 9 8

0 0 0 0 0 EP1_TX_LEN[10:8]

From

CPU r r r r r rw rw rw


RESET 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

EP1_TX_LEN[7:0]

From



Reset 0 0 0 0 0 0 0 0


exception.

Figure 30-29 EP1_TX_LEN Register




488



15 14 13 12 11 10 9 8

0 0 0 0 0 EP2_TX_LEN[10:8]

From



RESET 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

EP2_TX_LEN[7:0]

From



Reset 0 0 0 0 0 0 0 0


exception.





489


Address : USBC1:0x00e0_0048 and 0x00e0_0049

15 14 13 12 11 10 9 8

0 0 0 0 0 EP3_TX_LEN[10:8]

From



RESET 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

EP3_TX_LEN[7:0]

From



Reset 0 0 0 0 0 0 0 0


exception.





490


Address : USBC1:0x00e0_004c and 0x00e0_004d

15 14 13 12 11 10 9 8

0 0 0 0 0 EP4_TX_LEN[10:8]

From



RESET 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

EP4_TX_LEN[7:0]

From



Reset 0 0 0 0 0 0 0 0


exception.





491


Address : USBC1:0x00e0_0050 and 0x00e0_0051

15 14 13 12 11 10 9 8

0 0 0 0 0 EP5_TX_LEN[10:8]

From



RESET 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

EP5_TX_LEN[7:0]

From



Reset 0 0 0 0 0 0 0 0



30.3.3.28 Endpoint 0 Length (EP0_LEN)

This Register sets the current length of Endpoint0.


7 6 5 4 3 2 1 0

EP0_LEN[7:0]

From



RESET 0 0 0 0 0 0 0 0


Figure 30-34 EP0_LEN Register

492


30.4 FUNCTION DESCRIPTION

30.4.1 RESET

When a reset condition is detected on the bus, the USBC tries to negotiate high-speed operation if the HS Enable bit in UCSR register is set. And the device will perform the following actions:

Set the FAdress register to zero.

Set EINDEXR register to zero

Flush all endpoints FIFOs.

Clear all control and status register

Enable all endpoint interrupt

Generate a Reset interrupt.

30.4.2 SOFTCONNECT

The USBC can be controlled by software to allow the connection to the USB bus. The USB PHY can be switched between normal mode and non-driving mode by setting or clearing bit 6(Soft Conn bit) of the UCSR register. If this bit is set, the USB PHY will be in the normal mode and the data lines of the USB bus are enabled. Setting Soft Conn bit will also put the USBC to POWERED state. In this state, the USBC will not respond to any USB signaling except a USB reset. When Soft Conn bit is cleared, the USB PHY will be put into non-driving mode and USB data lines are tri-stated. In non-driving mode, the USB device appears disconnected to the other devices on the USB bus.

After the system reset, Soft Conn is cleared to 0. So the software can then choose when to connect USB bus through setting Soft Conn bit. Normally, the software should ensure the initialization is complete and the system is ready to perform enumeration before connecting to the USB.

30.4.3 SOF

The USBC should received a SOF (start of frame) packet from the host once every 1ms when is Full-speed mode, or every 125us when in High-speed mode.

A SOF interrupt will be generate when the SOF packet is received if the SOF interrupt is enabled. And the frame number contained in the packet is written into the Frame Number register. If no SOF packet is received after 1.00358 ms (or 125.125 us), it is assumed the packet has been lost. The USBC will

493


continue to generate the SOF interrupt every millisecond or 125ns, but the Frame number register is not updated.

30.4.4 SUSPEND/RESUME

When no activity has occurred on the USB for 3 ms, the USBC will enter Suspend mode and the suspend interrupt will be generated.

When Resume signaling is detected, the clock to the USBC must be restarted, and the USBC will exit Suspend mode, while the Resume interrupt will be generated at this case.

The USBC can also support remote wakeup. The CPU can set the Resume bit in the UCSR register to get the USBC out of suspend mode and drive Resume signaling onto the bus. The CPU should clear this bit after approximately 10 ms to end the Resume signal. At this time no Resume interrupt will be generated.

30.4.5 IN TRANSACTION HANDLING

IN transaction is handled through the USBC Tx FIFOs.

The maximum size of data packet is programmable and determined by the value written to the TXPSZR register for the endpoint.

The maximum packet size set for any endpoint must not exceed the FIFO size. And the TXPSZR register should not be written to while there is data in the FIFO as unexpected results may occur.

30.4.5.1 SINGLE PACKET BUFFERING

Only one packet can be buffered in the FIFO. As each packet to be sent is load ed into the Tx FIFO, the TxPktRdy bit in TxCSR needs to be set. If the AutoSet bit in TxCSR is set, the TxPktRdy bit will be automatically set when a maximum-sized packet is loaded into the FIFO. For packet sizes less than the maximum, TxPktRdy will always have to be set manually.

When the TxPktRdy bit is set, either manually or automatically, the FIFONotEmpty bit in TxCSR is also set and the packet is ready to be sent. When the packet has been successfully sent, both TxPktRdy and FIFONotEmpty will be cleared and the appropriate Tx endpoint interrupt generated. The next packet can then be loaded into the FIFO.

30.4.6 OUT TRANSACTION HANDLING

OUT transaction is handled trough the USBC Rx FIFOs.

494


The maximum size of data packet is programmable and determined by the value written to the RXPSZR register for the endpoint.

The maximum packet size set for any endpoint must not exceed the FIFO size.

30.4.6.1 SINGLE PACKET BUFFERING

Only one packet can be buffered in the FIFO. When a packet is received and placed in the Rx FIFO, the RxPktRdy bit and the FIFOFull bit in RxCSR are set and the appropriate Rx endpoint interrupt is generated (if enabled) to signal that a packet can now be unloaded from the FIFO.

After the packet has been unloaded, the RxPktRdy bit needs to be cleared in order to allow further packets to be received. If the AutoClear bit in RxCSR is set and a maximum-sized packet is unloaded from the FIFO, the RxPktRdy bit is cleared automatically. The FIFOFull bit is also cleared. For packet size that is less than the maximum, RxPktRdy will always have to be cleared manually.

495


30.5 OPERATION

30.5.1 Three USB TRANSFER TYPE INTRODUCTION

30.5.1.1 CONTROL TRANSFER

Control transfers are typically used for command and status operations. They are essential to set up a USB device with all enumeration functions being performed using control transfers. In our USBC, endpoint0 support this transfer.

A control transfer can have up to three stages:

The Setup Stage is where the request is sent. This consists of three packets. The setup token is sent first which contains the address and endpoint number. The data packet is sent next and always has a PID type of data0 and includes a setup packet which details the type of request. We detail the setup packet later. The last packet is a handshake used for acknowledging successful receipt or to indicate an error. If the function successfully receives the setup data (CRC and PID etc OK) it responds with ACK, otherwise it ignores the data and doesn’t send a handshake packet. Functions cannot issue a STALL or NAK packet in response to a setup packet.

Figure 30-35 Setup Stage Format

The optional Data Stage consists of one or multiple IN or OUT transfers. The setup request indicates the amount of data to be transmitted in this stage. If it exceeds the maximum packet size, data will be sent in multiple transfers each being the maximum packet length except for the last packet.

The data stage has two different scenarios depending upon the direction of data transfer.

496


Figure 30-36 Data Stage Format

- IN: When the host is ready to receive control data it issues an IN Token. If the function receives the IN token with an error e.g. the PID doesn't match the inverted PID bits, then it ignores the packet. If the token was received correctly, the device can either reply with a DATA packet containing the control data to be sent, a stall packet indicating the endpoint has had a error or a NAK packet indicating to the host that the endpoint is working, but temporary has no data to send.

- OUT: When the host needs to send the device a control data packet, it issues an OUT token followed by a data packet containing the control data as the payload. If any part of the OUT token or data packet is corrupt then the function ignores the packet. If the function's endpoint buffer was empty and it has clocked the data into the endpoint buffer it issues an ACK informing the host it has successfully received the data. If the endpoint buffer is not empty due to processing of the previous packet, then the function returns a NAK. However if the endpoint has had a error and its halt bit has been set, it returns a STALL.

Status Stage reports the status of the overall request and this once again varies due to direction of transfer. Status reporting is always performed by the function.

497


Figure 30-37 Status Stage Format

- IN: If the host sent IN token(s) during the data stage to receive data, then the host must acknowledge the successful reception of this data. This is done by the host sending an OUT token followed by a zero length data packet. The function can now report its status in the handshaking stage. An ACK indicates the function has completed the command is now ready to accept another command. If an error occurred during the processing of this command, then the function will issue a STALL. However if the function is still processing, it returns a NAK indicating to the host to repeat the status stage later.

OUT: If the host sent OUT token(s) during the data stage to transmit data, the function will acknowledge the successful reception of data by sending a zero length packet in response to an IN token. However if an error occurred, it should issue a STALL or if it is still busy processing data, it should issue a NAK asking the host to retry the status phase later.

498


30.5.1.2 INTERRUPT TRANSFER

An Interrupt request is queued by the device until the host polls the USB device asking for data. The below diagram shows the format of an Interrupt IN and Interrupt OUT transaction. In the USBC, endpoint1 support this transfer.

Figure 30-38 Interrupt Transfer Format

IN: The host will periodically poll the interrupt endpoint. This rate of polling is specified in the endpoint descriptor which is covered later. Each poll will involve the host sending an IN Token.

If an interrupt has been queued by the device, the function will send a data packet containing data relevant to the interrupt when it receives the IN Token. Upon successful reception at the host, the host will return an ACK. However if the data is corrupted, the host will return no status. If on the other hand a interrupt condition was not present when the host polled the interrupt endpoint with an IN token, then the function signals this state by sending a NAK. If an error has occurred on this endpoint, a STALL is sent in reply to the IN token instead.

OUT: When the host wants to send the device interrupt data, it issues an OUT token followed by a data packet containing the interrupt data. Also function will issues the responds to HOST base on different conditions.

499


30.5.1.3 BULK TRANSFER

Bulk transfers can be used for large burst data. Such examples could include a print-job sent to a printer or an image generated from a scanner. Bulk transfers provide error correction in the form of a CRC16 field on the data payload and error detection/re-transmission mechanisms ensuring data is transmitted and received without error. In the USBC, endpoint1 support this transfer.

Figure 30-39 Bulk Transfer Format

For full speed endpoints, the maximum bulk packet size is either 8, 16, 32 or 64 bytes long. For high speed endpoints, the maximum packet size can be up to 512 bytes long. If the data payload falls short of the maximum packet size, it doesn't need to be padded with zeros. A bulk transfer is considered complete when it has transferred the exact amount of data requested, transferred a packet less than the maximum endpoint size of transferred a zero-length packet.

The above diagram shows the format of a bulk IN and OUT transaction.

IN: When the host is ready to receive bulk data it issues an IN Token. If the function receives the IN token with an error, it ignores the packet. If the token was received correctly, the function can either reply with a DATA packet containing the bulk data to be sent, or a stall packet indicating the endpoint has had a error or a NAK packet indicating to the host that the endpoint is working, but temporary has no data to send.

500


OUT: When the host wants to send the function a bulk data packet, it issues an OUT token followed by a data packet containing the bulk data. If any part of the OUT token or data packet is corrupt then the function ignores the packet. If the function's endpoint buffer was empty and it has clocked the data into the endpoint buffer it issues an ACK informing the host it has successfully received the data. If the endpoint buffer is not empty due to processing a previous packet, then the function returns an NAK. However if the endpoint has had an error and it's halt bit has been set, it returns a STALL.

30.5.3 CONTROL TRANSACTIONS

EP0 is the control endpoint of the USBC. The software should handle all the Standard Device Requests that may be sent or received via EP0. The protocol for these device requests involves different numbers and types of transaction per transfer.

The Standard Device Requests required by a USB peripheral can be divided into three categories: Zero Data Requests, Write Requests, and Read Requests.

Zero Data Requests : all the information is included in the command.

Write Requests: the command will be followed by additional data.

Read Requests: the device is required to send data back to the host.

30.5.2.1 Zero Data Requests

Zero data requests have all their information included in the 8- byte command and requires no additional data to be transferred. For example: SET_ADDRESS, SET_CONFIGURATION, SET_INTERFACE, SET_FEATURE.

The E0CSR register is the USBC control transfer status register. The software should set the corresponding bit based on the different condition to handle the control transfer.

With all requests when USBC receives an EP0 interrupt, the sequence of events will begin.

The RxPktRdy bit (E0CSR) will also have been set. The 8- byte command should then be read from the Endpoint 0 FIFO, decoded and the appropriate action taken. For example if the command is SET_ADDRESS, the 7-bit address value contained in the command should be written to the FADDRR register.

501


The E0CSR register should then be written to set the ServicedRxPktRdy bit (indicating that the command has been read from the FIFO) and to set the DataEnd bit (indicating that no further data is expected for this request).

When the host moves to the status stage of the request, a second EP 0 interrupt will be generated to indicate that the request has completed. No further action is required from the software: the second interrupt is just a confirmation that the request completed successfully.

If the command is an unrecognized command, or for some other reason cannot be executed, then when it has been decoded, the E0CSR register should be written to set the ServicedRxPktRdy bit and to set the SendStall bit. When the host moves to the status stage of the request, the USBC will send a STALL to tell the host that the request was not executed. A second Endpoint 0 interrupt will be generated and the SentStall bit will be set.

If the host sends more data after the DataEnd bit has been set, then the USBC will send a STALL. An EP0 interrupt will be generated and the SentStall bit will be set.

30.5.2.2 WRITE REQUESTS

Write requests involve an additional packet (or packets) of data being sent from the host after the 8- byte command. For example: SET_DESCRIPTOR.

The E0CSR register is the USBC control transfer status register. The software should set the corresponding bit based on the different condition to handle the control transfer.

With all requests when USBC receives an EP0 interrupt, the sequence of events will begin. The RxPktRdy bit will also have been set. The 8- byte command should then be read from the Endpoint 0 FIFO and decoded. The E0CSR register should then be written to set the ServicedRxPktRdy bit (D6) (indicating that the command has been read from the FIFO) but in this case the DataEnd bit should not be set (indicating that more data is expected).

When a second EP0 interrupt is received, the E0CSR register should be read to check the endpoint status. The RxPktRdy bit should be set to indicate that a data packet has been received. The E0COUNTR register should then be read to determine the size of this data packet. The data packet can then be read from the Endpoint 0 FIFO.

If the length of the data associated with the request (indicated by the wLength field in the command) is greater than the maximum packet size for Endpoint 0, further data packets will be sent. In this case, E0CSR should be written to set the ServicedRxPktRdy bit, but the DataEnd bit should not be set.

502


When all the expected data packets have been received, the E0CSR register should be written to set the ServicedRxPktRdy bit and to set the DataEnd bit (indicating that no more data is expected).

When the host moves to the status stage of the request, another Endpoint 0 interrupt will be generated to indicate that the request has completed. No further action is required from the software, the interrupt is just a confirmation that the request completed successfully.

If the command is an unrecognized command, or for some other reason cannot be executed, then when it has been decoded, the E0CSR register should be written to set the ServicedRxPktRdy bit and to set the SendStall bit. When the host sends more data, the USBC will send a STALL to tell the host that the request was not executed. An Endpoint 0 interrupt will be generated and the SentStall bit will be set. If the host sends more data after the DataEnd has been set, then the USBC will send a STALL. An Endpoint 0 interrupt will be generated and the SentStall bit will be set.

30.5.2.3 READ REQUEST

Read requests have a packet (or packets) of data sent from the function to the host after the 8- byte command. For example: GET_CONFIGURATION, GET_STATUS, GET_INTERFACE, GET_DESCRIPTOR.

With all requests when USBC receives an EP0 interrupt, the sequence of events will begin.The RxPktRdy bit (E0CSR) will also have been set. The 8- byte command should then be read from the Endpoint 0 FIFO and decoded. The E0CSR register should then be written to set the ServicedRxPktRdy bit (indicating that the command has been read from the FIFO).

The data to be sent to the host should then be written to the EP0 FIFO. If the data to be sent is greater than the maximum packet size for EP0, only the maximum packet size should be written to the FIFO. The E0CSR register should then be written to set the TxPktRdy bit (indicating that there is a packet in the FIFO to be sent). When the packet has been sent to the host, another EP0 interrupt will be generated and the next data packet can be written to the FIFO. When the last data packet has been written to the FIFO, the E0CSR register should be written to set the TxPktRdy bit and to set the DataEnd bit (indicating that there is no more data after this packet).

When the host moves to the Status stage of the request, another EP0 interrupt will be generated to indicate that the request has completed. No further action is required from the software: the interrupt is just a confirmation that the request completed successfully.

If the command is an unrecognized command, or for some other reasons cannot be executed, then when it has been decoded, the E0CSR register

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should be written to set the ServicedRxPktRdy bit and to set the SendStall bit. When the host requests data, the USBC will send a STALL to tell the host that the request was not executed. An Endpoint 0 interrupt will be generated and the SentStall bit will be set.

If the host requests more data after DataEnd (E0CSR) has been set, then the USBC will send a STALL. An Endpoint 0 interrupt will be generated and the SentStall bit will be set.

30.5.2.4 ENDPOINT 0 STATES

The Endpoint 0 control needs three modes: IDLE, TX and RX corresponding to the different phases of the control transfer and the states Endpoint 0 enters for the different phases of the transfer.

The default mode on power-up or reset should be IDLE.

RxPktRdy (E0CSR.D0) becoming set when Endpoint 0 is in IDLE state indicates a new device request. Once the device request is unloaded from the FIFO, the USBC decodes the descriptor to find whether there is a Data phase and, if so, the direction of the Data phase of the control transfer (in order to set the FIFO direction).

Depending on the direction of the Data phase, Endpoint 0 goes into either TX state or RX state. If there is no Data phase, Endpoint 0 remains in IDLE state to accept the next device request.

The actions that the CPU needs to take at the different phases of the possible transfers (e.g. Loading the FIFO, Setting TxPktRdy) are indicated in the diagram on the following page. The USBC changes the FIFO direction depending on the direction of the Data phase independently of the CPU

30.5.2.5 ENDPOINT 0 SERVICE ROUTINE

The EP0 interrupts will generate when the following conditions happen:

When the core sets the RxPktRdy bit (E0CSR.D0) after a valid token has been received and data has been written to the FIFO.

When the core clears the TxPktRdy bit (E0CSR.D1) after the packet of data in the FIFO has been successfully transmitted to the host.

When the core sets the SentStall bit (E0CSR.D2) after a control transaction is ended due to a protocol violation.

When the core sets the SetupEnd bit (E0CSR.D4) because a control transfer has ended before DataEnd (E0CSR.D3) is set.

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Whenever the Endpoint 0 service routine is entered, the firmware must first check to see if the current control transfer has been ended due to either a STALL condition or a premature end of control transfer. If the control transfer ends due to a STALL condition, the SentStall bit would be set. If the control transfer ends due to a premature end of control transfer, the SetupEnd bitwould be set. In either case, the firmware should abort processing the current control transfer and set the state to IDLE.

Once the firmware has determined that the interrupt was not generated by an illegal bus state, the next action taken depends on the Endpoint state.

If Endpoint 0 is in IDLE state, the only valid reason an interrupt can be generated is as a result of the core receiving data from the USB bus. The service routine must check for this by testing the RxPktRdy bit. If this bit is set, then the core has received a SETUP packet. This must be unloaded from the FIFO and decoded to determine the action the core must take.

Depending on the command contained within the SETUP packet, Endpoint 0 will enter one of three states:

If the command is a single packet transaction (SET_ADDRESS, SET_INTERFACE etc.) without any data phase, the endpoint will remain in IDLE state.

If the command has an OUT data phase (SET_DESCRIPTOR etc.), the endpoint will enter RX state.

If the command has an IN data phase (GET_DESCRIPTOR etc.), the endpoint will enter TX state.

If the endpoint is in TX state, the interrupt indicates that the core has received an IN token and data from the FIFO has been sent. The firmware must respond to this either by placing more data in the FIFO if the host is still expecting more data2 or by setting the DataEnd bit to indicate that the data phase is complete. Once the data phase of the transaction has been completed,

Endpoint 0 should be returned to IDLE state to await the next control transaction. If the endpoint is in RX state, the interrupt indicates that a data packet has been received. The firmware must respond by unloading the received data from the FIFO. The firmware must then determine whether it has received all of the expected data2. If it has, the firmware should set the DataEnd bit and return Endpoint 0 to IDLE state. If more data is expected, the firmware should set the ServicedRxPktRdy bit (E0CSR.D6) to indicate that it has read the data in the FIFO and leave the endpoint in RX state.

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30.5.3 BULK TRANSACTION

30.5.3.1 BULKIN TRANSACTION

Bulk IN transaction is used to transfer non-period data from the function controller to the host.

The TxCSR register is the USBC Tx transfer status register. The software should set the corresponding bit based on the different condition to handle the transfer to host.

When the AutoSet bit is enabled, the TxPktRdy bit will be automatically set when a packet of TxMaxP bytes has been loaded into the FIFO.

SETUP

Firstly, the TXPSZR register must be written with the maximum packet size for the endpoint in configuring a Tx endpoint for Bulk transactions. This value should be the same as the Standard Endpoint Descriptor’s wMaxPacketSize field for the endpoint. The relevant interrupt enable bit in the IntrTxE register should be set to "1" if the interrupt is required for this endpoint.

The TxCSR register should be set as shown:

- Bit15: AutoSet if set to 1 the AutoSet feature enable, otherwise the TxPktRdy bit should set manually.

- Bit13 Mode set to 1 to ensure the FIFO is enabled Tx.

- Bit11 FrcDataTog set to 0 to allow normal data toggle operation.

The lower byte of TxCSR should be written to set ClrDataTog bit, when the endpoint is first configured. This will ensure that the data toggle starts in the correct state. If there are any data packets in the FIFO, they should be flushed by setting the FlushFIFO bit.

OPERATION

When data is to be transferred over a Bulk IN pipe, a data packet needs to be loaded into the FIFO and the TxCSR register written to set the TxPktRdy bit. When the packet has been sent, the TxPktRdy bit will be cleared by the USBC and an interrupt generated so that the next packet can be loaded into the FIFO.

The packet size must not exceed the size specified by the bottom 11 bits of the TXPSZR register. This part of the register defines the payload for transfers over the USB and is required by the USB Specification to be either 8,16,32,64 bit for Full/High-speed or 512 bytes for High-speed only. If more than this amount of data is to be transferred, this needs to be sent as multiple USB

506


packets which should all be TXPSZR[10:0] in size, except for the last packet which holds the residue.

The host may determine that all the data for a transfer has been sent by knowing the total amount of data that is expected.

Alternatively it may infer all the data have been sent when it receives a packet which is smaller than the stated payload. In this case, if the total size of the data is a multiple of this payload, it will be necessary for the function to send a null packet after all the data has been sent. This is done by setting TxPktRdy when the next interrupt is received, without loading any data into the FIFO.

ERROR HANDLING

Software can set the SendStall bit (TxCSR) to shut down the Bulk IN pipe. After that, when the USBC receives the next IN token, it will send a STALL to the host, and set the SentStall bit, then generate an interrupt. When software receives an interrupt with the SentStall bit set, it should clear the SentStall bit. It should however leave the SendStall bit set until it is ready to reenable the Bulk IN pipe. When a pipe is re-enabled, the data toggle sequence should be restarted by setting the ClrDataTog bit in the TxCSR register.

30.5.3.2 BULKOUT TRANSACTION

Bulk OUT transaction is used to transfer non-period data from the host to the function controller.

The RxCSR register is the USBC Rx transfer status register. The software should set the corresponding bit based on the different condition to handle the transfer to host.

When the AutoClear bit is enabled, the RxPktRdy bit will be automatically clear when a packet of RxMaxP bytes has been unloaded from the FIFO.

SETUP

Firstly, the RxMaxP register must be written with the maximum packet size for the endpoint in configuring a Rx endpoint for Bulk transactions. This value should be the same as the Standard Endpoint Descriptor’s wMaxPacketSize field for the endpoint. The relevant interrupt enable bit in the IntrRxE register should be set to "1" if the interrupt is required for this endpoint.

The RxCSR register should be set as shown:

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- Bit15: AutoClear if set to 1 the AutoClear feature enable, otherwise the RxPktRdy bit should set manually.

- Bit12 DisNyet set to 0 to allow normal PING flow control.

The lower byte of RxCSR should be written to set ClrDataTog bit, when the endpoint is first configured. This will ensure that the data toggle starts in the correct state. If there are any data packets in the FIFO, they should be flushed by setting the FlushFIFO bit.

OPERATION

The RxPktRdy bit is set by USBC and an interrupt is generated when a data packet is received by a Bulk Rx endpoint. The software should read the RxCount register for the endpoint to determine the size of the data packet. And then the data packet should be unloaded from the FIFO, then the RxPktP bit should be cleared automatically or manually.

The packets received must not exceed the size specified by the bottom 11 bits of the RxMaxP register. This part of the register defines the payload for transfers over the USB and is required by the USB Specification to be either 8,16,32,64 bit for Full/High-speed or 512 bytes for High-speed only.

When a block of data larger than wMaxPacketSize needs to be sent to the function, it will be sent as multiple packets. All the packets will be wMaxPacketSize in size, except he last packet which will contain the residue. The software may use an application specific method of determining the total size of the block and hence when the last packet has been received. Alternatively it may infer that the entire block has been received when it receives a packet which is less than the amount. If the total size of the data block is a multiple of the wMaxPacketSize, a null data packet will be sent after the data to signify that the transfer is finish.

ERROR HANDLING

Software can set the SendStall bit (RxCSR) to shut down the Bulk OUT pipe. After that, when the USBC receives the next packet, it will send a STALL to the host, and set the SentStall bit, then generates an interrupt. When software receives an interrupt with the SentStall bit set, it should clear the SentStall bit. It should however leave the SendStall bit set until it is ready to re-enable the Bulk IN pipe. When a pipe is re-enabled, the data toggle sequence should be restarted by setting the ClrDataTog bit in the RxCSR register.

30.5.4 INTERRUPT TRANSACTION

The Interrupt IN transaction used the same protocol as a Bulk IN transaction and can be used the same way. Similarly, an Interrupt OUT transaction used

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almost the same protocol as a Bulk OUT transaction and can be used the same way.

The USB Specification defines Interrupt transaction support continuous toggle of the data toggle bit while Bulk transaction does not support. This feature is enabled by setting the FrcDataTog bit in the TxCSR register. When this bit is set to "1", the USBC will consider the packet as having been successfully sent and toggle the data bit for the endpoint, regardless of whether an ACK was received from the host.

Interrupt endpoint do not support PING flow control. This means that the USBC should never respond with a NYET handshake, only ACK/NAK/STALL. To ensure this, the DisNyet bit in the RxCSR register should be set to "1" to disable the transmission of NYET handshakes in High-speed mode.

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Section 31 Ports Module

31.1 Introduction

Many of the pins associated with the external interface may be used for several different functions. Their primary function is to provide an external interface to access off-chip resources. When not used for their primary functions, many of the pins may be used as general purpose digital input/output (I/O) pins. In some cases, the pin function is set by the operating mode, and the alternate pin functions are not supported.

To facilitate the general purpose digital I/O function, these pins are grouped into 8-bit ports. Each port has registers that configure the pins for the desired function, monitor the pins, and control the pins within the ports.

PORTA A[23:16]/PA[7:0]

PORTB A[15:8]/PB[7:0]

PORTC A[7:0]/PC[7:0]

PORTD D[31:24]/PD[7:0]

PORTF RW,EB[1:0],A[25:24],OE,

PORTE D[23:16]/PE[7:0]

CS[1:0]/PF[7:0]

Figure 31-1 Ports Module Block Diagram

31.2 Signals

See Table 31-2 in 31.4 Functional Description for signal location and naming convention.

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The ports programming model consists of these registers:

The port output data registers (PORTx) store the data to be driven on the corresponding port pins when the pins are configured for digital output.

The port data direction registers (DDRx) control the direction of the port pin drivers when the pins are configured for digital I/O.

Port pin data/set data registers (PORTxP/SETx):

- Reflect the current state of the port pins

- Allow for setting individual bits in PORTx

The port clear output data registers (CLRx) allow for clearing individual bits in PORTx.

The port pin assignment registers (PAPAR, PBPAR, PCPAR, PDEPAR, PFPAR) control the function of each pin of the A, B, C, D, E and F ports.

In emulation mode, accesses to the port registers are ignored and the port access goes external so that emulation hardware can satisfy the port access request. The cycle termination is always provided by the port logic, even in emulation mode.

All port registers are word-, half-word, and byte-accessible and are grouped to allow coherent access to port data register groups. Writing to reserved bits in the port registers has no effect and reading returns 0s.

The I/O ports have a base address of 0x00C0_0000.

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31.3.1 Memory Map

Table 31-1 I/O Port Module Memory Map

Address Bits 31-24 Bits 23-16 Bits 15-8 Bits 7-0 Access(55

0x00c0_0000

)

PORTA PORTB PORTC PORTD S/U

0x00c0_0004 PORTE PORTF Reversed(56 Reversed(2) ) S/U

0x00c0_0008 Reserved(2) S/U

0x00c0_000c DDRA DDRB DDRC DDRD S/U

0x00c0_0010 DDRE DDRF Reversed(2) S/U

0x00c0_0014 Reserved(2) S/U

0x00c0_0018 PORTAP/SETA PORTBP/SETB PORTCP/SET

C

PORTDP/SET

D S/U

0x00c0_001c PORTEP/SETE PORTFP/SETF Reversed(2) S/U

0x00c0_0020 Reversed(2) S/U

0x00c0_0024 CLRA CLRB CLRC CLRD S/U

0x00c0_0028 CLRE CLRF Reversed(2) S/U

0x00c0_002c Reversed(2) S/U

0x00c0_0030 PAPAR PBPAR PCPAR PDPAR S/U

0x00c0_0034 PEPAR PFPAR Reversed(2) S/U

0x00c0_0038-

0x00c0_003c Reversed(2) S/U



error.

56Writes have no effect, reads return 0s, and the access terminates without a transfer error exception.

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This subsection provides a description of the I/O port registers.

31.3.2.1 Port Output Data Registers

The port output data registers (PORTx) store the data to be driven on the corresponding port x pins when the pins are configured for digital output. Reading PORTx returns the current value in the register, not the port x pin values.

The SETx and CLRx registers also affect the PORTx register bits. To set bits in PORTx, write 1s to the corresponding bits in PORTxP/SETx. To clear bits in PORTx, write 0s to the corresponding bits in CLRx.

PORTx are read/write registers when not in emulation mode. Reset sets PORTx.

Address : 0x00c0_0000 - PORTA Address : 0x00c0_0001 - PORTB Address : 0x00c0_0002 - PORTC Address : 0x00c0_0003 - PORTD Address : 0x00c0_0004 - PORTE Address : 0x00c0_0005 - PORTF

7 6 5 4 3 2 1 0

R PORTx7 PORTx6 PORTx5 PORTx4 PORTx3 PORTx2 PORTx1 PORTx0

W

RESET: 1 1 1 1 1 1 1 1

Figure 31-2 Port Output Data Registers (PORTx)

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31.3.2.2 Port Data Direction Registers

A port data direction registers (DDRx) control the direction of the port x pin drivers when the pins are configured for digital I/O. Setting any bit in DDRx configures the corresponding port x pin as an output. Clearing any bit in DDRx configures the corresponding pin as an input. When a pin is not configured for digital I/O, its corresponding data direction bit has no effect.

DDRx are read/write registers when not in emulation mode. Reset clears DDRx.

Address : 0x00c0_000c - DDRA Address : 0x00c0_000d - DDRB Address : 0x00c0_000e - DDRC Address : 0x00c0_000f - DDRD Address : 0x00c0_0010 - DDRE Address : 0x00c0_0011 - DDRF

7 6 5 4 3 2 1 0

R DDRx7 DDRx6 DDRx5 DDRx4 DDRx3 DDRx2 DDRx1 DDRx0

W

RESET: 0 0 0 0 0 0 0 0

Figure 31-3 Port Data Direction Registers (DDRx)

DDRx[7:0] — Port x Data Direction Bits 1= Pin configured as output 0= Pin configured as input

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31.3.2.3 Port Pin Data/Set Data Registers

Reading a Port Pin Data/Set Data Register (PORTxP/SETx) returns the current state of the port x pins.

Writing 1s to PORTxP/SETx sets the corresponding bits in PORTx. Writing 0s has no effect.

PORTxP/SETx are read/write registers when not in emulation mode.

Address : 0x00c0_0018 - PORTAP/SETA Address : 0x00c0_0019 - PORTBP/SETB Address : 0x00c0_001a - PORTCP/SETC Address : 0x00c0_001b - PORTDP/SETD Address : 0x00c0_001c - PORTEP/SETE Address : 0x00c0_001d - PORTFP/SETF

7 6 5 4 3 2 1 0

R PORTx7 PORTx6 PORTx5 PORTx4 PORTx3 PORTx2 PORTx1 PORTx0

W



Figure 31-4 Port Pin Data/Set Data Registers (PORTxP/SETx)

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31.3.2.4 Port Clear Output Data Registers

Writing 0s to a Port Clear Output Data Register (CLRx) clears the corresponding bits in PORTx. Writing 1s has no effect. Reading CLRx returns 0s.

CLRx are read/write registers when not in emulation mode.

Address : 0x00c0_0024 - CLRA Address : 0x00c0_0025 - CLRB Address : 0x00c0_0026 - CLRC Address : 0x00c0_0027 - CLRD Address : 0x00c0_0028 - CLRE Address : 0x00c0_0029 - CLRF

7 6 5 4 3 2 1 0

R 0 0 0 0 0 0 0 0

W CLRx7 CLRx6 CLRx5 CLRx4 CLRx3 CLRx2 CLRx1 CLRx0

RESET: 0 0 0 0 0 0 0 0

Figure 31-5 Port Clear Output Data Registers (CLRx)

516


31.3.2.5 Port A Pin Assignment Register

The Port A Pin Assignment Register controls the pin function of ports A.


7 6 5 4 3 2 1 0

R PAPA7 PAPA6 PAPA5 PAPA4 PAPA3 PAPA2 PAPA1 PAPA0

W

RESET: 0 0 0 0 0 0 0 0

Figure 31-6 Port A Pin Assignment Register (PAPAR)

PAPA[7:0] — Port A Pin Assignment Bits 1= Port A pins configured for digital I/O 0= Port A pins configured for primary function

31.3.2.6 Port B Pin Assignment Register

The Port B Pin Assignment Register controls the pin function of ports B.


7 6 5 4 3 2 1 0

R PBPA7 PBPA6 PBPA5 PBPA4 PBPA3 PBPA2 PBPA1 PBPA0

W

RESET: 0 0 0 0 0 0 0 0

Figure 31-7 Port B Pin Assignment Register (PBPAR)

PBPA[7:0] — Port B Pin Assignment Bits 1= Port B pins configured for digital I/O 0= Port B pins configured for primary function

517


31.3.2.7 Port C Pin Assignment Register

The Port C Pin Assignment Register controls the pin function of ports B.


7 6 5 4 3 2 1 0

R PCPA7 PCPA6 PCPA5 PCPA4 PCPA3 PCPA2 PCPA1 PCPA0

W

RESET: 0 0 0 0 0 0 0 0

Figure 31-8 Port B Pin Assignment Register (PCPAR)

PCPA[7:0] — Port C Pin Assignment Bits 1= Port C pins configured for digital I/O 0= Port C pins configured for primary function

518


31.3.2.8 Port D Pin Assignment Register

The Port D Pin Assignment Register controls the pin function of ports D.


7 6 5 4 3 2 1 0

R PDPA

0 0 0 0 0 0 0

W

RESET: 0 0 0 0 0 0 0 0

Figure 31-9 Port D and E Pin Assignment Register (PDPAR)

PDPA— Port D Pin Assignment Bit 1= Port D pins configured for digital I/O 0= Port D pins configured for primary function

519


31.3.2.9 Port E Pin Assignment Register

The Port E Pin Assignment Register controls the pin function of ports E.


7 6 5 4 3 2 1 0

R PEPA

0 0 0 0 0 0 0

W

RESET: 0 0 0 0 0 0 0 0

Figure 31-10 Port D and E Pin Assignment Register (PEPAR)

PEPA— Port E Pin Assignment Bit 1= Port E pins configured for digital I/O 0= Port E pins configured for primary function

520


31.3.2.10 Port F Pin Assignment Register

The Port F Pin Assignment Register controls the pin function of ports F.


7 6 5 4 3 2 1 0

R PFPA7 PFPA6 PFPA5 PFPA4 PFPA3 PFPA2 PFPA1 PFPA0

W

RESET: 0 0 0 0 0 0 0 0

Figure 31-11 Port A Pin Assignment Register (PAPAR)

PFPA[7:0] — Port F Pin Assignment Bits 1= Port F pins configured for digital I/O 0= Port F pins configured for primary function

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Every digital I/O pin is individually configurable as an input or an output via a data direction register (DDRx).

Every port has an output data register (PORTx) and a pin data register (PORTxP/SETx) to monitor and control the state of its pins. Data written to PORTx is stored and then driven to the corresponding PORTx pins configured as outputs.

Reading PORTx returns the current state of the register regardless of the state of the corresponding pins.

Reading PORTxP returns the current state of the corresponding pins, regardless of whether the pins are input or output.

Every port has a set register (PORTxP/SETx) and a clear register (CLRx) for setting or clearing individual bits in PORTx.

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31.4.1 Pin Functions

Ports A-F Supported Pin Functions Pin Port Primary Function GPIO function

A[23] A A[23] (O)(PAPAR7=0) PA[7](I/O)(PAPAR7=1)








A[15] B A[15] (O)(PBPAR7=0) PB[7](I/O)(PBPAR7=1)








A[7] C A[7] (O)(PCPAR7=0) PC[7](I/O)(PCPAR7=1)








D[31:24] D D[31:24](I/O) (PDPAR = 0) PD[7:0] (I/O) (PDPAR =1)

D[23:16] E D[23:16]I/O) (PEPAR = 0) PE[7:0] (I/O) (PEPAR =1)

RW F RW(I/O)(PFPAR7=0) PF[7](I/O) ( PFPAR7=1)

EB[1] F EB[1](I/O)(PFPAR6=0) PF[6](I/O) ( PFPAR6=1)

EB[0] F EB[0](I/O)(PFPAR5=0) PF[5](I/O) ( PFPAR5=1)

A[25] F A[25](I/O)(PFPAR4=0) PF[4](I/O) ( PFPAR4=1)

523


A[24] F A[24](I/O)(PFPAR3=0) PF[3](I/O) ( PFPAR3=1)

OE F OE(I/O)(PFPAR2=0) PF[2](I/O) ( PFPAR2=1)

CS[1] F CS[1](I/O)(PFPAR1=0) PF[1](I/O) ( PFPAR1=1)

CS[0] F CS[0](I/O)(PFPAR0=0) PF[0](I/O) ( PFPAR0=1)

31.4.2 Port Digital I/O Timing

Input data on all pins configured as digital I/O is synchronized to the rising edge of CLKOUT. See Figure 31-12.

Digital Input Timing

Data written to PORTx of any pin configured as a digital output is immediately driven to its respective pin. See Figure 31-13.

Digital Output Timing

31.5 Interrupts

The ports module does not generate interrupt requests.

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Section 32 True Random Number Generator (TRNG)

32.1 Introduction

TRNG module is used to generate true random numbers.


The TRNG controller is not affected by low-power mode. CPU can stop TRNG by setting the corresponding module stop bit in Clock Module.

32.3 Block Diagram

TRNG module have one clock input (ipg_clk) and one data output (dout). In TF32A09 chip, dout signal will be shifted and stored in TRNG Data Register, when the interrupt enable (TRNGIE) bit is set, TRNG will generate interrupt to CPU, and DR register will store 32-bit random number.

DIVCRipg_clk

TRNG

TRNG_CLK

TRNG_ENdout

DataShifterRegister

DR

ips_rdata

trng_int

Figure 32-1 TRNG Block Diagram

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Table 32-1 shows the TRNG register memory map.

Figure 32-1 Register Memory Map


0x00cd_0000

TRNG Control Register (TCR) S

0x00cd_0004 TRNG Data Register (TDR) S


32.5.1 TRNG Control Register (TCR)

TCR register contains the control bits for TRNG module.




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Address : 0x00cd_0000 through 0x00cd_0003

31 30 29 28 27 26 25 24

R 0 0 0 0 0 0 0 0

W

RESET: 0 0 0 0 0 0 0 0

23 22 21 20 19 18 17 16

R 0 0 0 0 0 0 0 0

W

RESET: 0 0 0 0 0 0 0 1

15 14 13 12 11 10 9 8

R 0 0 0 0 TRNG_INT TRNGCLR TRNGIE TRNGEN

W

RESET: 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

R DIVCR[7:0]

W

RESET: 0 0 0 0 0 0 0 0


Figure 32-2 TRNG Control Register (TCR)

TRNGEN — TRNG Enable Bit This bit enables TRNG function.

1= enable 0= disable

TRNGIE — TRNG Interrupt Enable Bit This bit enables TRNG interrupt signal to INTC.

1= enable interrupt 0= disable interrupt

TRNGCLR — Clear TRNG Interrupt This bit clears the interrupt when write "1" to it, read TRNGCLR always return "0".

1= clear interrupt 0= has no effect

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TRNG_INT — TRNG Interrupt This bit will be set when 32-bit TRNG data stored in DR.

1= 32-bit TRNG data is ready 0= no 32-bit TRNG data in DR

DIVCR[7:0] — TRNG Divider Counter To determine the divider for ipg_clk which used to generate the TRNG_CLK, the TRNG_CLK is calculated as the following formula:

32.5.2 FTRNG_CLK=Fsys/(2*DIVCR[7:0])

The frequency of TRNG_CLK should be below 20MHz.

32.5.2 TRNG Data Register (TDR)

Address : 0x00cd_0004 through 0x00cd_0007

31 30 29 28 27 26 25 24

R DR[31:24]

W

RESET: 0 0 0 0 0 0 0 0

23 22 21 20 19 18 17 16

R DR[23:16]

W

RESET: 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8

R DR[15:8]

W

RESET: 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

R DR[7:0]

W

RESET: 0 0 0 0 0 0 0 0


Figure 32-3 TRNG Data Register (TDR)

TDR is a 32-bit readable and writable register.The intermediate and final results are stored in it.

528



The operation of TRNG module is following:

1. Set TRNGEN bit in TCR "1".

2. When TRNG_INT bit in TCR is set, get 32-bit random number from TDR.

529


Appendix A Preliminary Electrical Characteristic

A.1 General

This section provides electrical parametric and electrical ratings for the TF32A09 microcontroller unit.

The electrical specifications are preliminary and are from previous designs or design simulations. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle; however, for production silicon these specification will be met. Finalized specifications will be published after complete characterization and device qualifications have been completed.

530


A.2 Absolute Maximum Ratings

Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it. See Table A-1.

The MCU contains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in the table. Connect unused inputs to the appropriate voltage level, either VSSH and VDDH. This device is not guaranteed to operate properly at the maximum ratings. Refer to A.4 DC Electrical Specifications for guaranteed operating conditions.

Table A-1 Absolute Maximum Ratings

Num Rating Symbol Value Unit

1 Supply Voltage VDD33 -0.5 to +4.6 V

2 Input Voltage59 VIN -0.5 to +6.0 V

3 Instantaneous maximum current single pin limit

(applies to all pins) ID 25 mA

4 Operating temperature range TOPT 0 to +70 OC

5 Storage temperature range TSTG -25 to +125 OC

59Input must be current limited to the value specified. To determine the value of the required

current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then

use the larger of the two values.

531


A.3 Electrostatic Discharge (ESD) Protection

Table A-2 ESD Protection Characteristics

Parameter60,61 Symbol Value Units

ESD target for human body model HBM 2000 V

ESD target for machine model MM 200 V

HBM circuit description RSeries 1500 W

C 100 pF

MM circuit description RSeries 0 W

C 200 pF

Number of pulses per pin (HBM) Positive pulses Negative pulses

— 3 3

—

Number of pulses per pin (HBM) Positive pulses Negative pulses

— 3 3

—

Interval of pulses — 1 Sec

60All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade

Integrated Circuits. 61A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the

device specification requirements. Complete DC parametric and functional testing shall be

performed per applicable device specification at room temperature followed by hot temperature,

unless specified otherwise in the device specification.

532


A.4 DC Electrical Specifications

Table A-3 DC Electrical Specifications

Parameter Symbol Min Typical Max Unit

Supply Voltage VDDH 2.97 3.3 3.63 V

Input High Voltage VIH 2.0 — 5.5 V

Input Low Voltage VIL -0.3 — 0.8 V

Threshold point VT 1.45 1.58 1.74 V

Schmitt trig. Low to High Threshold point VT+ 1.44 1.50 1.56 V

Schmitt trig.High to Low Threshold point VT- 0.89 0.94 0.99 V

Output High Voltage VOH 2.4 — — V

Output Low Voltage VOL — — 0.4 V

Input Leakage Current IIN — — +10 µA

Tri-state output Leakage Current IOZ — — +10 µA

Pull-up Resistor RPU 39 65 116 kΩ

Low level output currernt @ VOL=0.4V IOL 9.4 15.9 19.8 mA

High level output current @ VOH=2.4V IOH 11.2 23.8 38.3 mA

Supply current, USB Key Mode62

IDDH

Normal Mode

Wait Mode

Doze Mode

Stop Mode

OSC and PLL enabled

OSC enabled, PLL disabled

OSC and PLL disabled (Not available)

— — —

— — —

90 30 25

2 1

200

— — —

— — —

mA

mA

mA

mA

mA

µA

62Current measured at fSYS = 60 MHz derived from 12.00 MHz crystal and PLL, all modules active,

and default drive strength with matching load.

533


Supply current, SD Card Mode63

IDDH

Normal Mode

Wait Mode

Doze Mode

Stop Mode

OSC and PLL enabled



— — —

— — —

50 30 25

2 1

200

— — —

— — —

mA

mA

mA

mA

mA

µA

Supply current, Smart Card Mode64

IDDH

Normal Mode

Wait Mode

Doze Mode

Stop Mode

OSC and PLL enabled



— — —

— — —

50 30 25

2 1

200

— — —

— — —

mA

mA

mA

mA

mA

µA

63Current measured at fSYS = 60 MHz derived from 12.00 MHz crystal and PLL, all modules except

USB active, and default drive strength with matching load. 64Current measured at fSYS = 60 MHz derived from internal oscillator and PLL, all modules except

USB and NANDFLASH Interface active, and default drive strength with matching load.

534


A.5 VD Electrical Specifications

Table A-4 VD Electrical Specifications

Parameter Symbol Min Max Unit

Low-Voltage Detect Trip Voltage(VDD falling) (LVCTR=0)

VLDV 2.63 2.66 V

Low-Voltage Detect Trip Voltage(VDD falling) (LVCTR=1)

VLDV 2.80 2.83 V

Low-Voltage Detect Hysteresis(VDD rising) VLDV 60 100 mV

High-Voltage Detect Trip Voltage(VDD rising) (HVCTR=0)

VHDV 3.89 3.91 V

High-Voltage Detect Trip Voltage(VDD rising) (HVCTR=1)

VHDV 3.73 3.75 V

High-Voltage Detect Hysteresis(VDD falling)

VLDV 60 100 mV

535


A.6 External Interface Timing Characteristics

Table A-5 External Interface Timing Characteristics

(VDD = 2.97V to 3.63 V, VSS = 0V, TA = TL to TH)

No. Characteristic(65),(66 Symbol ) Min Max Unit

1 CLKOUT period tcyc 16 - ns

2 CLKOUT low pulse width tCLW 0.5tcyc-1 - ns

3 CLKOUT high pulse width tCHW 0.5tcyc-1 ns

4 All rise times tCR - 2 ns

5 All fall times tCF - 2 ns

6 CLKOUT high to A[22:0],CS[1:0], FCE,FALE, FCLE, R/W valid(67 tCHAV )

- 4 ns

7 CLKOUT high to A[22:0], CS[1:0], FCE,FALE,FCLE R/W invalid

tCHAI 0 - ns

8 CLKOUT high to OE,EB,FOE,FWE asserted(3) tCHOEA 0.5tcyc 0.5tcyc+4 ns

9 CLKOUT high to OE,EB read, FOE negated tCHOEN 0 4 ns

9A CLKOUT low to FWE, EB write negated tCLEN 0.5tcyc 0.5tcyc +3 ns

10 CLKOUT low to data-out valid write tCLDOVW - 4 ns

11 CLKOUT high to data-out invalid write/show tCHDOIW 2 - ns

12 Data-in valid to CLKOUT high read tDIVCH 9 - ns

65All AC timing is shown with respect to 50% VDD levels, unless otherwise noted. 66Timing is not guaranteed during the clock cycle of mode and/or setup changes (for example,

changing pin function between GPIO and primary function, changing GPIO between input/output

functions, changing control registers that affect pin functions).

67This parameter is characterized before qualification rather than 100% tested.

536


Appendix B Abbreviations And Terms

Table B-1 Abbreviations And Terms Abbreviations Description

BCH Bose-Chaudhuri-Hocquenghem correction algorithm

CCM Chip configuration module

CPU Central processor unit

DES Data encryption standard

DMAC Direct memory access controller

ECC Error correction code

EPORT Edge port module

FIFO First in first out

I2C Inter integrated circuit

INTC Interrupt controller

KPP Keypad port

MIM Memory integration module

MPU Memory protection unit

PIT Programmable interrupt timer

PLL Phase-lock loop

POR Power-on reset

PWM Pulse width modulator

ROM Read only memory

SCI Serial communication interface

SPI Serial peripheral interface

SRAM Static random access memory

TRNG True random number generator

USBC USB2.0 controller

PHY USB Physical Device, A piece of hardware on the end of a USB cable that performs some useful end user function.

USI Universal serial interface(iso7816)

537


WDT Watch dog timer

USI Universal serial interface(iso7816)

VR Voltage Regulator

VD Voltage detector

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