© 2009 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

Phys. Status Solidi A 206, No. 1, 179–182 (2009) / DOI 10.1002/pssa.200824338 p s sapplications and materials science

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ZnO nanowire field-effect transistor as a UV photodetector; optimization for maximum sensitivity

Woong Kim* and Kyo Seon Chu

Department of Materials Science and Engineering, Korea University, Seoul 136-713, South Korea

Received 6 August 2008, revised 19 August 2008, accepted 22 August 2008

Published online 23 October 2008

PACS 73.63.Nm, 85.30.De, 85.30.Tv

* Corresponding author: e-mail woongkim@korea.ac.kr

© 2009 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

1 Introduction ZnO is a direct band gap semicon-ducting material (Eg ~ 3.4 eV) with a high exciton binding energy (60 meV). It is an environmentally friendly, natu-rally abundant, and inexpensive material. Owing to these properties, a variety of potential applications such as light-emitting diodes, laser diodes, photodetectors, transparent field-effect transistors (FETs), and chemical and biological sensors have been explored [1–5]. Moreover, synthesis of ZnO in nanoscale could lead to improvement of device performance because nanomaterials have unique properties arising from the quantum confinement effect and high sur-face-to-volume ratio [6–9]. For example, a ZnO nanowire (NW) based FET can detect ultraviolet (UV) light with high sensitivity owing to high surface area [10, 11]. How-ever, study of the electrical characteristics of FETs upon UV illumination has not been fully explored. In this work, we investigate bias and gate voltage effects on the UV photodetection and demonstrate that both voltages have

significant influence on the sensitivity of the FET photo-detector. Our study reveals that, for maximum sensitivity, there is an optimum point of operation in terms of bias and gate voltages. 2 Experimental ZnO nanowires were synthesized on sapphire substrates using a carbothermal process in a hori-zontal tube furnace [12]. They were configured as FETs as follows. A sapphire substrate with nanowires was put in a vial containing 2-propanol. The nanowires were sonicated off the substrate and dispersed in the solvent. The solvent containing dispersed nanowires was drop-dried on a SiO2/Si substrate, where the oxide was thermally grown (tox ~ 115 nm). Highly doped silicon was used as a back gate for the FET. A pattern of source and drain electrodes was defined by photolithography. 75 nm of Ti and 45 nm of Au were e-beam evaporated, following a brief O2 plasma treatment to remove photoresist residues on the

We demonstrate that drain–source (Vds) and gate–source

voltages (Vgs) of a zinc oxide nanowire (ZnO NW) field-effect

transistor (FET) can be optimized to increase UV photodetec-

tion sensitivity. Investigation of the relationship between the

sensitivity and the applied voltages reveals that the photo-

detector is most sensitive when it operates (1) with highest

on/off current ratio and (2) at the “bottom” of the subthreshold

swing region. Our results can be broadly applied to maximize

sensitivity of other FET-based sensors and detectors.

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180 Woong Kim and Kyo Seon Chu: ZnO nanowire field-effect transistor as a UV photodetector

© 2009 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim www.pss-a.com

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P++ Si

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Figure 1 (online colour at: www.pss-a.com) (a) A SEM image

and (b) a schematic of a ZnO NW FET; the diameter of the

nanowire (d), channel length (Lch), and oxide thickness (tox) are

~120 nm, 8.7 µm, and 115 nm, respectively.

ZnO surface. The devices were annealed at 200 °C in Ar for 5 min. This annealing process could improve the con-tact quality between metal and nanowires. A scanning elec-tron microscope (SEM) image and a schematic diagram show the geometry of a ZnO NW FET. The diameter of the nanowire and the channel length of this device were ~120 nm and ~8.7 μm, respectively (Fig. 1a, b).

3 Results and discussion Electrical properties of the ZnO NW FET were characterized. The linearity of current versus bias voltage characteristics indicated that the nanowire was nearly ohmically contacted by source and drain metal electrodes [13]. Current versus gate voltage characteristics showed that the ZnO NW is an n-type semi-conductor (Fig. 2a). The NW transistor was depleted when the gate voltage was below the threshold voltage (Vgs < Vth). This n-type behavior has been attributed to native defects such as oxygen vacancies or zinc interstitials [14]. The ZnO NW FET was an enhancement-mode transistor with threshold voltage (Vth) of ~1.5 V. The field-effect mobility (μFE) and the subthreshold swing (S) of the device were ~30 cm2/V s and ~400 mV/dec, respectively. Upon UV il-

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Figure 2 (online colour at: www.pss-a.com) (a) Current versus

gate voltage (Ids–Vgs) characteristic curves at various drain–

source voltages (Vds). (b) Ids–Vgs characteristics under UV illumi-

nation and under darkness when Vds = 1 V, and (c) when

Vds = 1 mV. Dashed lines were used as a guide line. (d) Linear re-

lationship between photocurrent/dark current ratio (Iph/Idark) and

initial on/off current ratio (Ion/Ioff) of the ZnO NW FET.

lumination (with a hand-held UV lamp, λ = 365 nm and P = 0.47 mW/cm2), electrical characteristics of the transis-tor changed from a semiconducting state to a metal-like state with little gate dependency (Fig. 2b). This can be at-tributed to the increase in photo-excited carrier concentra-tion to a degenerate level. The metal-like behavior of ZnO NWs during UV illumination was also observed via tem-perature-dependent photoconductivity measurement [15]. The UV photoresponse was highly dependent on the initial state of the FET-based photodetector, which could be manipulated by changing both the bias and the gate voltages. For example, the on/off current ratio of the tran-sistor can be increased by increasing the drain bias voltage (Fig. 2a). We observed that the photodetector response was associated with the initial on/off ratio of the transistor.

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Figure 3 (online colour at: www.pss-a.com) (a)

Drain–source current measured as a function of

time (Ids – t) while the light was on and off when

Vgs = 5 V, 0 V, and –5 V (Vds = 1 V). (b) Expo-

nential decay characteristics after the light is off

when Vgs = 5 V, 0 V, and –5 V (Vds = 1 V).

Markers indicate experimental data and the lines

show fitting curves.

Phys. Status Solidi A 206, No. 1 (2009) 181

www.pss-a.com © 2009 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

Original

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When the on/off ratio was ~3 × 105 obtained with the bias voltage of 1 V, the current increased by ~1 μA upon illu-mination (measured at Vgs = –5 V, Fig. 2b). On the other hand, when the on/off ratio was ~70 (Vds = 1 mV), the in-crease was only ~1 nA (Vgs = –5 V, Fig. 2c). Figure 2d shows that there is a positive linear relationship between the photocurrent/dark current ratio (Iph/Idark) and the on/off current ratio (Ion/Ioff) of the transistor. This indicates that the sensitivity can be improved by operating the transistor with increased on/off ratio. However, the improvement of the on/off ratio has a certain limit. Increasing the bias volt-age over this limit will only cause saturation of the on-state current (Ion) and an increase in the leakage current (Ioff), re-sulting in a lower Ion/Ioff. Therefore, there is an optimum bias voltage for maximum on/off ratio, which is approxi-mately 1 V in our FETs. Gate voltage also could affect the initial state of the FET by varying the carrier concentration in the nanowire channel. The FET can be depleted (Vgs < Vth) or accumu-lated (Vgs > Vth) by the gate voltage. In fact, the effect of Vgs on the sensitivity was already shown in Fig. 2b, c. For in-stance, at Vgs = –5 V, where the FET is initially depleted, the current increases by a factor of 106 upon illumination. At Vgs = 5 V, where it is initially accumulated, the current increases only by a factor of 10 (Fig. 2b). The result indi-cates that the photodetector is more sensitive when the transistor is initially in a depleted state. This can also be observed in the drain–source current (Ids – t) measured as a function of time at three different gate voltages; –5 V, 0 V, and 5 V (Fig. 3a). The photodetector was most sensitive (Iph/Idark ~ 106) at Vgs = –5 V among the three. Additionally, we found that the decay characteristics were also dependent on the gate voltage. The photocurrent de-cayed exponentially over time; ΔI = Iph – Idark = A exp (– t/τ), where A is the pre-exponential factor and τ is the exponen-tial time constant. The obtained time constants by fitting were 185 s, 107 s, and 47 s for Vg = 5 V, 0 V, and –5 V, respectively (Fig. 3b). This relatively slow time scale indi-cates that the decay process is limited by oxygen adsorp-tion rather than by the recombination of photogenerated electron–hole pairs. Both Ids–Vgs and Ids – t measurements showed that an initially depleted state is necessary for high sensitivity. This interpretation holds for the case when the

photo-excited carrier concentration is as high as a degener-ate level. The cases for the lower carrier concentration were studied by the recovery characteristics of the FET after UV light was turned off. Figure 4a shows Ids–Vgs curves meas-ured during the recovery. During illumination, the carrier concentration was at a degenerate level and the conduc-tance showed little gate dependency. Once the UV light was off, the conductance of the device decreased, indicat-ing the reduction in the concentration of photo-excited car-riers. The conductance decreased more rapidly in the nega-tive gate voltage region than in the positive region. Finally, the transistor returned to a semiconducting state. Estimated carrier concentrations at 2 min and 4 min after the illumi-nation was off were 8 × 1017 cm–3 and 3 × 1017 cm–3, re-spectively. Dependence of sensitivity on gate voltage for these carrier concentrations is clearly seen in Fig. 4b, where the plot of the ratio of the residual photocurrent to the dark current (Iph/Idark) versus gate voltage is presented. When the device was under UV illumination, highest sen-sitivity (Iph/Idark ~ 106) could be obtained over any depletion region below the subthreshold swing region (Vg < –1 V). However, the Ids–Vgs curves measured 2 min and 4 min af-ter the UV was off revealed that the photodetector showed maximum sensitivity when Vgs was positioned at the negative end or the “bottom” of the subthreshold swing (Vg ~ –1 V). The transistor initially has minimum dark cur-rent at this point, but a small increase in carrier concentra-tion will cause the current to increase along the steep slope of the subthreshold swing, which makes it the most sensi-tive point. 4 Conclusion We demonstrated that the sensitivity of a ZnO NW FET-based photodetector is highly dependent on bias and gate voltages. It is most sensitive when the two voltages are adjusted so that the FET operates initially with highest on/off ratio at the end of the subthreshold swing region. Our photodetector shows maximum photo- to dark-current ratio of ~106 upon UV illumination near Vgs = –1 V and Vds = 1 V. The results could be applied to improve sen-sitivity of other kinds of FET-based sensors and detectors whose sensing mechanism is based on the change of carrier concentration.

Figure 4 (online colour at: www.pss-a.com) (a)

Change of Ids–Vgs characteristics over time after

UV light is turned off (Vds = 1 V). (b) Iph/Idark as a

function of gate voltage. Maximum Iph/Idark was

obtained at Vg ~ –1 V.

182 Woong Kim and Kyo Seon Chu: ZnO nanowire field-effect transistor as a UV photodetector

© 2009 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim www.pss-a.com

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Acknowledgement This work was supported by a Korea

University Grant (K0819991).

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