z8 assembly language programming manual dec80

8/2/2019 Z8 Assembly Language Programming Manual Dec80

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Z8 PLZ/ASM

Assembly LanguageProgramming ManualDecember 1980


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18 PLI/ASIIAssembly LanguageProgralDlDing lIanual

December 1980


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Copyright 1980 by Zilog, Inc. All rights reserved. No partof this publication may be reproduced, stored in a retrievalsystem, or transmitted, in any form or by any means, elec-tronic, mechanical, photocopying, recording, or otherwise,without the prior written permission of Zilog.Zilog assumes no responsibility for the use of any qircuitryother than circuitry embodied in a Zilog product. No othercircuit patent licenses are implied.


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Preface

This re fe rence manual descr ibes assembly language programming forZi log ' s Z8 s ing le -ch ip microcomputer . The f i r s t th ree sec t ionsof the manual focus on Z8 design fea tu re s and theassembly- language in s t ruc t ion s e t . Sect ions 4 and 5 prov ideaddi t iona l information needed to bui ld a source program,including the use of high- leve l PLZ s ta tements .This manual i s one in a se r i e s descr ib ing the Z8. You wil l needsevera l other manuals to develop, debug, and run Z8assembly- language programs. Programs a re developed on e i the rZi log ' s microcomputer system (MCZ) or the Zilog developmentsystem (ZDS) using the software capab i l i t i e s o f the RIO opera t ingsystem. The manuals needed to use the opera t ing system are :

Z80 RIO Operat ing System User ' s Manual, 03-0072-01Z80 RIO Text Editor User ' s Manual, 03-0074-00

The Z8 assembler produces r e loca tab le objec t modules. Operat ionof th e assembler and objec t module l inkage and re loca t ion aredescr ibed in the :

Z8 PLZ/ASM Assembler User Guide, 03-3048-02PLZ Linker User Guide, 03-3098-02

F ina l l y , while t h i s programming manual inc ludes an overview o fthe Z8 a rch i t e c t u re , you wil l need the following manual fo rde ta i l ed hardware and conf igura t ion in fo rmat ion :Z8 Microcomputer Technica l Manual, 03-3047-02

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SECTION 1

SECTION 2

ContentsARCHITECTURAL OVERVIEW1 .11 .2

1 .3

1 .41 .51 .6

1 .7

In t roduc t i onMemory Segments1. 2. 11 . 2. 21 . 2. 31 . 2. 4

Program Memory . . Externa l Data Memory Reg i s t e r Memory Da ta Leng th s Inpu t /Outpu t1 . 3 .1 Por t 11 . 3. 2 Por t 01 . 3. 3 Por t 21 . 3. 4 Po r t 3Interrupts ..........................Timers /Coun te rs S ta tu s Flags and Program Cont ro l s1 . 6 .11 . 6 .21 . 6 .31 . 6 .41. 6 . 51. 6 . 6

Carry FlagZero FlagSign Flag Overf low Flag Decimal Adjus t FlagHa 1 f Ca r r y Fl ag

Stack Memory

Z8 ASSEMBLER CONVENTIONS2 .12 .2

2 .3

Assembler Overview Assembly Language Sta tement Format 2 .2 .12 .2 . 22 .2 . 32 .2 . 4

Program Labels andIns t ruc t ion Operand Fie ldComments

I d en t i f i e r s

Ari thmet i c Operands2 .3 .12 .3 .22 .3 . 32 .3 .4

Run-Time Versus Assembly-TimeA ri thme t ic Cons tan t sData va r i a b l e sExpres s ions and Opera to rs

v

1-11-21-31-31-31-71-81-81-8l - lCl - lCl - lC1-1]1 - 1 ~

1-1 ;1-1:1-1 :1-111-111-11I - I !

2-12-12-22-32-32-5

2-5

2-62-72-82-9


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CONTENTS (cont.)

SECTION 2 Z8 ASSEMBLER CONVENTIONS (cont . )2.4 Z8 Addressing Modes . . . . . 2-13

2.4 .12 .4 .22.4 .32.4.42 .4 .52.4 .62 .4 .7

Reg i s t e r Address . 2-13Ind i r ec t -Reg i s te r Address 2-15Indexed Address . . 2-16Direc t Address 2-17Relat ive Address 2-17Immediate Data . 2-18A Note on the Regis te r Pointe r 2-19

SECTION 3 ASSEMBLY-LANGUAGE INSTRUCTION SET3.1 Functional Summary ................ 3-13 2 No ta t ion .................................... 3 - 33.3 Assembly-Language Ins t ruc t ions 3-5

SECTION 4 STRUCTURING A Z8 PROGRAM4.1 In t roduct ion . 4-14.2 Program Structure . . 4-1

4.3

4.2 .14 .2 .24 .2 .34 .2 .44 .2 .54 .2 .6

ModulesProcedures ..DO Loops . . IF Statements . . . Scope ............................Summary

4-14-24-34-44-54-6Relocatab i l i ty 4-84.3 .14.3 .24 .3 .3

Sect ions ......... ..................... 4-8Location Counter Control . . . . . . 4-10Modes of Ari thmetic Expressions 4-10SECTION 5 PLZ/ASM HIGH-LEVEL STATEMENTS

5.1 Z8 Source Program Statements . 5-15.2 Pr09ram Structur ing Statements . 5-25.2 .15 .2 .25.2 .35.2 .45.2 .55.2 .6

Module Decla ra t ion . . . . . Procedure Decla ra t ion . DO Statement . . IF S ta t em e n t . . . . . . . . . . . . . . . . . . . . . . . . .IF-CASE StatementJump Opt imi zat ion .

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5-25-25-45-55-75-8


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CONTENTS (cont . )

SECTION 5 PLZ/ASM HIGH-LEVEL STATEMENTS (cont . )5 .3 Defining Data 5-9

5 .3 .15 .3 .25 .3 .35 .3 .45 .3 .55 .3 .6

Constant Defin i t ion . . 5-10Data Types . . 5-11Type Defin i t ion . . 5-14Variable Decla ra t ion . 5-14Label Decla ra t ion . . 5-19SIZEOF Operator . 5-20

APPENDIX A ASSEMBLY-LANGUAGE INSTRUCTION SUMMARYAPPENDIX B HIGH-LEVEL STATEMENT SUMMARYAPPENDIX C ASSEMBLER DIRECTIVES AND PSEUDO INSTRUCTIONS

C .l Assembler Direc t ives . . . . . C-lC.2 Pseudo Ins t ruc t ions . . . . . . . . C-4C.3 Condit ional Assembly . C-4APPENDIX D RESERVED WORDS AND SPECIAL CHARACTERS

D.l Reserved Words . . . D-lD.2 Specia l Characters . D-2APPENDIX E ASCII CHARACTER SET

INDEX

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Figure1-11-21-31-41-51-6

LIST OF ILLUSTRATIONS

Z8 Memory Segments . Working-Reg i s t e r Groups Control Reg i s t ers ...............................Data Lengths ....Z8 Archi tec tu re Diagram Z8 Pin Funct ions and Assignments

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1-21-41-61-71-91-9


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1 .1 Introduction

Section 1Architectural Overview

Zi log ' s Z8 microcomputer in t roduces a new genera t ion ofs ing le -ch ip a rch i t ec ture . Compared to e a r l i e r s ing le -ch ipmicrocomputers , the Z8 of fe r s fa s t e r execut ion , more e f f i c i e n tuse o f memory, more soph i s t i ca t ed i n t e r rup t , i npu t /ou tpu t ( I /O) ,and b i t -m an ipu la t ion c a p a b i l i t i e s , and eas ie r system expansion .Under program c o n t r o l , the Z8 conf igura t ion can be t a i l o red tothe needs o f i t s user . I t can serve as an I /O- in tens ivemicrocomputer , as an i n t e l l i g e n t per iphera l cont ro l l e r with in al a rge r sys tem, or as a memory-intens ive microprocesso r .The Z8's f ea tu res include a powerful r epe r to i r e of 43i n s t ruc t i ons , s imi l a r in form to the in s t ruc t ion s e t s of the Z80and Z8000 microprocessor f ami l i e s . The e f f i c iency o f thesei n s t r u c t i o n s and of the Z8 's in te rna l r eg i s t e r -addres s ing schemenot only speeds program execut ion , but also packs more programin to the Z8 chip than would be poss ib le with comparablemicrocomputers . This i s , of cour se , ext remely important fors ing le -ch ip dev ices where on-ch ip memory space i s l i m i t e d .Real- t ime con t ro l app l ica t ions , fo r which the Z8 i s pa r t i cu l a r l ys u i t e d , requi re f a s t i ns t ruc t ion execut ion and f a s t i n t e r rup tresponse . Operat ing from an 8 MHz c lock source ( i n t e r n a l 4 MHzclock r a t e ) , the Z8 executes most in s t ruc t ions in 1 .5 to 2 .5microseconds (6 to 10 machine cyc les ) . The longes t i ns t ruc t iont akes 5 microseconds (20 c y c l e s ) .The fol lowing summarizes the main f ea tu res of the Z8:

40-pin package, of fe r ing more I/O program con t ro lthan previous ly ava i l ab le in s ing le -ch ipmicrocomputers ; On-chip, 2K-byte, read-only (ROM) program memory withposs ib le expans ion by 62K o f external program memory; On-chip, 144-byte , random-access (RAM) reg i s t e r memory,inc luding 4 I/O por t s and 16 con t ro l r eg i s t e r s ; Poss ib le 62K bytes ex te rna l data memory; Six maskable and pr io r i t i zed i n t e r rup t s ; Two on-chip in te rva l t imers , a l so programmable as even tcounters ;

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Independent on-ch ip UART with hardware p a r i t yg en era to r and checker ; On-chip c lock fo r i n t e rn a l t iming .

The remainder of t h i s sec t ion d esc r i b es in more d e t a i l those Z8f ea t u re s of primary i n t e r e s t to assembly- language programmers.See the Z8 Technical Manual fo r de ta i l ed a r ch i t ec tu r a l andconf igura t ion in fo rmat ion .

1 .2 Memory SegmentsAs shown in Figure 1-1 , the 28 has th ree separa te memory segmentsfo r s to r ing program i n s t r u c t i o n s and d a t a .

Program memory (chip re s iden t or ex terna l ) Data memory (ex te rna l ) Regis t e r memory (chip res iden t )

The l a t t e r inc ludes I/O r e g i s t e r s , co n t ro l and s t a t u s r e g i s t e r s ,and genera l purpose data r e g i s t e r s

r---------,65535

EXTERNALROM OR RAM

r - - - - - - - - t ~ g : ~ ONCHIPROM

PROGRAM MEMORY

. . .--------,65535

EXTERNALRAM

1 - - - - - - - - 1 ~ ~ ! ~ NOTADDRESSABLE

DATA MEMORY

CONTROL ANDSTATUS REGISTERSNOTIMPLEMENTED

GENERALREGISTERS

110 PORTREGISTERSREGISTER MEMORY(ONCHIP RAM)

Figure 1-1 . Z8 Memory Segments

1-2

255

240

127


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The Z8 hardware envi ronment must be sp e c i f i c a l l y conf igured toaccess ex t e rna l program or data memory. Both segments can beaccessed by 16-b i t addresse s .

1 .2 .1 Program MemoryThe f i r s t 2048 bytes o f program memory c o n s i s t of on-ch ipprogrammable s to rage addressed by the program counter . Foraddresses 2048 or g re a t e r , the Z8 automat ica l ly execu tes ex t e rna lprogram memory fe tches (provided the Z8 i s conf iguredaccord i ng l y ) . The f i r s t example below jumps to address 1500 i fthe Zero f lag (Z) i s s e t . The second c a l l s a procedure whoses t a r t ing address i s l oca t ion 20000 in ex t e rna l program memory.

JP Z,1500CALL 20000The f i r s t 12 bytes of program memory a re reserved for the Z8 'si n t e r r u p t mechanism. Addresses 0-11 con ta in s ix l 6 - b i t addressescorresponding to the s ix poss i b l e i n t e r r u p t s ava i l ab le on the Z8,IRQO through IRQ5, r e s p e c t i v e l y . When an i n t e r r u p t occur s ,con t ro l passes to th e address corresponding to t h a t p a r t i c u l a ri n t e r ru p t . A system r e s e t fo rces the program counte r to 12 , thef i r s t address ava i l ab le fo r the user program. See the di scuss i onof i n t e r r u p t s i n Sec t ion 1 . 4 .

1 .2 .2 External Data MemoryA Z8 system can d i r e c t ly access as much as 62K bytes o f ex te rna lda t a memory. This segment i s addressed beginning with dataaddress 2048. Exte rna l I/O i s a lso mapped into t h i s segment .

1.2 .3 Register MemoryRegis te r memory inc ludes 124 genera l -purpose r e g i s t e r s , 4 I/Op o r t s , and 16 s t a t u s and con t ro l r e g i s t e r s . The I/O p o r t andcon t ro l r e g i s t e r s are- rnc luded in r eg i s t e r memory to al low any Z8in s t ruc t ion to p rocess I/O or con t ro l informat ion d i r e c t l y , thuse l imina t ing th e need fo r spec ia l I/O or con t ro l i n s t r u c t i o n s .The Z8 i n s t ruc t ion s e t permi ts d i r e c t access to any o f these 144r e g i s t e r s . Each of the 124 genera l -purpose r e g i s t e r s canfunc t ion as an accumula to r , an address p o in t e r , or an indexr e g i s t e r .

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Z8 i n s t ru c t i o n s can access r e g i s t e r s d i r e c t l y or i nd i rec t ly usingan 8 - b i t address f i e l d . The Z8 a lso a l lows 4 - b i t address ing o fr e g i s t e r s , which gene ra l ly saves byte s , and speeds programexecut ion and t ask swi tch ing . In t h i s 4 - b i t address ing mode, ther eg i s t e r f i l e i s div ided in to 9 work ing- reg i s te r groups , eachoccupying 16 cont iguous r e g i s t e r l oca t ions (Figure 1 - 2 ) . Ar e g i s t e r poin te r (one of the co n t ro l r eg i s te r s ) addresses thes t a r t i n g l o ca t i o n of the cur ren t ly ac t ive work ing- reg i s te r group .

(DEC)255

240

128

112

6

0

4

8

2

6

0

(HEX)FCONTROL REGISTERS, . . . .- -----------F

UNUSED

r - - - - - - - - - - - - - 87

6

5

4

3

2

1

0

Figure 1-2 . Working-Register Groups

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NOTE: Changing the value o f the r e g i s t e r pointe r i s an easy wayto save the 16 cur ren t ly -ac t ive working r e g i s t e r s (asduring i n t e r r u p t process ing) . Reserving one or morework ing- reg i s te r groups for the use of i n t e r rup t -hand l ingrout ines i s a recommended programming p r ac t i c e .In the fol lowing example, the Set Register Pointer (SRP)in s t ruc t ion se t s the r e g i s t e r poin te r to 240, the s ta r t ingaddress o f the con t ro l r e g i s t e r group. The fol lowing Load (LD)in s t ruc t ion i n i t i a l i z e s r e g i s t e r 252 to t en .

SRP #240LD R12, #10 !Register Pointer con ta ins FO (hex)!!Working r e g i s t e r 12 occupies r e g i s t e rloca t ion 252!

Because of t he i r spec ia l s ign i f i cance , the I/O por t r e g i s t e r s(0-3) and cont ro l r e g i s t e r s (240-255) are referenced l a t e r int h i s sec t ion . The con t ro l r e g i s t e r s a re p a r t i c u l a r l y pervasivein a l l Z8 ope ra t ions , s ince they are used in the handling of I /O,i n t e r ru p t s , the t imer / coun te r , program cont ro l f l ags , and theprogram s tack , as well as to point to the cur ren twork ing- reg i s te r group. To provide a quick reference in thefol lowing s ec t i o n s , the cont ro l r e g i s t e r s a re l i s ted in Figure1-3 . They are descr ibed in b i t - l e ve l de t a i l in the Z8 TechnicalManual. Z8 i n s t r u c t i o n s can reference con t ro l r e g i s t e r s bynumber or by t h e i r predefined symbolic i de n t i f i e r s shown in thefol lowing f igure .NOTE

Regis te r memory addresses 128-239 do note x i s t and should no t be spec i f i ed in Z8i n s t ru c t i o n s . The r e su l t of access ing thesel oca t ions i s undefined .

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LOCATION255254253252251250249248247246245244243242241240

127

STACK POINTER (BITS 7-0)STACK POINTER (BITS 15-8)

REGISTER POINTERPROGRAM CONTROL FLAGSINTERRUPT MASK REGISTER

INTERRUPT REOUEST REGISTERINTERRUPT PRIORITY REGISTER

PORTS 0-1 MODEPORT 3 MODEPORT 2 MODE

TO PRESCALER LOADTIMER/COUNTER 0 LOADT1 PRESCALER LOAD

TIMER/COUNTER 1 LOADTIMER MODE

SERIAL I/ONOTIMPLEMENTED

GENERALPURPOSEREGISTERS

PORT 3PORT 2PORT 1PORTO

IDENTIFIERSSPLSPHRPFLAGSIMRIROIPRP01MP3MP2MPREOTOPRE1T1TMRSIO

P3P2P1PO

Figure 1-3 . Control Registers

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1.2.4 Data LengthsZ8 i n s t r u c t i o n s can opera te on indiv idua l b i t s , 4-b i t BinaryCoded Decimal (BCD) d ig i t s or n ibb les , 8 -b i t by te s , or 1 6 - b i twords (Figure 1-4) . B i t s can be s e t , r e s e t , or t e s t e d . Nibblesare used in BCD ar i thmet ic opera t ions . Bytes a re used forcharac te r or small in teger values ( in the range 0 to 255 i funsigned, or in the range -128 to 127 i f s igned) . Words are usedfor l a rger in teger values ( in the range 0 to 65535 i f unsigned,or in the range -32768 to 32767 i f s i gned) .The bas ic da ta element of the Z8 i s the byte . Memory loca t ions(whether they res ide in program, d a t a , or r e g i s t e r memorysegments) are ord ina r i ly accessed e igh t b i t s a t a t ime .Increment Word (INCW) and Decrement Word (DECW) a re the onlyi n s t r u c t i o n s t ha t opera te on 16-b i t words.

78543210I I I I I I I I BITS IN A BYTEUPPER LOWER NIBBLES IN A BYTE! , I I I !

BYTE

UPPER BYTE LOWER BYTE WORD, , ! ! , , , I

Figure 1-4. Data Lengths

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1 .3 Input/OutputThir ty- two o f the 28 ' s 40 l i nes are ded ica ted to inpu t andoutpu t . These 32 l i nes are grouped in to 4 por t s of 8 l i nes eachand can be configured as input , output , or addre ss /da ta . Undersof tware co n t r o l , the por t s can be programmed to provide t iming,i n t e r r u p t reques t s , s t a t u s s i g n a l s , and se r i a l or p a ra l l e l I/Ofea tures with or wi thout handshake.In the fol lowing explanat ion of the various por t func t ions , Por t1 i s descr ibed before Port 0 for convenience. The 28arch i tec tu re diagrams (Figures 1-5 and 1-6) show the I/O l i n e sand s igna l s re fe renced . Although they are p ic tu red separa te ly inFigure 1-5 , remember t h a t from a programming s tandpo in t the I/Op o r t s , t imers , i n t e r ru p t con t ro l s , f l ags , and r e g i s t e r poin te rare a l l manipulated through reg i s t e r memory.

1.3 .1 Port 1Por t 1 can be programmed as a byte I/O por t or as an address /da tapor t for i n t e r fac ing to ex te rna l memory. Associated with Por t 1are the Address Strobe (AS), Data Strobe (OS) and Read/Write(R/W) t iming s ig n a l s . Under program con t ro l , two l i nes from Port3 ( l ines P33 and P34) can be used with Por t 1 as the handshakecont ro l l i ne s (OAVI and ROYl) or as a Por t 1 i n t e r rup t reques tinput (IRQl) and an ex te rna l data memory access (OM) s t a tusoutpu t .I f exte rna l data memory i s to be accessed , Por t 1 i s programmedas an address /da ta por t through which the exte rna l address anddata are passed . In t h i s case , the lower e igh t b i t s o f theaddress (AO-A7) are mult iplexed with data b i t s (00-07). I f anaddress longer than e igh t b i t s i s requi red , the add i t iona laddress b i t s (A8-A15) or ig ina te from Port O.1 . 3. 2 Port 0Por t 0 can be programmed to be e i the r an I/O por t or an addressoutpu t for exte rna l memory. Depending on the s ize o f theaddress , Por t 0 prov ides e i t h e r b i t s 8-11 or b i t s 8-15 of theaddress . (Por t 1 provides b i t s 0-7) . If the address i s 12 b i t sor l e s s , the upper four b i t s (nibble) of Por t 0 can be programmedindependent ly as I/O while the lower nibble i s used foraddressing. When Por t 0 i s used in the I/O mode, tw o l i nes fromPort 3 ( l ines P32 and P35) can be used fo r the handshake con t ro l sDAVO and ROYO.

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OUTPUT INPUT XTAL AS DS R/W RESET

UO ADDRESS OR 1/0 ADDRESSIDATA OR 1/0(BIT PROGRAMMABLE) (NIBBLE PROGRAMMABLE) (BYTE PROGRAMMABLE)

Figure 1-5 . Z8 Architecture Diagram

RESET +5V - +5V P3 ,n'"1 R/W GND -ND XTAL2 P3,CONTROL os XTALl " ' - }CLOCK XTAL1 P2 ,AS XTAL2P20 . - P3, P2,--- POo P2, - P30 P2 ,.....- PO, RESET P2 ......- PO, P2 , . - R/WPORTO PORT 2 P2 ,(NIBBLE .....- PO, P2 , ---- (BIT PRO DS P2 ,PROGRAMMABLE) .....- PO P2 . ---- GRAMMABLE)110 OR AD8-AD 15 110 AS P2,.....- PO, ZB P2 , --- P35 P20--- PO, MCU P2 , ---- GND P3 ,--- PO, P2 , ---- P3, P3.--- Pl 0 P30 -3, - POo P l,--- Pl , PO, Pl ,--- Pl , P3 , -- PORT 3 PO, P1 5PORT 1 P3 , (FOUR INPUT;(BYTE --- Pl , - FOUR OUTPUT). PO, P l.PROGRAMMABLE) --- Pl . P3 . -- SERIAL AND1/0 OR ADo-AD7 PARALLEL 110 PO. Pl,--- P1 5 P35 -- AND CONTROLPl , P3 , -- P05 Pl,--- Pl , P3 , -- PO, Pl ,.....- PO, Pl 0

Figure 1-6. Z8 Pin Functions and Assignments

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1.3 .3 Port 2Por t 2 can be programmed for inpu t or output on a l i ne -by- l ine(b i twise) b a s i s . As in th e case of Por t s 0 and 1 , tw o l i ne s fromPor t 3 ( l ines P31 and P36) can be programmed as the handshakecont ro l l i ne s DAV2 and RDY2. The output buf fe r s of Por t 2 have aprogrammable opt ion for inh ib i t ing the ac t ive pul l -ups to provideopen-drain type ou tpu t s .

1.3 .4 Port 3Por t 3 can be programmed for I/O and/or as a con t ro l por t . InI/O mode, the d i rec t ion of the e igh t l i nes i s f ixed as four inand four o u t . The con t ro l func t ions of Por t 3 are handshake,i n t e r rup t r eques t , t imer in and o u t , and s t a t u s ou t .Two l i nes of Por t 3 can be programmed as a s e r i a l inpu t and as e r i a l ou tpu t i n t e r f a c e . Each l i ne has an 8- b i t s e r i a l / pa ra l l e lreg i s t e r assoc ia ted with it. Ser ia l I/O uses an asynchronousformat with the b i t ra te con t ro l l ed by the in te rna l t imer .In te r rup t s a re generated when a charac t e r i s received ort ransmi t t e d .

1 .4 Interruptsrhe Z8 al lows s ix d i f f e r e n t in t e r rup t s from eight poss ib le,ou rces - - the four inpu t l i ne s o f Por t 3, s e r i a l in and ou t , an d:he tw o t imers (TO and T l, d i scussed in Sect ion 1 .5 ) .3ix b i t s in the In terrupt-Mask con t ro l reg i s t e r can enab le /l i s ab l e the s ix i n t e r rup t s IRQO-IRQ5 i nd iv idua l ly . When more:han one i n t e r rup t i s pending, p r i o r i t i e s are resolved by a) r io r i ty encoder , cont ro l led by the In t e r rup t -P r i o r i t y con t ro l: eg i s t e r .~ t e r r u p t reques ts a re s tored in an In te r rup t -R eques t con t ro l"eg i s t e r , which can a lso be used fo r po l l i ng . When an i n t e r rup t"equest i s gran ted , the Z8 en te r s an " i n t e r rup t machine cycle":hat g loba l ly d i sab l es a l l o the r i n t e r rup t s , saves the program:ounter (address o f the nex t program in s t ruc t ion to be executed)lnd s t a t u s f l a g s , and f i na l l y branches to the vec tor l oca t ion fo ri n t e r rup t . I t i s only a t t h i s po in t t ha t con t ro l passes to.he i n t e r rup t -hand l ing procedure for the i n t e r r up t .le fore the Z8 can recognize i n t e r rup t s fol lowing RESET, somen i t i a l i z a t i o n t a sks must be performed. RESET causes then te r rup t Request Regis te r (IRQO - IRQ5) to be c lea red and heldo zero , and i n t e r rup t s to be g loba l ly disabled ( b i t 7 of then te r rup t Mask Regis te r = 0 ) . The i n i t i a l i z a t i o n rout ine shouldonf igure the Z8 i n t e r rup t reques ts to be enabled/d isabled (v ia

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the IMR) as requ i red by the t a r g e t ap p l i c a t i o n , and p r i o r i t i z e dfo r vectored i n t e r ru p t s (v ia the In te r rup t P r io r i ty Regi s t e r ) .Because RESET holds the IRQ r e g i s t e r to zero , one f i n a l s t ep i srequired before i n t e r rup t s can func t i on , even in pol led mode.S p ec i f i c a l l y , i n t e r r u p t s must be g loba l ly enabled v ia the EIi n s t r u c t i o n ; s imply se t t ing b i t 7 of IMR i s not s u f f i c i e n t .Subsequent to t h i s EI, i n t e r r u p t s can be enabled e i the r by IMRreg i s t e r manipulat ion or by use of the EI i n s t r u c t i o n , withequiva lent e f f e c t s .Addi t iona l ly i n t e r rup t s must be disabled by execut ing a DIin s t ruc t ion before the IPR or IMR con t ro l r e g i s t e r s can bemodif ied . In te r rup t s can then be enabled by execut ing an EIi n s t r u c t i o n .

1.5 Timers/CountersThe Z8 has tw o 8 - b i t counters (TO and Tl ) , each dr iven by i t s own6 -b i t pre sca le r . The pre sca le r s can be dr iven , in t u r n , bye i t h e r an in te rna l (TO and Tl) or ex te rna l (Tl only) c locksource . TO and Tl can opera te independen t ly o f the processorin s t ruc t ion sequence and, consequen t ly , can unburden the programfrom t i m e -c r i t i c a l opera t ions l i k e event count ing or e lapsed- t imeca l cu l a t i o n .Each presca le r can be programmed to divide the inpu t frequency o fi t s clock source by any number from 1 to 64. The pre sca le rdr i ves i t s coun t e r , which decrements a value (0 through 255)s tored in the t imer r e g i s t e r . When the t imer reg i s t e r reachesend-of -count , a t imer i n t e r r u p t request - - IRQ4 (TO) or IRQ5(T l ) - - i s genera ted .Under program co n t r o l , coun te r s /p re sca le r s can be s t a r t e d ,s topped, r es ta r ted to cont inue count ing , or r es ta r ted from thei n i t i a l value of the coun t e r s . The counters can a lso beprogrammed to s top on reaching end-of -count , or to au t oma t i ca l l yre load the i n i t i a l counter value and con t inue coun t ing . El thercounter can be read a t any t ime wi thou t dis turb ing i t s value o rcount mode.The c lock source fo r the Tl coun te r /p re sca le r can be e i t h e r themicroprocessor c lock or an ex t e rna l t imer i npu t . Under programcon t ro l , the ex te rna l t imer inpu t can func t ion as an ex te rna lclock (maximum f requency 1 MHz), a t r i g g e r inpu t t h a t can bere t r igge rab le or n o t , or as a gate inpu t for the i n t e r n a l c l ock .

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)ne l i ne o f Por t 3 a l so serves as a t imer ou tpu t through whichro, T l, or the in te rna l clock can be o u t p u t . The t imer outpu t:oggles whenever an end-of-count o ccu r s . I f the t imer i s)rogrammed to re load the count value and cont inue a t!nd-of-count , t h i s l ine produces a 50% duty cy c l e . The co u n te r s:an be cascaded by feeding the t imer inpu t l ine with the t imer)u tpu t .l .6 Status Flags and Program Controlsrhe a b i l i t y to t e s t data and make d ec i s i o n s based on the r e s u l ts espec ia l ly important in s ing le -ch ip microcomputers . Programsl r i t t en fo r these computers tend to be dominated by con t ro lns t ruc t ions (cond i t iona l and uncondi t iona l jumps, c a l l s , e t c . )Ind by t e s t and mask i n s t r u c t i o n s .:ontrol r eg i s t e r 252 con ta ins s ix f l ags fo r the use of the Z8I rocessor and programmer.

Carry (C)Zero (Z)Sign (S)Overflow (V)Decimal Adjust (D)Half Carry (H)he h a l f ca r ry and decimal ad jus t f l ags a re used only by th e Z8.he other f l ag s can be used by the programmer with the Jump (JP)nd Jump Rela t ive (JR) i n s t ru c t i o n s to provide a r e p e r t o i r e o f 19ondi t iona l t e s t s .xamples:

JP NC, SUBTOT

JR OV, $+50

.6 .1 Carry Flag

!Jump to rou t ine namedSUBTOT if ca r ry i s not se t !!Jump 50 bytes ahead in programif overflow has occurred!

he ca r ry f lag (C) i s a f f ec t ed by Addi t ion (ADD, ADC),ubt rac t ion (SUB, SBC), Compare (CP), Decimal Adjust (DA), RotateRL, RLC, RR, RRC), Swap (SWAP), and the In t e r ru p t Return (IRET)ns t ruc t ions . When s e t , it g en e ra l l y i nd ica t e s a ca r ry o u t o f1e b i t 7 pos i t ion of a r eg i s t e r being used as an accumula tor .Jr example, adding tw o 8 - b i t numbers as in the fol lowing1s t ruc t ions would cause a ca r ry out o f b i t 7 and s e t the c a r ryl ag .

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+

LD 20, #225ADD 20, #64 !Load value 225 in to locat ion 20!!Add 64 to contents of locat ion 201B it 7 6 5 4 3 2 1 022564289

1o[ 1 1 0 0 0 0 1100 0 0 0 00100001= car ry f lagThe car ry f lag can be s e t to one by the Set Carry Flag (SCF)i n s t ruc t i on , cleared to zero by the Reset Carry Flag (RCF)i n s t ruc t i on , and complemented (changed to 0 i f 1, and vice-versa)by the Complement Carry Flag (CCF) i n s t r uc t i on .

1.6 .2 Zero FlagThe zero f lag i s af fec ted by the same i ns t ruc t ions as the ca r ryf lag plus the Logica l (AND, OR, XOR, COM), Increment andDecrement (INC, INCW, DEC, DECW) , and Tes t (TCM, TM)i ns t ruc t ions . In genera l , the zero f lag i s s e t when the"accumulator" r e g i s t e r ' s contents fo l lowing one of the aboveopera t ions i s zero .

DEC 20JP Z , 1 5 0 0

1.6 .3 Sign Flag

!Decrement loca t ion 20 contents!!Jump to program l oca t ion 1500i f loca t ion 20 i s zero a f t e rdecrement ing!

The sign f lag i s af fec ted by the same i ns t ruc t ions as the zerof lag . The sign f lag i s s e t to one when b i t 7 of the r eg i s t e rused as an accumulator in these opera t ions conta ins a one (anegat ive number in twos complement representa t ion) fo l lowing theopera t ion .LD 20, SUBISUB 20, SUB2JP MI, NEG

!Load value of var iab le namedSUBI in to locat ion 20!!Subt rac t value of SUB2!! I f S=l ( r e s u l t i s "minus") ,jump to locat ion labeled NEG!

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1 .6 .4 Overflow FlagThe overf low f lag i s a f f ec t ed by the same i n s t ru c t i o n s as thezero and s ign f l a g s . When s e t , the overflow f lag i nd ica t e s t h a ta twos-complement number in a r e s u l t r e g i s t e r i s in e r ro r s inceit has exceeded the l a rg e s t (+127) or i s l e s s than the sma l l e s t(-128) number than can be represen ted in twos-complementn o t a t i o n . Consider the fo l lowing , as an example:

B it 7 6 5 4 3 2 1 0120+ 10522 5

o 1 1 1 1 000o 1 1 0 1 0 0 1[ 101100001

= ca r ry f lagThe r e s u l t in t h i s case (-95) i s i n co r r ec t . In t h i s case , theJverf low f lag would be s e t .

SUB 20, 21JR ov, $-50

!Su b t rac t l oca t ion 2 1 ' s co n ten t s fromloca t ion 20 ' s !!Jump back 50 bytes in programif overflow has occur red!

1 .6 .5 Decimal Adjust Flagrhe decimal ad jus t f lag i s used fo r BCD a r i t h m e t i c . Since the31gorithm for co r rec t i n g BCD opera t ions i s d i f f e r e n t fo r add i t ion3nd sub t rac t ion , t h i s f lag i s used to sp ec i fy what type oflns t ruc t ion wa s executed l a s t so t h a t th e subsequent Decimal~ d j u s t (DA) opera t ion can do i t s func t ion co r r ec t l y . The decimal~ d j u s t f lag cannot normally be used as a t e s t condi t ion by th e)rogrammer.

L.6.6 Half Carry Flagrhe h a l f ca r ry f lag i nd ica t e s a ca r ry out o f , or a borrow in tol i t 3 as the r e s u l t of adding or sub t rac t ing two 8 -b i t b y t e s ,!ach represen t ing two BCD d i g i t s . The h a l f ca r ry f lag i s used by:he Decimal Adjus t (DA) in s t ruc t ion to conver t the binary r e s u l t)f a previous add i t ion or sub t rac t ion in to the c o r r e c t decimal:BCD) r e su l t . As in the case of the dec imal -ad jus t f l ag , t h i s: lag i s not normal ly accessed by the u se r .

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1 .7 Stack MemoryTo suppor t the power of i t s i n t e r r u p t c ap ab i l i t y , the Z8 has af l ex ib le s tack scheme and a f a s t "con tex t -swi tch ing" mechanism.Context switching r e fe r s to the saving an d r es to ra t ion o f workingr e g i s t e r s , the program counter , f l ag s , and other p e r t i n en tinformat ion when an i n t e r r u p t occur s .Under program co n t r o l , the Z8 can use an in te rna l ( r e g i s t e rmemory) or ex te rna l (da ta memory) s t ack , l imi ted in s ize only bythe ava i l ab le memory space . An 8 - b i t or l 6 - b i t s tack po in te roccupies con t ro l reg i s t e r 255 or the con t ro l reg i s t e r p a i r254-255.CALL i n s t r u c t i o n s use the s tack to s to re the program counterbefore branching to a procedure. In t e r rup t s automat ica l ly savethe program counter and f lag r e g i s t e r . The RET i n s t r u c t i o nre s to re s the program counter from the s tack upon re turn from aprocedure, while IRET a lso r es to res the f lag r e g i s t e r upon re turnfrom an i n t e r ru p t procedure . In a d d i t i o n , the Z8 has PUSH andPOP i n s t r u c t i o n s th a t can save and re s to re any r e g i s t e r of thereg i s t e r f i l e .

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Section 2Z8 Assembler Conventions

2.1 Assembler OverviewThe Z8 microcomputer i s programmed in a symbolic assemblylanguage (PLZ/ASM). This marks a s i g n i f i c a n t improvement overcoding in binary n o t a t i o n . The o p era t io n codes fo rassembly- language s ta tements a re eas i l y memorized (DEC fo rdecrement and DECW fo r decrement word) . In add i t ion , meaningfulsymbolic names can be ass igned to program addresses and d a ta(MULTIPLY ROUTINE as the l ab e l o f the f i r s t s ta tement in amu l t ip ly procedure) .A Z8 source module c o n s i s t s o f PLZ/ASM assembly languages t a t emen t s . These s ta tements a re then t r a n s l a t e d by the Z8assembler in to an objec t module t h a t can e i t h e r be sepa ra t e lyexecuted by the Z8 microcomputer , or can be l i nked with o t h e ro b j ec t modules to form a complete program. Because the assemblerhas some h i g h - l ev e l f e a t u r e s , a source module can a l so i nc ludePLZ co n s t ru c t s such as DO and IF s t a t emen t s . The use r can a l soembed assembler d i r e c t i v e s , which co n t ro l the o p era t io n of theassemble r , in the source module. High-level s ta tements andassembler d i r ec t i v e s are di scussed in Sect ions 4 and 5.Depending on the assemble r d i r ec t i v e s used , addresses wi th in anobjec t module or program can be abso lu te (meaning addresses inthe source program correspond ex ac t l y to Z8 program memoryaddresses ) or re loca tab le (meaning addresses can be ass ignedr e l a t i v e to some base address a t a l a t e r t ime) . Objec t modulesshould be made r e l o ca t ab l e wherever poss ib le so they can bel inked with o th e r objec t modules , and so t h a t o b j ec t programs canbe loaded anywhere in memory. I t a lso al lows the c rea t ion o fl i b r a r i e s of commonly used procedures ( inc lud ing math orinpu t /ou tpu t rou t ines ) t h a t can be l inked s e l ec t i v e ly in tosev e ra l programs as d e s i r e d .Operat ion o f the assembler , module l i n k ag e , address r e l o c a t i o n ,and program execu t ion a re di scussed in the Z8 PLZ/ASM AssemblerUser Guide.

2 .2 Assembly Language Statement FormatThe most fundamental component o f a PLZ/ASM program i s theassemblY-language s t a t emen t co n s i s t i n g of an i n s t ru c t i o n and i t soperands . The i n s t r u c t i o n d esc r i b es an ac t i o n to be t aken ; theoperands supply the data to be acted upon.

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An assembly language sta tement can actual ly include four f ie lds : Statement labels An ins t ruc t ion Operands Comments

The statement l abe l and comment f ie lds are always opt ional . Thesta tement has zero, one, or two operands, depending on theins t ruc t ion se lec ted. The following sta tements have the sameef fec t in a Z8 program, but the second i s much more descr ipt ive(and consequently more helpful in program debugging) Label

INITTl:

Ins t ruc t ionLDLD

Operand (s)Tl, #255Tl, #255

Comment! Load Timer 1i n i t i a l value!

Each of the elements of a PLZ/ASM program must be separated fromother elements by one or more del imi ters . A del imi ter is one ofthe characters : space (blank) , comma, semicolon, tab, carr iagere turn, l ine feed, or form feed. Note tha t carr iage return i st reated the same as any other del imi ter , so that a s ingles tatement may span several l ine s , or several s tatements mayappear on a s ingle l ine . The del imi ter used in a speci f ics i tuat ion is up to the programmer. For the sake of i l l us t r a t ion ,th i s manual uses blanks to separate statement f ie lds and commasto separate operands.2.2.1 Program Labels and Iden t i f ie rsAny assembly-language (or high-level) statement in a Z8 programcan be preceded by any number of l abe l s . Any s tatementreferenced by another statement must be labeled. A l abe lconsis ts of an iden t i f ie r followed by a colon (:) in the form:

l abe l l : labe12: labeln: sta tementA PLZ/ASM iden t i f ie r can contain up to 127 charac ters , of whichthe f i r s t must be a l e t t e r . The remaining characters can bel e t t e r s , dig i t s , or the special character underscore ( ) .Let ters can be capi ta l ized or lower-cased, but each time aniden t i f ie r is used, it must be wri t ten in exact ly the same way.The following are val id iden t i f ie rs :

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START UP ROUTINEProgram I n i t i a l i z a t i o nA -Loop 12Nl -s o r t

In addi t ion to t he i r s ta tement - label ing func t ion , i d e n t i f i e r sserve as symbolic names fo r cons tan ts (Sect ion 2 .3 .2 ) , da tavar iab les (Sect ion 2 . 3 . 3 ) , and procedures (Sec t ion 5 . 2 . 2 ) .Cer ta in i den t i f i e r s serve as PLZ/ASM keywords and should no t beused as programmer-defined i den t i f i e r s (see Appendix D).An i d e n t i f i e r can be assoc ia ted with only one item with in thescope of i t s de f i n i t i on . Sect ion 4.2 .5 expla ins the scope ofi d e n t i f i e r s , including the scope of l a be l s . For the moment, wecan say t ha t l abe l s a re access ib le with in the module in whichthey are def ined , and are not acces s ib l e outs ide t ha t moduleunless s pec i f i ca l l y declared to be GLOBAL or EXTERNAL.

2.2 .2 InstructionThe in s t ruc t ion i s the assembly-language mnemonic desc r ib ing aspec i f i c ac t ion to be taken .

LD R5, RIO !Load r e g i s t e r 5 from reg i s t e r 10!SRP #%10 !Se t Reg is te r Pointe r to 10 (hex)!

The in s t ruc t ion must be separated from i t s operands by ade l imi t e r .

2.2 .3 Operand FieldDepending on the i n s t r u c t i o n sp e c i f i e d , t h i s f ie ld can have zero ,one, or two operands . I f tw o operands are needed , they must besepara ted by a de l imi t e r .

CCF !No operand!SRP #%10 lOne operand!ADD R6, #210 !Two operands!

Operands supply the informat ion the i ns t ruc t ion needs to ca r ryout i t s ac t ion . An operand can be:

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Data to be processed ( immediate da ta ) ; The address o f a l oca t ion from which data i s to be taken(source address) ; The address o f a l oca t ion where data i s to be p ut(des t ina t ion address) ; The address o f a program l oca t ion to which programcon t ro l i s to be passed; A cond i t ion code , used to d i r e c t the flow o f programco n t r o l .

When these operand types are combined, the poss ib le o rder ings areas fo l lows:Ins t ruc t ion D es t i n a t i o n , ImmediateIns t ruc t ion D es t i n a t i o n , SourceIns t ruc t ion Condit ion Code, Program Locat ion

Immediate data can be in the form of a cons tan t , an ad d ress , oran express ion (cons tan t s and /or addresses combined by opera to rs) Each of these forms i s descr ibed in Sect ion 2 .3 .LD RO, #KLD RO, #COUNTER

ADD RO, #(CON/3 + 5)

!Load constan t K i n to reg 01lLoad address o f COUNTER in toreg 01!Add value o f express ion(CON/3 + 5) to con ten t s o freg 01

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Source, d es t i n a t i o n , an d program addresses can also take sev e ra lforms. PLZ/ASM address ing modes are described in Sect ion 2 .4 .Some examples a re :LD RO, @R5

LD 55, VARI

JP Z, LOOPI

JP NZ, LOOPI + 5

!Load value whose address i s inr e g i s t e r 5 in to r e g i s t e r O!!Load value loca ted a t addressl abe led VARI in to r e g i s t e rf i l e loca t ion 55!

!Jump to program addressl abe led LOOPI i f zero f l ag (Z)i s se t !!Otherwise , jump to l oca t ionf ive bytes a f t e r LOOPI!

Condit ion codes are l i s t e d in Sect ion 3 .2 . They a re used only bythe Jump (JP) and Jump Rela t ive (JR) i n s t r u c t i o n s .

2.2 .4 CommentsComments a re used to document program code as a guide to programlog ic and to s impl i fy p resen t or fu ture program debugging.Comments can be inse r ted anywhere a program de l imi t e r can appear .Comments a re bounded by exclamat ion poin t s (!) an d can containany cha rac te r s except the exclamat ion poin t i t s e l f .

!Module 3, Changed 7-25-78!RES R13, 13 !Turn o ff "convert" f lag!

A s ingle comment can cross l i ne boundaries ; t h a t i s , car r iagere tu rns can occur within a comment.Comments can a l so s t a r t with II. This type o f comment does n otneed a c los ing symbol ; the ca r r i age r e tu rn , , a t the end o fthe l ine on which t h i s comment appears t e rminates the comment.

IIModule 3, Changed 7-25-78 RES R13, #3 IITurn o ff "convert" f lag

2 .3 Arithmetic OperandsConstants and data va r i ab le s are types o f operands t h a t can beused in assembly-t ime a r i thme t i c express ions , or s ing ly asoperands fo r a Z8 i n s t r u c t i o n . This sec t ion descr ibes thedi f fe rences between assembly-t ime and run- t ime ar i thmet ic ,

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de f i nes cons tants and data var i ab les , and expla ins howexpress ions a re formed using ope ra to rs .

2.3.1 Run-TilDe Versus Assembly-Time ArithmeticAri thmet ic i s performed in two ways in an assembly-languageprogram. Run-time ar i thmet ic i s done while the program i sac tua l ly execut lng .

SUB RIO, R12 !Subt rac t the contents o f reg 12from the content s o f reg 10!Assembly-t ime ar i thmet ic i s done by the assembler when theprogram i s assembled and involves the eva lua t ion o f ar i thmet icexpress ions in operands , such as the fo l lowing:

LD RO, *(22/7 + X)JP Z, LOOPI + 12ADD R2, @HOLDREG-l

Assembly-time a r i thme t i c i s more l imi ted than run-t ime ar i thmet icin such areas as s igned versus unsigned a r i thme t i c and the rangeof values permi t ted .Only unsigned a r i thme t i c i s allowed in assembly- t ime express ioneva lua t ion . Run-time a r i thme t i c uses both s igned and unsignedmodes, as determined from the assembly-language in s t ruc t ionspec i f ied and the meaning a t t ached to operands by the programmer.All assembly-t ime a r i thme t i c i s computed using 16-b i t a r i thmet ic ,"modulo 65536". Values g r ea t e r than or equal to 65536 a redivided by 65536 an d the remainder of the d iv i s ion i s used as ther e su l t . I f the r e s u l t o f assembly-t ime a r i thme t i c i s to bes tored in a s ing le byte l o ca t i o n , the r esu l t ing value must berepresentable in 8 b i t s ; t h a t i s , the range 0 to 255 (or -128 to127 i f signed rep re sen ta t ion i s i n t ended) .

LD RIO, tX+22

JP X+22

!Resul t of (X+22) must be inrange -128 to 255!!Modulo 65536. Resu l t i s theaddress 22 bytes beyond X!

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2.3 .2 ConstantsA constant value is one tha t does not change throughout theprogram. Constants can be expressed as numbers, as charac te rsequences, or as a symbolic name representing a constant value.Numbers can be writ ten in decimal, hexadecimal, binary, or oc ta lnota t ion . The l a t t e r three are preceded by a percent sign (%)and, in the case of binary and oc t a l , by a base spec i f ie renclosed in parentheses. I f a number has no pre f ix , decimal i sassumed.

10%10%AFOF%(2) 10110010%(8)70

decimalhexadecimalhexadecimalbinaryoc ta lA character sequence is a sequence of one or more charactersenclosed in single quote marks. Any ASCII charac te r (except apercent sign or single quote) can be included in the charac te rsequence. Since constants are represented as 32-bi t values , onlythe f i r s t four characters in a s t r ing l i t e r a l , used as aconstant , are meaningful , for example, 'ABCD = ABCDE'.

'A''This is a character sequence'A charac te r can also be represented in a character sequence inthe form "%hh," where "hh" is the hexadecimal equiva len t of theASCII code for the charac ter . (See Appendix E for the ASCIIcharacter se t and i t s hexadecimal equivalents . )

'Here i s an ESC character : %lB'For convenience, ce r ta in ASCII characters have been assignedshor te r , more mnemonic codes as follows:

Example:

%L or %l Linefeed%T or %t Tab%R or %r Ca r r ia g e Re t urn%P or %p Page (Form Feed)%% Percent Sign%Q or %q Single Quote

' F i r s t line%rSecond l ine%r''Quote%Qinside a quote%Q'A constan t can be assigned a symbolic name by a constan tdef in i t ion (CONSTANT) s ta tement . A symbolic i den t i f i e r , once

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assoc ia ted with a constant va lue , re t a ins tha t value through thee n t i r e program module.Constant symbols are def ined by the CONSTANT sta tement in theform shown below. Ide n t i f i e r s fo l low the ru les out l ined inSect ion 2 .2 .1 . The spec ia l cha rac t e r pa i r ":=" can be read " isdefined as " .

CONSTANTREC LENGTH : = 64BUFFER LENGTH := 4*REC LENGTHSEMICOLON := ' . ,BIGNUMBER := 65000smallnumber := -1Certain cons tants are p redef ined by the assembler and should notbe used fo r programmer-defined constant symbols (see Appendix D).

2.3 .3 Data VariablesA da ta var iab le can be thought o f as a con t a i ne r t h a t can holdd i f f e r e n t values from t ime to t ime . An 8 - b i t (BYTE orSHORT INTEGER) var iable can hold values in the range 0 to 255 i funsigned, o r -128 to 127 i f s igned twos-complement representa t ioni s intended. Simi la r ly , a 16-b i t (WORD or INTEGER) va r i ab le canhold values in the range 0 to 65535 i f unsigned, o r -32768 to32767 i f s igned.

NOTEBYTE and WORD var iab les should be used fo r unsigned va lues ,and SHORT INTEGER and INTEGER va r i ab le s should be used forsigned values ; the re are no r e s t r i c t i ons on whether ap a r t i c u l a r va r i ab le i s signed or unsigned. Therefore , BYTEand SHORT INTEGER are t r ea ted as equ iva len t , as are WORDand INTEGER; the appropr ia te i n t e rp re ta t ion i s made by theprogrammer.

A da ta var iab le name can be assoc ia ted with e i t h e r a r e g i s t e r orda ta memory loca t ion ; the value of the var iab le i s the content so f t h a t l oca t ion a t the t ime the va r i ab le i s r e f e renced . A da tava r i ab le name i s a symbolic i de n t i f i e r and fo l lows the ru les fori de n t i f i e r s in Sect ion 2 .2 .1 .LD R5, MPLIER

ADD R5, 3 + SUBTOTAL

!Load the value contained in theloca t ion symbolized by MPLIER!

!Add the value contained in theloca t ion 3 bytes a f t e r theloca t ion named SUBTOTAL to thecon t en t s o f reg 5!

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I f a data var i ab l e operand i s preceded by i, it i s t r ea t ed asimmediate da ta and the value used i s the da ta address associa tedwith the v a r i a b l e , no t the con ten t s o f the loca t ion . Forexample , suppose r e g i s t e r 50 has the symbolic name COUNTER andcon ta ins the b i t pa t t e rn 11111111 (decimal 255) .LD T l, COUNTER 1255 i s loaded in to Timer 11LD T l, iCOUNTER 150 i s loaded in to Timer 11LD T l, COUNTER - 5 lContents of reg 45 are loadedin to Timer 11LD T l, iCOUNTER - 5 145 i s loaded in to Timer 11

Every da ta var i ab l e name has a type and scope associa ted with it,as wel l as a va lue . The type and scope (and, o p t i o n a l l y , thei n i t i a l value) are def ined in a var i ab l e dec la ra t ion s ta tementl i ke the fo l lowing:INTERNALSWITCHI BYTE

In t h i s example , INTERNAL i s the scope of the var i ab l e SWITCHl,and BYTE i s i t s t ype .Variable dec la ra t ion i s the sub jec t of Sec t ion 5 .3 .4 . For thepurposes of t h i s sec t ion , va r i ab les can have GLOBAL, EXTERNAL,INTERNAL, o r LOCAL scope . They can be one of the simple t ypes ,BYTE or SHORT INTEGER ( for 8 - b i t values) or WORD or INTEGER ( for16-b i t va lues ) . They can also be one o f the s t ruc tu red types ,ARRAY or RECORD.

2.3 .4 Expressions and OperatorsExpress ions are formed using a r i t h m e t i c , l og i ca l , s h i f t , andr e l a t i ona l opera tors in combinat ion with cons tan t s and var i ab le s .These opera tors al low both unary (one-operand) and binary(two-operand) expre ss ions , a s shown below.Arithmetic OperatorsThe ar i t hmet i c ope ra to r s a re as fol lows:

Operator Operat ion+ Unary p l u s , binary addi t ion

Unary minus , binary sub t rac t ion* Unsigned mul t ip l i ca t ion

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Operator Operat ion/ Unsigned div i s ion

MOD Unsigned modulusThe div i s ion opera to r ( / ) t runca tes any remainder . The MODopera to r re tu rns the remainder from dividing i t s operands .

17/4 = 417 MOD 4 = 1

I f zero i s spec i f i ed as the r i g h t operand fo r e i t h e r o f thesediv i s ion ope ra to rs , the r e s u l t i s undef ined.Examples:

ADD R5, #-3

ADD R5, #K + (5*3)

!A minus 3 i s added toreg 5!!Value of cons tan t K + 15 i sadded to reg 5!

Once aga in , express ions contain ing these ope ra to rs a re evalua teda t assembly t ime and, consequen t ly , the a r i thme t i c performed i sunsigned. Signed a r i thme t i c can still be done a t run t ime,however. Signed mu l t i p l i c a t i o n , fo r example, can be done bylooping through a s e r i e s o f S h i f t and Add i n s t ru c t i o n s .Logical OperatorsThe l og ica l opera to rs a re as fo l lows :

Operator Operat ionLNOT (Unary) Logical complementLAND Log i c a l ANDLOR Log i c a l ORLXOR Logica l EXCLUSIVE OR

LNOT simply complements th e b i t pa t te rn of i t s ( s ing le) operand.A ll one b i t s are changed to zero and vice -ve rsa .LD P2M, LNOT MASK IReverse the b i t s in th emask used to program Por t 2!

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The e f f e c t of LAND, LOR, and LXOR can be seen from the fol lowingexamples. Assume two cons tants A and B have the b i t pa t te rns11110000 and 01010101, r espec t ive ly . The express ions :A LAND BA LOR BA LXOR B

wil l r e su l t in the fol lowing eva lua t ions of the operands:LAND 111100000101010101010000

LOR 111100000101010111110101LXOR 111100000101010110100101

LAND s e t s a one b i t whenever both ANDed b i t s a re one; LOR s e t s aone b i t whenever e i the r ORed b i t i s one; LXOR s e t s a one b i t whenthe tw o EXCLUSIVE-ORed b i t s are d i f f e r e n t .The assembly- t ime log ica l opera t ions performed by LNOT, LAND,LOR, and LX OR can a l so be done a t run t ime by the Z8 i n s t ruc t ionsCOM, AND, OR, and XOR. The assembly- t ime opera t ions requi re l e sscode and reg i s t e r manipu la t ion . The run- t ime opera t ions al lowgrea te r f l e x i b i l i t y , however. For example, they can operate onr e g i s t e r s (var iab les) whose con ten t s a re not known a t assemblyt ime, as well as on known constan t values .Shi f t OperatorsThe s h i f t opera to rs a re as fo l lows:

SHRSHL Logical s h i f t r igh tLogical s h i f t l e f tWhen used in express ions , the s h i f t opera to rs have the form

d opera to r nwhere lid" i s the data to be sh i f t ed and "n" spec i f i e s the numberof b i t s to be sh i f t e d . Vacated b i t s are rep laced with zeros .For example, i f the constan t PRODUCT i s equal to 10110011, thes ta tement

LD RO, #(PRODUCT SHL 2)would load the value 11001100 in to working r e g i s t e r O.If the second operand supp l ied i s negat ive ( t h a t i s , i f the signb i t is s e t ) , it has the e f f e c t o f reversing the d i rec t ion of thes h i f t .

ADD PRODUCT, # (MPLIER SHR -1)

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Relat ional OperatorsThe re l a t iona l opera to rs are as fo l lows :

< Less than= Greater than o r equal> Greater than

These s ix re l a t iona l opera tors re turn a l og ica l TRUE value ( a l lones) i f the comparison of the two operands i s t ru e , and re turn al og ica l FALSE value ( a l l zeros) otherwise . The ope ra to rs assumeboth operands a re unsigned.LD RO,i(1=2)LD RO,i(2+2) < 5 !Reg 0 i s loaded with zeros!!Reg 0 i s loaded with ones!

Precedence of Opera to rs . Express ions are gene ra l ly evalua tedl e f t to r i g h t with opera to rs having the highes t precedenceevaluated f i r s t . I f tw o ope ra to rs have equal precedence, thel e f t mo s t i s evaluated f i r s t .The fol lowing l i s t s the PLZ/ASM opera to rs in order o fprecedence:1 . Unary ope ra to rs : +; - , LNOT2. Mult ip ly /Divide /Shi f t /AND: *, / , MOD, SHR, SHL, LAND3. Add/Subtract/OR/XOR: +, - , LOR, LXOR4. Rela t ional ope ra to rs : Paren theses can be used to change the normal order of precedence .I tems enclosed in paren theses a re evaluated f i r s t . I fparen theses are nes ted , th e innermost are eva lua ted f i r s t .

20/5 - 12/3 = 020/(5 - 12/3) = 20

Modes of Ar i thmet ic Express ions . A ll ar i thmet ic express ions havea mode assoc ia ted with them: abso lu te , r e loca tab le , or ex t e r n a l .These modes are defined in d e t a i l in Sect ion 4 .3 .3 .

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2.4 Z8 Addressing ModesWith the excep t ion o f immediate d a ta and condi t ion codes , a l lassembly- l anguage operands a re expressed as a dd r e s se s : r e g i s t e rad d res ses , program memory ad d res ses , and ex te rn a l da ta memorya dd r e s se s . The v ar io u s address modes recognized by the Z8assembler a re as fo l lows:

Regis te r In d i r e c t Regis t e r Indexed Address Direc t Address Rela t iv e Address Immediate

Spec ia l c h a r a c t e r s a re used in operands to i den t i fy ce r t a in o fthese address modes. The ch a rac t e r s a re :

"R" preced ing a workingreg i s t e r number; "RR" preceding a wo rk in g - reg i s t e r p a i r ; "@" preceding an i n d i r e c t - r e g i s t e r r e fe ren ce ; "I" preceding immediate d a t a ; " ( ) " used to enclose the index r eg i s t e r p a r t o fan indexed a dd r e s s ; "$" s ign i fy ing the c u r r e n t program counte r l o c a t i o n ,u su a l ly used in r e l a t i v e ad d res s in g .

The use of these c h a r a c t e r s i s shown in the fol lowing s e c t i o n s .Not every address mode can be used by every i n s t r u c t i o n . Thei n d iv id u a l i n s t ru c t i o n d e s c r i p t i o n s in Sec t ion 3 d esc r ib e whichaddress modes can be used fo r each i n s t r u c t i o n .

2.4 .1 Register AddressIn r eg i s t e r address ing mode, the operand va lue i s the co n ten t s ofthe sp ec i f i ed r e g i s t e r .

r e g i s t e r~ _ i n __t_r_u_c _t _ i _ o _ n ~ ~ - - - - - - ~ ~ ~ : I operand

The r eg i s t e r can be addressed in e i t h e r o f two ways. The addresscan be :

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an 8 - b i t address in the range 0-127, 240-255, o r a 4 -b i t work i ng- reg i s t e r address .

The fu l l 8 - b i t address i s indica ted in the operand f i e ld bysupplying an express ion (see Sect ion 2 .3 .4) which eva lua tes toe i the r the number o f the r e g i s t e r or a va r i ab le name assoc i a t edwith a r e g i s t e r . Neither of these has a spec ia l -cha rac t e rp r e f ix .

LD 55, U F3

LD FLAGS, iZEROS

ADD 120, SUBTOTAL

Working-Regis ter Address

!Load r e g i s t e r 55 with thehexadecimal value F3!!Load r e g i s t e r named FLAGS( i . e . , reg 252) with the va lueof the cons t an t named ZEROS!!Add content s of r e g i s t e r namedSUBTOTAL to r e g i s t e r l20!

Designat ing a r e g i s t e r by a 4 -b i t working- regi s te r address ,ra the r than an 8 -b i t r e g i s t e r address , of ten reduces the l engthof an in s t ruc t ion and r e su l t s in a s h o r t e r execut ion t ime. Int h i s case , the fu l l address i s formed by concatena t ing th e 4 - b i tf i e ld (address range 0-15) with the upper 4 b i t s of the Regis te rPo i n t e r ; thus the working- regi s te r s e t can be var ied dynamical lys imply by changing the value o f the Regis te r Poin ter (cont ro lr e g i s t e r 253) .A working- regi s te r operand i s indica ted by a number in the range0-15 preceded by the l e t t e r "R".

LD RO, R15

LD 53, R15

ADD R6, AUGEND

Regis te r Pa i r Address

!Load the con t en t s o f workingr e g i s t e r 15 in to working r e g i s t e r O!!Load the con t en t s o f working r e g i s t e r15 in to r e g i s t e r 53!!Add content s of r e g i s t e r namedAUGEND to working r e g i s t e r 6!

Regis te rs can be used in pa i r s to des igna te l 6 - b i t values ormemory addresses . A r e g i s t e r pa i r can be spec i f ied as anexpress ion which eva l ua t e s to an even number in the range0,2 ,4 . . 126 or 240,242 254. I t - can a l so be designated as th evar iable name of an even-numbered r e g i s t e r .

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DECW 20 !Decrement content s of r e g i s t e r s 20and 21!

Working-Regis ter Pa i r AddressWorking-reg is te r pa i r s a re indica ted by an even number in therange 0, 2, 4, 6, 14. If the 10w-order(odd) byte of a pa i ri s s p ec i f i ed , an e r ro r wi l l r e s u l t . In the case of a workingreg i s t e r p a i r , the r e g i s t e r number i s preceded by the l e t t e r s"RR." For example , RRO r e fe r s to RO and R1.

INCW RR10 ! Increment content s of workingr e g i s t e r s 10 and 11!

2 .4 .2 Indirect -Regis ter AddressIn i n d i r e c t address ing , the value o f the operand i s n ot thecontent s of a r e g i s t e r . Ins t ead , the r e g i s t e r ( r eg i s t e r p a i r ,working r e g i s t e r or working- regi s te r pa i r ) con ta ins the addressof the l oca t ion whose content s a re to be used as the operandval ue

reg i s t e r (s)in s t ruc t ion address I - - - - - - - - - I . operand

Depending on the i n s t r u c t i o n s e l ec t ed , the address may po in t to ar e g i s t e r , program memory, or ex te rna l data memory l o ca t i o n .Regis te r p a i r s or working- regi s te r pa i r s are used to hold the16-b i t addresses when access ing program or exte rna l da ta memory.Pa i r s a re indica ted by an even number (see Sect ion 2 . 4 . 1 ) .The i n d i r e c t - r e g i s t e r address mode may save space and improveexecut ion speed when data i s accessed from consecut ive l o ca t i o n s .This mode can a lso be used to s imula te more complex address ingmodes, s ince addresses can be computed before the assoc i a t ed da t ai s accessed .An i n d i r e c t address can be an express ion which eva l ua t e s to ar e g i s t e r number, the va r i ab le name of a r e g i s t e r f i l e l o ca t i o n ,or a r e g i s t e r -p a i r des igna to r . I t can a l so be a work i ng- reg i s t e rdes igna to r , or a work ing- reg i s t e r -pa i r des i gna t o r . In a l l case s ,the r e g i s t e r spec i f i ca t ion must be preceded by a commercial a tsymbol (@) .

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JP @RRO

JP @20

LO @TOTALS, 30

LO @TOTALS, #30

2.4 .3 Indexed Address

!Pass con t ro l (jump) to theprogram memory loca t ionaddressed by workingr e g i s t e r pa i r O-l!!Jump to program loca t ionaddressed by r e g i s t e r pa i r20-21 !!Load con ten t s o f r e g i s t e r30 i n to loca t ion addressed byreg i s t e r named TOTALS!!Load immediate value 30 in toloca t ion addressed by TOTALS!

An indexed address cons i s t s o f a r e g i s t e r address of f s e t by thecon ten t s of a designated working r e g i s t e r ( the index) . Thiso f f se t i s added to the r e g i s t e r address and the r esu l t ing addresspoints to the l oca t ion whose value i s used by th e i n s t ruc t ion .This address mode i s used only by the Load (LO) i n s t ruc t ion .

in s t ruc t ion

workingreg i s t e r

address I --------------- I. + )---__ operandThe reg i s t e r address i s spec i f i ed as an express ion whicheva lua tes to a r e g i s t e r - f i l e number or to the va r i ab le name o f areg i s t e r f i l e l o ca t i o n . This address i s followed by the index, awork ing- reg i s te r des igna to r enclosed in p a ren t h eses .

LO RIO, TABLE (RO) !Load the con ten t s o f theloca t ion addressed by TABLEplus the con ten t s o f reg 0into reg 10!

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LD 240 (RO), RIO !Load the con ten t s o f reg 10 in tothe con t ro l reg i s t e r whoseaddress i s 240 plus the con ten t sof reg O!Since the spec i f ied r e g i s t e r address and working r e g i s t e rcon ten t s are both 8 - b i t va lues , the indexed-address mode can beused for base address ing . The base address i s loaded into theworking reg i s t e r and the o f f s e t ( r eg i s te r address) then completesthe address f i e ld .

2.4 .4 Direct AddressDirec t -address mode i s used only by the Jump (JP) and Cal l (CALL)i n s t r u c t i o n s to spec i fy the des t ina t ion where program con t ro l i sto be t r an s f e r r ed . The address may be spec i f ied as an express ionwhich eva lua tes to a number or a program l a be l .

in s t ruc t ion

address

CALL MATH ROUTINE

JP C,%2000

2.4 .5 Relat ive Address

!Transfer con t ro l to theprocedure labeled MATH_ROUTINE!!Jump to l oca t ion 2000 (hex) ifthe carry f lag i s se t !

Rela t ive-address mode i s implied by i t s i n s t ruc t ion . I t i s usedonly by the Jump Rela t ive (JR) and the Decrement and Jump I fNonzero (DJNZ) i n s t r u c t i o n s and i s the only mode ava i l ab le tothese i n s t ruc t ions . The operand, in t h i s case , represents ano f f se t t h a t i s added to the con ten t s of the program counter toform the des t ina t ion address ( the program address where con t ro li s to be t r a n s fe r r e d ) . The o r ig in a l con ten t s o f the programcounter i s taken to be the address of the in s t ruc t ion bytefol lowing the JR or DJNZ i n s t ru c t i o n , while the o f f s e t value i san 8 - b i t signed value in the range -128 to 127.

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in s t ruc t ion

prog ramcounter

r - - - - - - - - - ~ . ~ I addressI

~ O _ f _ f _ s _ e _ t ~ r - - - - - - - - - - - - - - - - - - - - - - - - - ~ ~ ~ I ~ I address IThe o f f s e t value can be expressed in tw o ways. In the f i r s tcase , the programmer provides a spec i f i c of f s e t in the form "$+n"where n i s a cons tan t express ion in the range +129, -126 and $represents the con ten t s o f the program counter a t the s t a r t o fthe JR o r DJNZ in s t ruc t ion (each i n s t r u c t i o n i s two bytes inlength)

JR OV, $+K !Add value of cons tan t K to programcoun ter and jump to new loca t ion i foverf low has occurred!In the second method, the assembler c a l c u l a t e s the o f f s e t . Theprogrammer s imply s pe c i f i e s an express ion which eva lua t es to a1umber or a program l abe l as in d i r e c t address ing . The addressspec i f ied by the operana-must be in the same module and sec t ion3S the JR or DJNZ in s t ruc t ion and must be within the o f f s e t range(+127, -128) .

JR OV, MATH ERRORDJNZ R5, LOOP !Decrement reg 5 an d jump to LOOP ifthe r e s u l t i s no t zero!

rhe Jump (JPR) con t ro l i n s t r u c t i o n causes the assembler to)roduce a JR whenever poss ib le . Refer to Sect ion 5.2 .6 fo ri e t a i l ed informat ion on the Jump opt imizat ion .

~ . 4 . 6 Immediate Data[mmediate data i s an address mode fo r the purposes of t h i sl i s cus s ion . The operand value used by the i n s t r u c t i o n in t h i s:ase i s the value suppl ied in the operand f ie ld i t s e l f .

in s t ruc t ion

operand

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Immediate address mode i s of ten used to load r e g i s t e r s with t he i ri n i t i a l va l ues . The Z8 i s optimized for t h i s func t ion , providingseve ra l shor t immediate data in s t ruc t ions to reduce the bytecount o f programs.Immediate data i s preceded by the spec ia l cha rac t e r # and may bea cons t an t ( including cha rac t e r cons t an t s and symbolsrepresent ing constant s) or an express ion as described in sec t ion2 .3 .4 . Remember, i f a va r i ab le name i s pref ixed by #, the valueused i s the address represen ted by the v a r i ab l e , not the con t en t sof the address . Immediate data values must be in the range -128to 255 ( tha t i s , express ib le in 8 b i t s ) , o r an e r ro r message wi 11be genera ted .

LD 100, #%12LD COUNTER, #COUNT-50

LD POINTER, #ITEM

!Load l2(hex) in to reg 100!!Load r e g i s t e r namedCOUNTER with value o fcons t an t COUNT-50!

!Load r e g i s t e r namedPOINTER with the value of theaddress o f var iable ITEM!

Two spec i a l op e ra t o r s a re provided to ease the manipulat ion o f16-b i t addresses : the HI opera tor g ives the h igh-order by te , andLO gives the low-order byte o f a l 6 - b i t express ion . Since HI andLO can only be used where the immediate address ing mode i sapp l i cab le , the # cha rac t e r must precede them.

LD R6,#HI DLABEL

LD R7,#LO DLABEL

!Load b i t s 8-15 of l 6 - b i taddress o f DLABEL in to reg 6!!Load b i t s 0-7 of l 6 - b i taddress o f DLABEL in to reg 7!

2.4 .7 A Note on the Register PointerFor the assembly-language programmer, deal ing with workingr e g i s t e r s i s an automat ic procedure . The assembler determinesthe appropr ia te b inary in s t ruc t ion code so t h a t the spec i f i edworking- regi s te r address can be formed a t run time using th ecur ren t value o f the r e g i s t e r po in te r . The upper four b i t s o fthe memory address a re taken from the r e g i s t e r po in te r ; the lowerfour b i t s a re taken from the in s t ruc t ion code, and toge ther theyspec i fy the des ignated working r e g i s t e r .When programming in b inary code , an add i t iona l p o ss i b i l i t ye x i s t s . When a f u l l 8 -b i t r e g i s t e r des i gna t o r i s requ i red by thein s t ruc t ion format ( r eg i s t e r or r e g i s t e r -p a i r address modes), aworking r e g i s t e r or working- regi s te r pa i r can be spec i f ied

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wi thout knowing the cur ren t value of the r e g i s t e r p o i n t e r . I fthe upper nibb le of the r e g i s t e r f i e ld i s coded as a hexadecimalE, the lower nibb le i s i n t e rp re t ed as a work ing- reg i s te r (EO-EFhex are no t implemented r eg i s t e r ad d resses ) . The f i n a l r e g i s t e raddress i s formed a t run t ime by rep lac ing E with the r e g i s t e rpoin te r v a lu e . This mechanism i s handled au tomat ica l ly by th eassembler whenever a working r eg i s t e r d es ig n a to r i s used .The wo rk in g - reg i s t e r mechanism al lows sec t ions o f code usingd i f f e re n t r eg i s t e r - p o in t e r va lues to share a common procedure andpass parameters to it via the working r e g i s t e r s .

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Section 3Assembly Language Instruction Set3 .1 Functional SummaryPLZ/ASM i n s t r u c t i o n s can be div ided fu n c t i o n a l l y in to thefo l lowing e i g h t groups :

Load Ari thmet ic Log i c a l Program Contro l (Branch) B it Manipula t ion (Test ) Block Transfe r Rota te and S h i f t CPU Contro lThe fo l lowing summary shows the i n s t ru c t i o n s belonging to eachgroup and the number o f operands requ i red for each, where "s rc"is the source operand , "ds t" i s the des t ina t ion operand , and "cc"i s a co n d i t i o n code .

In s t ru c t i o nCLRLDLDCLDEPOPPUSH

Load In s t ru c t i o n sOperandsd s td s t , s r cd s t , s r cd s t , s r cd s ts rc

Ari thmet ic In s t ru c t i o n sIn s t ru c t i o n Operands

ADC d s t , s r cADD d s t , s r cCP d s t , s r cDA d s tDEC d s tDECW d s tINC d s tINCW d s tSBC d s t , s r cSUB d s t , s r c

3-1

Name of In s t ru c t i o nClearLoadLoad ConstantLoad External DataPo pPush

Name of In s t ru c t i o nAdd Wi th CarryAddCompareDecimal Adjus tDecrementDecrement WordIncrementIncrement WordSu b t rac t With CarrySubt rac t


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Ins t ruc t ionANDCOMORXOR

Ins t ruc t ionCALLDJNZIRETJPJRRET

Ins t ruc t ionTCMTM

Ins t ruc t ionLDCILDEI

Ins t ruc t ionRLRLCRRRRCSRASWAP

Logical Ins t ruc t ionsOperandsd s t , s r cd s td s t , s r cd s t , s r c

Name of Ins t ruc t ionLog i c a l AndComplementLog i c a l OrLogical Exclusive Or

Program-Contro l Ins t ruc t ionsOperandsd s tr , d s t

c c , d s tc c , d s t

Name of Ins t ruc t ionCal l ProcedureDecrement and JumpI f NonzeroI n t e r r u p t ReturnJumpJump Rela t iveReturn

Bit -Manipu la t ion Ins t ruc t ionsOperandsd s t , s r cd s t , s r c

Name o f Ins t ruc t ionTest Complement Under MaskTest Under Mask

Block-Transfer Ins t ruc t ion

Operandsd s t , s rcds t , s rc

Name o f Ins t ruc t ionLoad Constant AutoincrementLoad Externa l DataAutoincrement

Rotate and S h i f t Ins t ruc t ionsOperand Name o f Ins t ruc t iond s t Rotate Leftd s t Rotate Left Through Carryd s t Rotate Rightd s t Rotate Right Through Carryd s t S h i f t Right Arithmeticd s t Swap Nibbles

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CPU Control In s t ru c t i o n sIns t ruc t ion

CCFDIEINOPRCFSCFSRP

3.2 Notation

Operand

s rc

Name o f In s t ru c t i o nComplement Carry FlagDisable In te r rup t sEnable In te r rup t sNo Operat ionReset Carry FlagSet Carry FlagS e t Regis te r Pointe r

Operands and s t a tu s f l ags are represen ted by a no ta t iona lshor thand in the de ta i l ed ins t ruc t ion desc r ip t ions t h a t make upthe r e s t of t h i s chap t e r . The nota t ion fo r operands (cond i t ioncodes and address modes) and the ac t ua l operands they r epre sen tare as fo l lows :Nota t ion

ccr

R

RR

I r

IR

I r r

IRR

Address ModeCondi t ion CodeWorking r e g i s t e ronlyRegis te r orworking r e g i s t e rRegis te r pa i r orworking r e g i s t e rpa i r

Ind i rec t workingr eg i s t e r onlyInd i rec t r eg i s t e ror workingr eg i s t e rInd i rec t workingr eg i s t e r pa i r onlyIn d i r e c t r e g i s t e rpa i r or workingr eg i s t e r pa i r

Actual Operand/RangeSee condi t ion code list belowRn, where n = 0-15

~ = 0 - 1 2 7 , 240-255 orRn as def ined abovewhere reg i s aneven number in the range

above or a va r i ab le whoseaddress i s even or RRp wherep = 0 ,2 ,4 ,6 14@Rn, where n = 0-15@ r e ~ , where reg i s asdef lned above or@Rn, as def ined above@RRp, where p = 0 ,2 ,4 ,6 14@reg, where reg i s aneven number in the rangedef ined above, or ava r i ab le whose address i seven or @RRp as def ined above

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Nota t ionxDARA

1M

Address ModeIndexed

Direc t AddressRela t i veAddress

Immediate

Actual Operand/Ranger eg(Rn) , where regand Rn a re a s de f inedabo eProgram l ab e l or express ionProgram l ab e l or $ + or -o f f s e t , where the l o ca t i o naddressed must be in th erange +127, -128 bytesfrom the s t a r t of thenext i n s t ru c t i o n# d a ta , where da ta i s anexpress ion

Sta tu s Flags a re represen ted as fo l lows:C Carry f lagZ Zero f lagS Sign f lagV Overflow f lagD Decimal a d j u s t f lagH Half ca r ry f lag

The condi t ion codes and the f lag s e t t i n g s they r ep re sen t a r e :Code

F(blank)ZNZCNCPLMINEEQOVNOVGELTGTLE

MeaningAl ways fa l seAlways t r u eZeroNot zeroCarryNo ca r ryPlusMinusNot equalEqualOverflowNo over f lowGrea te r thano r equalLess thanGrea te r thanLess than orequal

Flag Se t t i n g s

Z 1Z ac 1C aS aS 1Z aZ 1V 1V a(S XOR V) = a(S XOR V) = 1(Z OR (S XOR V))(Z OR (S XOR V))

3-4

a1

Binary0000100001101110011111111101010111100110010011001001000110100010


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Code Meaning Flag Se t t ings BinaryUGE Unsigned g r ea t e r c=o 1111than or equalULT Unsigned l e s s than C=l 0111UGT Unsigned g r ea t e r ( (C=O) & (Z=O) ) 1 1011thanULE Unsigned l e s s than (C OR Z) = 1 0011or equal

Note t h a t some o f the condi t ion codes correspond to i d en t i ca lf lag se t t i n g s : Z-EQ, NZ-NE, C-ULT, NC-UGE.

3 .3 Assembly-Language Instruct ionsIn the remainder o f t h i s sec t ion , Z8 assembly- languagein s t ruc t ions are descr ibed in de ta i l in a lphabe t i ca l o rd e r . Eachdesc r ip t ion inc ludes :

The name of the in s t ruc t ion The binary in s t ruc t ion formats The opera t ion performed by the in s t ruc t ion The s t a t u s f l ags af fec ted by th e in s t ruc t ion The number of machine cycles used to execute th ein s t ruc t ion The number of bytes used by th e in s t ruc t ion A s h o r t example showing the use o f the i n s t r u c t i o n

The desc r ip t ion of each i n s t ru c t i o n ' s opera t ion inc ludes ashor thand summary. In addi t ion to symbols a l ready l i s t ed above,the fol lowing are a lso used in these summaries.SymbolSPPCFLAGSRPIMR

MeaningStack poin te r (con t ro l r e g i s t e r s 254-255)Program counte rFlag reg i s t e r (con t ro l reg i s t e r 252)Regis te r poin te r (con t ro l r e g i s t e r 253)In t e r ru p t mask r e g i s t e r (con t ro lreg i s t e r 251)

Assignment o f a value i s indicated by th e symbol "


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ADCAdd With Carry

ADC ds t , s r cINSTRUCTION FORMATS: mode d s t src

I ooolimodei I d s t I s rc 0010 r r0011 IrI QOOlimOde I 0100 R R0101 R IRI oolimode I 0110 R 1M0111 IR 1M

OPERATION: d s t ( - dst+src+CThe source byte , along with the se t t ing of thecar ry f lag , i s added to the des t ina t ion byte . Ther e s u l t is s tored in th e des t ina t ion loca t ion .

FLAGS: C: Set i f there was a carry from the most s i g n i f i c a n tb i t of the r e su l t ; c leared otherwiseZ: Set i f the r e su l t i s zero ; c leared otherwiseV: Set i f ar i thmet ic overflow occurred; c lea red otherwisS: Set i f the r e su l t i s l e s s than zero; c leared otherwisH: Set i f a car ry from the low-order nibble occurredD: Always r ese t to zeroBYTES AND CYCLES:

EXAMPLE:

d s t s rcr r , I rother combinations 23

cyc les610

I f the r e g i s t e r named SUM con ta ins %16, th e carryflag is se t to one, working r eg i s te r 10 con ta ins%20 (32 dec imal ) , and r e g i s t e r 32 con ta ins %10,the s ta tement

ADC SUM,@RIOw i l l leave the value %27 in reg i s t e r SUM.

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~ D D dd

ADD dst ,srcINSTRUCTION FORMATS: mode dst src

10000 Imode I Idst I src I 0010 r r0011 r Ir10000 Imode II src dst 0100 R R0101 R IR10000 Imode I I dst src 0110 R IM0111 IR IM

OPERATION: dst


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ANDLogical

AND d s t , s r cINSTRUCTION FORMATS: mode d s t s rcI lol lmode II d s t I s rc I 0010 r rDOll r I rI 101 1mode I s r c d s t 0100 R R0101 R IR

10101lmode II d s t I I s rc 0110 R 1MOl l l IR 1MOPERATION: d s t (- d s t AND s rc

The source byte i s l og ica l ly ANDed with th edes t ina t ion by te . The r e su l t i s s to red in th edes t ina t ion l o ca t i o n . The AND opera t ion resu l t sin a one b i t being s to red whenever the b i t smatched in th e two operands are both ones .FLAGS: C: UnaffectedZ: Se t i f r e su l t i s zero ; c leared otherwiseV: Always r ese t to zeroS: Set i f the r e su l t b i t 7 i s s e t ; c leared otherwiseH: UnaffectedD: UnaffectedBYTES AND CYCLES:

EXAMPLE:

d s t s rcr r , I rother combinat ions 23

cycles610

I f the source operand i s the immediate value %7B(01111011) and the reg i s t e r named TARGET contains%C3 ( l lOOOOll) , the s ta tement

AND TARGET, #%7Bwi l l l eave the va lue %43 (01000011) in reg i s t e rTARGET.

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CALL:a11 Procedure

CALL d s t

INSTRUCTION FORMATS: d s tIII 0 1 I 110 I ,-I___ --"'d..::.s-'-t_ _ _ -- ' DA1110110100 I ....__s_t_-- , IRR

OPERATION: SP


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CCFComplement Carry Flag

CCFINSTRUCTION FORMAT:Illlo lUll I

OPERATION: C ( - NOT CThe ca r ry f lag i s complemented; i f C=l, it i schanged to C=O, and vice -ve rsa .

FLAGS: C: ComplementedNo o t h e r f l ags af fec ted

BYTES AND CYCLES:

EXAMPLE:

bytes1

cycles6

I f the carry f lag con ta ins a zero , the s ta tementCCF

wi l l change the zero to one.

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:LR::lear

CLR d s tINSTRUCTION FORMAT: mode d s tIIOlll mode I d s t 00000001 RIROPERATION: d s t


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COMComplement

COM d s tINSTRUCTION FORMAT: mode d s tIaHa Imode I d s t 00000001 RIROPERATION: d s t


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CPCompareCP d s t , s r c

INSTRUCTION1010 I mode I

1010 Imode I

1010 Imode IOPERATION:

FORMATS: mode d s t s rcId s t I s rc I 0010 r r001l r I r

s rc d s t 0100 R R0101 R IRd s t s rc 0110 R IMO l l l IR IM

d s t - s rcThe source byte i s compared to ( sub t rac ted from) thed es t i n a t i o n byte , and the appropr ia te f l ags se taccord ing ly . The con ten t s o f the des t ina t ion byteare unaffec ted by the compar ison.

FLAGS: C: Cleared i f there i s a ca r ry from the most s i g n i f i c a n tb i t o f the r e s u l t ; se t otherwise , indica t ing a borrowZ: S e t i f th e r e su l t i s zero ; c leared otherwiseV: S e t i f a r i thme t i c overf low occurred ; c leared otherwiseS: S e t i f th e r e su l t i s negat ive ; c l eared otherwiseH: UnaffectedD: Unaffected

BYTES AND CYCLES:

EXAMPLE:

d s t s rcr r , I rother combina t ions 23

cyc les610

I f the r e g i s t e r named TEST co n t a i n s %63, workingr e g i s t e r 0 con ta ins %30 (4 8 dec imal ) , and r e g i s t e r48 con ta ins %63, the s ta tementCP TEST, @RO

se t s (only) the Z f l ag . I f t h i s s ta tement i s..followed by "JP EQ, t rue_rou t ine" , th e jumpwi l l be t aken .

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DADecimal Adjust

DA d s tINSTRUCTION FORMAT: mode ds t

10100 Imode II -_d_s_t_-- , 00000001 RIROPERATION: d s t ( - DA d s t

The des t ina t ion byte i s ad jus ted to form two 4-b i tBCD d ig i t s fo l lowing an addi t ion or sub t rac t ionopera t ion . For addi t ion (ADD, ADC), or sub t rac t ion(SUB, SBC), th e fol lowing t ab le i nd ica t e s theoperat ion performed:

Ins t ruc t ion Carry Bits 4-7 H Flag Bits 0-3 Number Carry

ADDADC

SUBSBC

Before Value Before Value Added Afte rDA (Hex) DA (Hex) To Byte DA

0 0-9 0 0-9 00 00 0-8 0 A-F 06 00 0-9 1 0-3 06 00 A-F 0 0-9 60 10 9-F 0 A-F 66 10 A-F 1 0-3 66 11 0-2 0 0-9 60 11 0-2 0 A-F 66 10 0-9 0 0-9 00 00 0-8 1 6-F FA 01 7-F 0 0-9 AO 11 6-F 1 6-F 9A 1

The opera t ion i s undef ined i f the des t ina t ion bytewas not the r e su l t of a va l id add i t ion or sub t rac t ionof BCD d i g i t s .FLAGS: C: Set i f there was a carry from the most s i gn i f i c an tb i t ; c leared otherwise (see t ab le above)Z: Set i f the r e su l t i s zero ; c leared otherwise

V: UndefinedS: Set i f the r e su l t b i t 7 i s s e t ; c leared otherwiseH: UnaffectedD: Unaffected

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DADecimal AdjustBYTES AND CYCLES:

dst bytes2

cyclesR,IR 8

EXAMPLE: I f addition is performed using the BCD values 15 and27, the resul t should be 42. The sum is incorrect ,however, when the binary representat ions are added inthe dest inat ion location using standard binaryari thmetic.010101110001+ 00100011 1100 = %3C

The DA statement adjusts this resul t so that thecorrect BCD representat ion is obtained.0011 1100

+ 0000 01100100 0010 42

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DECDecremenj

DEC ds tINSTRUCTION FORMAT: mode dst10000 Imode II .._d_s_ t_ .... 00000001 RIROPERATION: ds t


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DECWDecrement Word

DECW d s tINSTRUCTION FORMAT: mode d s t

11000 Imode I d s t 00000001 RRIROPERATION: d s t


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DIDisable Interrupts

DIINSTRUCTION FORMAT:

11000 luulOPERATION: IMR(7)


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DJNZDecrement and Jump if Nonzero

DJNZ r , d s tINSTRUCTION FORMAT: d s t1 110 1 a I 1-1_ d _ s _ - - - ' 0000to1111

RA

OPERATION: r


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LD R6, #12LOOP: LD R9,OLDBUF (R6)

LD NEWBUF (R6), R9DJNZ R6, LOOP

D J ~ Decrement and Jump if Nonz4

!Load Counter!!Move one byte to!!New loca t ion!!Decrement and!Loop un t i l counter

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O!


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EIEnable Interrupts

EIINSTRUCTION FORMAT:IloolllllllOPERATION: IMR(7)


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INCIncrement

INC d s tINSTRUCTION FORMAT: mode d s t

I d s t l l l l O I r

10010 Imode I d s t 00000001 RIROPERATION: d s t


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INCWIncrement Word

INCW d s tINSTRUCTION FORMAT: mode d s t

d s t 00000001 RRIROPERATION: d s t


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IRETInterrupt Return

IRETINSTRUCTION FORMAT:

1101111111 1OPERATION: FLAGS ( - @SPSP ( - SP+l

PC ( - @SP

FLAGS:

SP ( - SP+2IMR(7) ( - 1This i n s t ruc t ion i s issued a t th e end o f an i n t e r ru p tse rv i ce rou t ine . I t r es to res the f lag r e g i s t e r(con t ro l r e g i s t e r 252) and th e program co u n t e r . I talso reenab les any i n t e r r u p t s t ha t are p o t e n t i a l l yenab led .A ll f l ags are res to red to o r ig in a l se t t i n g s (beforei n t e r r u p t occurred)

BYTES AND CYCLES:bytes

1cyc les

16

3-25


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JPJump

JP cc ,ds tINSTRUCTION FORMATS:Conditional cc dstI cc Illo 1 I ....____ _s_t_--' 0000tol l l l DAUnconditionalI 01110000 I L-I_d_s_ t _ .... IRROPERATION: I f cc i s t rue , PC ( - d s t

FLAGS:

A condi t iona l jump t r ans fe r s program controlto the designated locat ion i f the conditionspeci f ied by "cc" is t rue . See sec t ion 3 .1for a l i s t of condition codes.The uncondi t ional jump simply replaces thecontents of the program counter with the contentsof the speci f ied reg i s t e r pai r . Control thenpasses to the s tatement addressed by the programcounter .No f l aas affected

BYTES AND CYCLES:

EXAMPLE:

d stDAIRR

bytes32

cycles12 i f jump taken10 if jump not taken8

I f the carry flag is s e t , the s tatementJP C, %1520

replaces the contents of the program counter with%1520 and t r ans fe r s control to tha t locat ion . Hadthe carry f lag not been se t , control would havefa l len through to the statement following the JP .

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JRJump Relative

JR cc , d s tINSTRUCTION FORMAT: cc d s t

cc 110111 ....._ d _ s _ t _ .... 0000to1111RA

OPERATION: I f cc i s t r u e , PC


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LDLoad

LD ds t , s rcINSTRUCTION FORMATS: mode dst src

I dst Imodel src 1100 r 1M1000 r RI ec Imode I I d s t 1001 R* rI mode IDOll I I dst I src 1110 r Irl l l 1 Ir r11110 Imode I s rc d s t 0100 R R0101 R IR11110 Imode I dst src 0110 R 1M0111 IR 1M11111101011 I src dst IR R11100 10111 1 I ds t x I src r X11101 101111 I src x I dst X r

* In th is instance only a ful l reg i s t e r addresscan be used.

OPERATION: ds t ( - src

FLAGS:BY'rES AND

The data specif ied or pointed to by the sourceoperand i s loaded into the des t ina t ion loca t ion .No f lags affected

CYCLES:dst s rc bytes c;tclesr Ir,IM,R 2 6I r , R r 2 6r X 3 10X r 3 10other combinations 3 10

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EXAMPLE:

LDLoad

I f working r e g i s t e r 0 contains %OB (11 decimal) andworking r eg i s t e r 10 con ta ins %83, the s ta tementLD 240(RO), RIO

w i l l load th e value %83 in to r e g i s t e r 251 (240 +11) . Since t h i s i s th e i n t e r ru p t mask r e g i s t e r ,th e Load s ta tement has the e f f e c t o f enabl ingIRQO and IRQl. The con ten t s o f working reg i s t e r10 are unaffec ted by

z8 assembly language programming manual dec80

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