your best power integrity design will be your next …

Heidi Barnes 2019.08.21

SI/PI Applications Engineer / Keysight Technologies

Y O U R B E S T P O W E R I N T E G R I T Y D E S I G N W I L L B E Y O U R N E X T O N E

22

• Overview of current design and test trends

• Power delivery network complexity

• Power rail impedance finds worst case failures

• Target impedance and root cause of ringing on power rail

• Designing for flat impedance

• Power integrity workflow

3

Digital High Speed Electronics Are Everywhere

Every year, designers push new limits:

Faster data rates, lower power, smaller components, higher levels of

integration

Smart Cities

Smart AutomotiveSmart Devices Smart EnergySmart Compute

4

Technology Waves Driving Higher Throughput

Thunderbolt 4 (26 Gbd)

USB 4 (20 Gbps)

GEN 4 HSIO: 4-10 Gbps GEN 5 HSIO: 10-23 Gbps

2016 2017 2018 2019 2020 2021 2022

Current

Computer: PCIe, USB, Thunderbolt

Mobile: C-PHY, D-PHY, M-PHY

Display: HDMI, DP, eDP

Memory: DDR5, LPDDR5, GDDR6

DP 2.0 (10/16 Gbps)DDR 5 (6.4 Gbps)GDDR 6 (16 Gbps)

M-PHY 5.0 (23.3 Gbps)M-PHY 4.1 (12 Gbps) HDMI 2.1 (12 Gbps) LPDDR 5 (6.4 Gbps)

D-PHY 2.1 (4.5 Gbps)

C-PHY 1.2 (3.5 Gbps)D-PHY 3.0 (16 Gbps)C-PHY 2.0 (8 Gbps)

PCIe 5.0 (32 Gbps)

USB 3.2 (10 Gbps x 2)

5

5G Networks Timeline

1B 5G NR Connections0 5G NR Connections

2018 Milestone

Q4: VZ & ATT launch

5G NR Fixed mm-wave

2017 3GPP R15

Dec: 5G NR NSA freeze

(pulled in 6 months)

5G NR

NSA

R14

2017 Milestone

Q4: Verizon Pilots 5GTF 28Ghz Fixed Wireless in 11 cities

2015 2016 2017 2018 2019 20212020 2022

2018 Milestones

Feb: Winter Olympics, S. Korea

Summer: World Cup, Russia

2015 Milestones

Sept: 3GPP 5G Workshop

Nov: ITU WRC 15

2020 Milestone

Jul/Aug: Summer Olympics Japan

2022 Milestone

Summer: 2nd Phase Commercial

R13

You are here

R15

SA

2019 Milestone

Nov: ITU-WRC 19

5G Commercialization

Announcements

• Verizon: FW FR2 Oct 2018

• AT&T: FW FR2 Dec 2018

• T-Mobile: FR1 Late 2019

• Korea: 5G NR March 2019

• DOCOMO: 5G 2020 (Late 2019)

• China Mobile: 5G Early 2020

2023

R15

Late Drop

R16

3GPP 5G “Phase 1” 3GPP 5G “Phase 2”

R17?

6

Design & Test Requirements are Growing Exponentially

20x more

conformance tests

than 4G

Wi-Fi, Bluetooth®

GPS, FM Radio,

4G, 5G,NFC, RFID, Qi

5G NRWireless

Coexistence

EMI/EMC and

Regulatory Test

20+

IEC & European (EN)

Standards

7

F I N A L P R O D U C T M U S T PA S S E M I / E M C R E G U L AT I O N S

Failing EMI is Expensive

Cabling

CISPR Compliance

Conducted Emission Testing

8







9

Modern High Density Electronics

• 1000s of nets

• A web of interconnected point of load power supplies

• 1 ground net

• Barely noticeable on a schematic

• Typically the largest copper net in layout

• Noise path connected to everything

Electrical Schematics vs. LayoutP O W E R I S T H E F O U N D AT I O N T H AT C O N N E C T S T O E V E R Y T H I N G

10

FA S T D E L I V E R Y O F P O W E R AT M I C R O WAV E F R E Q U E N C I E S

Cross Talk

Power ICDC-DC

Power Supply ImpedanceEmission

Immunity

Signal Quality

Tx Rx

BERImpedance

Camera

DDR MemoryPost LVDS(Gbps)

Signal Quality

Reflection

Automotive Ethernet

(100Mbps)

ECU

Noise

ECU

MPU PHYPHY

Power Delivery Eco-System

• Many Point-of-Load power supplies

• Low Voltage, High 𝑑𝐼

𝑑𝑡Switching Loads

• Target Z to reduce broadband 𝐿𝑑𝐼

𝑑𝑡Voltage Noise

• Power Supply Rejection Ration (PSRR)

• DC-DC Converter Switching Noise and Stability

Note: A Point-of-Load (POL) Power Supply is typically a

Switched Mode Power Supply (SMPS) with a Buck Regulator

DC-DC Converter design that the Microprocessor PCB world

often calls as a Voltage Regulator Module (VRM)

Key Take Away:

Power Integrity Engineers

need RF/uW design and

measurement tools!

11

D ATA T X / R X FA I L U R E , O V E R V O LTA G E , E M I / E M C , C R O S S TA L K

Natural

Response

Power Rail

Step

LoadAC Load

Forced

Response

Volts

AmpsLoad CurrentPASS

Datasheet

Design

FAILOver Voltage

Tx/Rx Bit Error

EMI

CrosstalkOld Method:

Step Load

Transient Test

(False Positive)

New Method:

Finding the

worst case Load

𝑉 = 𝐿𝑑𝐼

𝑑𝑡

Key Take Away:

Forced response is

worst case, not the

data sheet step load.

12







13

I M P E D A N C E P E A K S I N T H E F R E Q U E N C Y D O M A I N C A U S E P O W E R R A I L R I P P L E

Impedance Peaks Help Predict

Worst Case Load Transients

Log Scale 10kHz to 5MHz

Imp

ed

an

ce a

t th

e L

oa

d

𝑉𝑟𝑖𝑝𝑝𝑙𝑒 = 𝐼𝑡𝑟𝑎𝑛𝑠𝑖𝑒𝑛𝑡 ∗ 𝑍𝑝𝑑𝑛 Key Take Away:

Voltage Rogue Waves are Real

Forced Excitation at Peak Z Frequencies

Rogue Wave Captured

14

F L AT Z D E C O U P L I N G C A PA C I T O R O P T I M I Z AT I O N

• EM simulation and Measure Based Models Enable Low Z Designs

• Flat Z Optimization Lowers Cost, Reduces Risk of Failures, Maximizes Performance

Decoupling Capacitors

40% Fewer

Components

Fewer solder

joints higher

reliabilityTarget Z

Original

DeCaps

Optimized

DeCap

Design

Imp

ed

an

ce (

Oh

ms)

Frequency (MHz)

Key Take Away:

Flat Z design over

a wide bandwidth

gives the best

performance!

High Density PCB Designs

15







16

TA R G E T Z T I M E S D I / D T C U R R E N T T R A N S I E N T I S T H E V O LTA G E R I P P L E

I

VZ

=Target

Target Impedance Calculation

Max Ripple

Max Transient Load

Voltage

Regulator

Module

VRM

PCB Power

Distribution

Network

PDN

Package +

Die Circuit

LOAD

17

E N E R G Y S W I N G S B E T W E E N T H E L A N D T H E C

𝑉 𝑡 = 𝐿𝑑𝑖

𝑑𝑡𝐼 = න𝐶

𝑑𝑉

𝑑𝑡

Energy stored in

the Magnetic FieldEnergy stored in

the Electric Field

𝐸𝐵 L

𝑍 = 𝑗𝜔𝐿 𝑍 =−1

𝑗𝜔𝐶

Phase V Leads I Phase V Lags I

18

PA R A L L E L I N D U C TA N C E C A N R E S O N AT E W I T H T H E D E C O U P L I N G C A PA C I TA N C E

Zpeak=1.5 Ohms

Zo=250 mOhms

𝑍0 =𝐿

𝐶

𝑄 =𝑍0

𝑅𝑡𝑜𝑡𝑎𝑙

𝑓0 =1

2𝜋 𝐿𝐶

𝒁𝒑𝒆𝒂𝒌 = 𝒁𝟎 ∙ 𝑸

∆𝑉 = ∆𝐼 ∙ 𝑍𝑝𝑒𝑎𝑘

1 Amp

AC Sweep

𝟏

𝝎𝑪𝝎𝑳

Parallel L-C in the PDN

V R LsupplyCbulk

ESRCbulk

ESLCbulk

Cdecap

ESRCdecap

ESLCdecap

Impedance vs. Frequency

1.5 Ohms

20 mOhms6 nH 100 nF

Flat VRM

+6dB/Octave - 6dB/Octave

19







20

D E C O U P L I N G I S R E Q U I R E D T O E X T E N D T H E P O W E R S U P P LY B A N D W I D T H

Step Load Forced

Power Supply

Simple R-L Model

Frequency Domain

Power Supply Output Impedance

Time Domain

Voltage and Current vs. Time

LOG SCALE LOG SCALE for time

R

𝝎𝑳

𝑓𝑠𝑢𝑝𝑝𝑙𝑦

ControlledNo Control

High Z

V R L

PROBLEM

The Load can make the Power

Supply Control Loop go unstable

1st Order SOLUTION

Design for Flat Impedance at the

output to keep V and I in phase

and the feedback stable.

21

D E S I G N I N G F O R F L AT I M P E D A N C E

Step Load Forced

Frequency Domain


Time Domain

Voltage and Current vs. Time

LOG SCALELOG SCALE for time

Target Z

𝝎𝑳𝒔𝒖𝒑𝒑𝒍𝒚

𝑓𝑠𝑢𝑝𝑝𝑙𝑦

Power

Supply

Decoupling

Ideal Bulk C

𝟏

𝝎𝑪𝒃𝒖𝒍𝒌

Flat Z Load

Flat Z Design

R-L Supply

𝐶𝑏𝑢𝑙𝑘 =𝐿𝑠𝑢𝑝𝑝𝑙𝑦𝑍𝑇𝑎𝑟𝑔𝑒𝑡2

V R Lsupply Cbulk

ZtargetPROBLEM

Find the decoupling capacitor that

will maintain a Flat Z Load for the

Power Supply

1st Order SOLUTION

Add Bulk Capacitor to

maintain flat impedance

22

S E L E C T E S R F O R F L AT Z P D N , M I N I M I Z E T H E E S L

Impedance Equation Series RLC Impedance vs. FrequencyCapacitor

Model

Voltage and current are in phase at fcap

phase of V lags I

phase of V leads I

Z𝒁 = 𝑹𝒄𝒂𝒑 + 𝒋𝝎𝑳𝒄𝒂𝒑 − 𝒋𝟏

𝝎𝑪

𝒇𝒄𝒂𝒑 =𝟏

𝟐𝝅 𝑳𝒄𝒂𝒑 × 𝑪

𝒇𝒄𝒂𝒑

𝑹𝒄𝒂𝒑

𝑳𝒄𝒂𝒑

𝑹𝒄𝒂𝒑

23

S M A L L E R C A PA C I T O R S H AV E L O W E R E S L

Adding Decoupling Capacitors to Reduce L

Frequency Domain


LOG SCALE

Target Z

24 mOhms

𝑳𝒅𝒆𝒄𝒂𝒑𝟏875 pH

Flat Z Extended

𝑳𝒅𝒆𝒄𝒂𝒑𝟐100 pH

𝑳𝑽𝑹𝑴15 nH

𝑪𝑫𝒆𝒄𝒂𝒑𝟐1.5 uF

12

3

𝑪𝑫𝒆𝒄𝒂𝒑𝟏16.4 uF

Parallel L-C in the PDN

V R

LFlat_VRM

Cdecap1 Cdecap2

RCdecap2

LCdecap2

RCdecap1

LCdecap1

𝐶𝑑𝑒𝑐𝑎𝑝2 =𝐿𝑑𝑒𝑐𝑎𝑝1𝑍𝑇𝑎𝑟𝑔𝑒𝑡2

=875𝑝𝐻

(24 𝑚𝑂ℎ𝑚)2

≈ 1.5 𝑢𝐹

24

Self-induced [inflicted] noise

External [injected] noise

Power Supply Noise Spec: 10mV pk-pk

Power Supply Noise Limits @ Package Ball

25

PA R A L L E L R E S O N A N C E C A U S E S A N I M P E D A N C E P E A K

Package/Die

DecouplingVRM

Control

No PDN

Decoupling

Step Forced

Time Domain

Voltage and Current vs. TimeFrequency Domain

Impedance at the Package Pin

No PDN

Decoupling

26

I N C R E A S E S PA R T C O U N T T O R E A C H TA R G E T Z

Package/Die

DecouplingVRM

Control

Low ESR 100 uF

Capacitor

Step Forced

Time Domain



Target Z

27

F L AT Z = M A X I M U M S TA B I L I T Y A N D M I N I M U M R I P P L E

Package/Die

DecouplingVRM

Control

Flat PDN

Decoupling

Step Forced

Time Domain



Target Z

28

E N G I N E E R E D D E S I G N V S . C O S T LY D E B U G / R E D E S I G N

History Lesson – The Transatlantic Cable

What is so hard about stringing a wire

between the transmitter and the receiver?

In 1858…signal quality declined rapidly, slowing

transmission to an almost unusable speed. The

cable was destroyed the following month when

Wildman Whitehouse applied excessive voltage

to it while trying to achieve faster operation.

Transatlantic telegraph cable

Where was the SI Engineer in 1858?

29

1. Are your designs still leveraging decade capacitor values?

2. Are poor designs band-aided with added filters and more

capacitors?

3. Where is the PI engineer?

P I E N G I N E E R S R E Q U I R E S I M U L AT I O N A N D M E A S U R E M E N T T O O L S

30







31

W H AT I S T H E P O W E R I N T E G R I T Y W O R K F L O W ?

Key Take Away:

The combined simulation and

measurement of the PI

Ecosystem reduces EMI/EMC

failures

• Designers often leverage designs and wait until measurement to debug

• Current industry workflow starts at post-layout, need to move to pre-layout

• Combined power integrity + power electronics covers both delivery and generation of power

Create Model Library

Pre-Layout Schematic Simulation

Post Layout PDN EM

Simulation

PI Ecosystem Schematic Simulation

ADS MeasurementsADSPIProADS

Measured Models Power Rail Ripple

Clock Jitter

EMI/EMC Noise

32

EM Simulation with PIProLayout

P D N E X A M P L E O F PA R A L L E L I N G 5 C A PA C I T O R S

33

Parallel Capacitors SPICE vs PCB EM Model

Single Capacitor EM Model

Distributed EM Model

Paralleling same value caps

Lumped SPICE Model

L U M P E D S P I C E M O D E L G E T S I T W R O N G

34

C ESR ESL

C1 1 uF 7 mΩ 300 pH

C2 0.10uF 15 mΩ 300 pH

C3 0.01uF 30 mΩ 300 pH

C4 0.001uF 100 mΩ 300 pH

C5 100pF 200 mΩ 300 pH

Capacitor Loading by the Decade

Z at Load vs. Z at VRM

At the Load

EM Model

At the VRM

EM Model

At Load and VRM

Lumped SPICE

Z AT T H E L O A D I S N O T T H E S A M E A S Z AT T H E V R M

35

E A S Y S E T U P F O R H I G H P O R T C O U N T S I M U L AT I O N S

1) IMPORT THE PCB

• Select VRM, Sink, Nets, Components

• Run EM AC Frequency Sweep 2) OPTIMIZE DECOUPLING

• Select capacitor models

• Setup optimization goals

• Run Optimization 2) GENERATE SCHEMATIC

• Auto generate schematic

with PCB PDN EM model

and optimized capacitors.

Target Z

36

K E Y S I G H T Y O U T U B E V I D E O W I T H P I C O T E S T

How to Video

http://tinyurl.com/vrm-video

http://tinyurl.com/vrm-video

37

V R M + P D N + L O A D = P I E C O S Y S T E M

38

S M A L L S I G N A L A C A N D L A R G E S I G N A L S W I T C H I N G R I P P L E

Faster than Transient

Copyright © 2019 Keysight Technologies, Picotest.com, and Xilinx

ADS Schematic + Data Display

39

E5061B for measuring

micro-Ohms of

ImpedanceInfiniium Scope for Realtime

Power Rail DiagnosticsCX33000 Current Analyzer for

Load Transient Diagnostics

PathWave ADS PI Eco-System Simulations

Pre-Layout and Post Layout PE Next Generation GaN

Reaching for 99% Efficiency

MHz Switching

Doubling the Power Density

> 1000 W/in3

Picotest Accessories

PWR5061B PI Bundles

PathWave ADS PIPro

EM Models for DeCap Optimization

40

D E S I G N M E T H O D O L O G Y F O R D E C A P O P T I M I Z AT I O N


1. Calculate 1st order approximations

2. Decoupling capacitor optimization requires a Target Z input

3. Power Integrity Eco-System includes switching VRM models

𝐶𝑏𝑢𝑙𝑘 =𝐿𝑠𝑢𝑝𝑝𝑙𝑦𝑍𝑇𝑎𝑟𝑔𝑒𝑡2 𝐶𝑑𝑒𝑐𝑎𝑝 =

𝐸𝑆𝐿𝐶𝑏𝑢𝑙𝑘𝑍𝑇𝑎𝑟𝑔𝑒𝑡2

Max 𝐿𝑃𝐷𝑁 = 𝐶𝑝𝑘𝑔 ∗ 𝑍𝑇𝑎𝑟𝑔𝑒𝑡2

41

How to Design for Power Integrity5 Part Series on YouTube

with PI expert Steve Sandler

42

Basics – Instructor Led Demo

Transceiver Turn-on with ideal R-L PCB PDN

Frequency Domain Impedance and Time Domain Excitation for

ripple

Explore –

Package Model Impedance

Impedance at Package Pin vs. Die

Advanced –Tune C_total for a given Target Z profile


42

your best power integrity design will be your next …

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