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Summary on ‘what is edaBarCamp’ and the ‘Rules of BarCamp’:

- edaBarCamp:

https://www.edabarcamp.de/what-is-bar-camp

Hints for the documentation:

Agenda / Session Wall:

Suggestions for the Evening-Event:

Wirtshaus Christoffel

https://www.wirtshaus-christoffel-erfurt.de

Michaelisstr. 41, 99084 Erfurt

Tel. +49 (0) 361 - 26 26 943

Vaulted cellar with medieval atmosphere Traditional german food, dark beer and vine

‚DoubleB‘

http://www.doubleb-erfurt.de

Marbacher Gasse 10, 99084 Erfurt

Tel. +49 (0) 361 - 211 51 22

Open bar atmosphere

Burger, steaks, salad & Co.

Guinness, beer and vine

Evening-Event (Decision): 19:30 at “DoubleB” → does unfortunately not work!!!

⇒ We meet at Dubliner’s http://dublinererfurt.de/

⇒ Take Tram to Erfurt Anger and walk to Neuwerkstraße 47

https://goo.gl/maps/5hAzFqPdXjR2

Session:Circuits in NN

● Introducing NNs

● Problem: How to feed Circuits to a NN? “Embedding”

● We need some thing like Word2Vec! -> this enabled all other research in text

processing

● Goals: e.g. Structure Recognition, other things?

● How to vectorize a circuit?

● Christoph:

○ Start from a Graph

○ Constructing some kind of incidence matrix of the circuit -> defining some

ordering is difficult

■ Rank approach L0 for finding submatrix?

● [Picture]

● Christian:

○ type of device, width, length etc. are important, not only structure

● Gregor:

○ [Picture]

○ Augmenting incidence matrix with these things

○ types of branches for S-D, G-S and so on

○ “virtual Nodes” for parallel branches

● Problem of sparsity

[Picture]

Session: AMS Coverage

● Specification Driven Functional Coverage for Analog Mixed Signal Systems

● Slides:

○ Motivation

○ Proposal

○ Overall Methodology (Flow)

○ LNA Example

● Discussion:

○ How to determine step size/resolution?

○ General solution or target a specific design class (e.g., filters)

○ How to determine the “most valuable” tests from the stimuli?

Session: VLSI Teaching

Task for the university

● Provide an overview for the process

○ “Map” the area to help reading the manuals

Problems

● Sometimes outdated methods at universities (Who writes Karnaugh-plans today

(apart from students)?)

● Availability of Toy-Tools to under-grad students

○ Open-Source-Tooling as used by efabless could be a solution

Ideas:

● Student-Packages of Software

○ Closed Cloud-based solutions

● Summer-school training for VLSI Design

● Student competitions like Invent-a-Chip

● Involve experts from companies in teaching

Session: AMS Architecture

● How to apply software design principles to hardware design:

● Some Ideas:

○ [Image]

● Ideas for general guidelines

○ Amplification before Attenuation

○ Testability?

■ influences load-conditions

○ Work with signal ranges => Signal plan

○ Separate VDD and VSS for

■ Analog

● Signal-Domain

● High-Power-Domain

■ Digital

● several power domains

■ Take care of parallel regulators, they might oscillate

○ control rates

■ slew-rate

■ filtering

○ Unit-Testing?!

■ Some people tried it

■ Domain separation => Stay in one domain for a unit-test

Georgs Plan:

● SRP

● not more than 5 blocks per layer

● A/D Power-Domain separation (+sensitive Domain if needed)

● As less clock domains as possible

● FF at input of digital blocks

● Each block should be tested seperately

● Test startup!

Session: Automated Modeling

● Introduction: transistor-level to behavior-level

● Why? -> Speedup

● Where are the differences between Electrical domain und wreal domain.

● Which Languages are you Using? System-AMS, VerilogAMS

● How to build such a model?

○ Bottom Up Characterization

○ -> is time consuming

● Models are often only functional, e.g. f(x,u)=y or state machine

1. Adding missing properties:

● e.g. Energy consumption, Operating condition dependency

● Enery Consumption I_VDD= f(u(t),y(t),x(t))

○ Idea: learn the structure? -> machine learning is hot topic

○ Different challenges:

■ Sampling

■ Dataset preparation

2. Modeling the full thing?

● Recurrent Networks RNN, LTSM?

Session: Multi-Logic Design

● Short introduction to the Application Background

● Overview of the Chip Architecture in BiCMOS Technology

● Introduction to the special logic cell design mixing CMOS and PECL logic

● Introduction to power saving aspects: partial cell shutdown via CMOS switches

● Discussion on implementation aspects

● Question: How to assist implementation with eda methods?

○ Problem: Differential routing in cadence → probably no ready-made solution

○ Problem: Multi-Logic design (CMOS, PECL) → how to verify timings

automatically? → unknown if there exists an applicable workflow

○ Problem: How to ensure init states during power-on?

○ Best way is to stress more a hierarchical description and do manual

implementation (and manual timing verification)

● “How to brick the chip in five easy steps -- a guideline”

○ Mix up connections

○ Disregard IR Drop for the worst case

○ Disregard temperature hotspots

○ Check biasing differences in warmer Areas (add extra bias cells)

○ Save on timing headroom (aim for ~10% … 100ps extra)

○ Disregard power-on sequencing

○ Forget some details with timings

Session: IIP Generator

● Short introduction to Generator based Design

Link to Cadence Schematic Model Generator (SMG) tutorial:

https://www.cadence.com/content/cadence-

www/global/en_US/home/multimedia.html/content/dam/cadence-

www/global/en_US/videos/tools/system_design_verification/analog_behavioral_model

ing

Session: Day-1-Feedback

1.) my best like / worst dislike was:

Like:

● Good possibility for discussion in Groups

● Round Table and informal structure

● Different backgrounds of participants

● networking

● good informations for newbies

● personal discussions

● Focus on AMS

● discussions deep in the topics → makes sometimes the swap-in difficult

● Open-Minded Setting

● self-organization

● Platform for scientific collaboration

dislike: no dislikes

2.) did you like the activity level? have you been 'active enough'?

Overall activity level:

● Like: many / everybody

Own activity:

● good: ~ ⅔

● can improve: 2-3

3.) what would be your suggestion to improve?

● Extend coffee breaks (for brain recovery)

● Setting focus topics seems to be a good idea

● Collect Session ideas before the bar-camp

● More Information on the Session-Wall

● Different modes for the two days?

○ First: presentation

○ Second: discussion (after a night of thinking)

● Continuity between BarCamps

○ What was going on during the last barcamps?

Session: edaBarCamp 5G?

● Would you participate in an edaBarCamp again? Why?

○ Like discussion with colleagues -- but with a broader spectrum, people with

different background, knowledge

● What would help for participation?

○ Finding your collaborators outside of your office

○ Management summary on the webpage

● What would help for invitation?

● Change the “mode of operation?”

○ keep the spontaneous factor

○ Two blocks?

■ Free Sessions (original BarCamp-Mode)

■ Pre-Selected Sessions

○ (Published) Proceedings to show at home

● Topic discussions before BarCamp

● Webpage

○ It’s unclear, what will happen here.

○ Text should encourage people to propose topics

● Google-Forms based feedback

○ make public

● Select Topic-of-Interest at the registration

○ + Possibility to add your own

● Summary of the topics of last BarCamp at homepage (front-page)

○ Headlines, example session-log

● Name-Change? Should we avoid the name BarCamp, Pro:2 (of 9)

● Should we have a track for pre-scheduled/pre-selected Sessions?

○ Pro 9 / 9

○ at least a 15 + 45 format? Alternative: 10+50

○ Posters (Possibility) and pose a slide-limit for Power-Point (e.g. 3 slides)

● Who wants to join the organizers groups?

○ Christoph

○ Christian?

● Urgent Hints

○ Fix Forum

○ Short description of Concept

○ Information about what can be expected from the event, example-pitches

○ Convince our bosses to invite their phd-students

Session: CRAVE for AMS /Cluster Fuzzing

Summary: CRAVE for AMS

Slides:

● Motivation

● Constrained Random Verification Environment

● Constraints definition

○ Parameter constraints

○ runtime constraints

● Parallel simulation framework

● DC-DC converter example

Discussion:

● How to define precision

● Which distributions are helpful?

● applications in other domains

○ yield testing

Session: AMS FPGA Simulation

Paper from SMACD 2017 on FPGA based simulation

https://ieeexplore.ieee.org/document/7981562/citations?tabFilter=papers#citations

Session: CBD for Mixed Domain Modeling

Session: Social Media in EDA / Open Science

14 Questions to 15 participants:

1. Do you use social media?:

2. Which platforms you use?

3. Do you generate (scientific) social media content?:

4. Why don’t you use social media for scientific communication?

- no time, too busy

- no use

- too much competition with other content

problems:

→ interest vs. effort

→ attractiveness of the content

→ reach/audience-size vs. content-orientation

5. Do you consider public relations via social media to be important for EDA

(science)?

6. Do you know ‘open science’ (concepts, platforms, methods)?

7. Have you seen/used open science methods in EDA?

8. Do you use www.arxiv.org?

9. Which kinds of ‘bad reviews’ have you received for your publications?

10. Which kinds of ‘good reviews’ have you received for your publications?

11. Who would prefer a ‘fully open’ review process?

12. Who would prefer an anonymous approach of ‘rebuttle’?

13. Who has already been reviewing other papers?

14. Who likes (vs. dislikes) reviewing?

15. Who likes (vs. dislikes) the idea of ranking (grades) for reviewers?

Session: Day-2-Feedback

1. Who received new ideas, promising hints and unknown knowledge during the

sessions?

2. Open Feedback in addition to day 1:

- more participants would be better:

→ more topics

→ increased possibility to more easily go into deeper discussions

- everyone should follow rule 1: ‘talk about (eda)barcamp’!

- informal character of the event is great → should not change!