xilinx xtp304 – vc7222 schematics (rev. c) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14...

73
of Sheet Date: Title: Ver: A B C D 1 2 3 4 D C B A 4 3 2 1 Sheet Size: B Rev: Drawn By MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT THE DOCUMENTATION IS DISCLOSED TO YOU “AS-IS” WITH NO WARRANTY OF ANY TO CHANGE THE DOCUMENTATION WITHOUT NOTICE AT ANY TIME. XILINX ASSUMES YOU MAY NOT REPRODUCE, DISTRIBUTE, REPUBLISH, DOWNLOAD, DISPLAY, POST, THE DEVELOPMENT OF DESIGNS TO OPERATE WITH XILINX HARDWARE DEVICES. AND/OR SPECIFICATION (THE “DOCUMENTATION”) TO YOU SOLELY FOR USE IN XILINX IS DISCLOSING THIS USER GUIDE, MANUAL, RELEASE NOTE, SCHEMATIC, XILINX EXPRESSLY DISCLAIMS ANY LIABILITY ARISING OUT OF YOUR USE OF BUT NOT LIMITED TO, ELECTRONIC, MECHANICAL, PHOTOCOPYING, RECORDING, OR OTHERWISE, WITHOUT THE PRIOR WRITTEN CONSENT OF XILINX. THE DOCUMENTATION. XILINX RESERVES THE RIGHT, AT ITS SOLE DISCRETION, NO OBLIGATION TO CORRECT ANY ERRORS CONTAINED IN THE DOCUMENTATION, OR TO ADVISE YOU OF ANY CORRECTIONS OR UPDATES. XILINX EXPRESSLY DISCLAIMS ANY LIABILITY IN CONNECTION WITH TECHNICAL SUPPORT OR ASSISTANCE THAT MAY BE PROVIDED TO YOU IN CONNECTION WITH THE DOCUMENTATION. KIND. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DOCUMENTATION, INCLUDING ANY WARRANTIES OF CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR USE OF THE DOCUMENTATION. DISCLAIMER: SCHEM, ROHS COMPLIANT MGT CHARACTERIZATION BOARD RN TEST P/N: TSS0XXX COVER SHEET OR TRANSMIT THE DOCUMENTATION IN ANY FORM OR BY ANY MEANS INCLUDING, HW-V7H-VC7222 VIRTEX-7 HCG1155 ASSY P/N: 0431710 PCB P/N: 1280636 SCH P/N: 0381469 C 73 VC7222 V7 HCG1155 MGT CHAR 01 12-14-2012_16:02 1

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Page 1: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT

THE DOCUMENTATION IS DISCLOSED TO YOU “AS-IS” WITH NO WARRANTY OF ANY

TO CHANGE THE DOCUMENTATION WITHOUT NOTICE AT ANY TIME. XILINX ASSUMES

YOU MAY NOT REPRODUCE, DISTRIBUTE, REPUBLISH, DOWNLOAD, DISPLAY, POST,THE DEVELOPMENT OF DESIGNS TO OPERATE WITH XILINX HARDWARE DEVICES.AND/OR SPECIFICATION (THE “DOCUMENTATION”) TO YOU SOLELY FOR USE INXILINX IS DISCLOSING THIS USER GUIDE, MANUAL, RELEASE NOTE, SCHEMATIC,

XILINX EXPRESSLY DISCLAIMS ANY LIABILITY ARISING OUT OF YOUR USE OF

BUT NOT LIMITED TO, ELECTRONIC, MECHANICAL, PHOTOCOPYING, RECORDING,OR OTHERWISE, WITHOUT THE PRIOR WRITTEN CONSENT OF XILINX.

THE DOCUMENTATION. XILINX RESERVES THE RIGHT, AT ITS SOLE DISCRETION,

NO OBLIGATION TO CORRECT ANY ERRORS CONTAINED IN THE DOCUMENTATION, ORTO ADVISE YOU OF ANY CORRECTIONS OR UPDATES. XILINX EXPRESSLYDISCLAIMS ANY LIABILITY IN CONNECTION WITH TECHNICAL SUPPORT ORASSISTANCE THAT MAY BE PROVIDED TO YOU IN CONNECTION WITH THEDOCUMENTATION.

KIND. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, ORSTATUTORY, REGARDING THE DOCUMENTATION, INCLUDING ANY WARRANTIES OF

CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES,OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY

INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR USE OFTHE DOCUMENTATION.

DISCLAIMER:

SCHEM, ROHS COMPLIANT

MGT CHARACTERIZATION BOARD

RN

TEST P/N: TSS0XXX

COVER SHEET

OR TRANSMIT THE DOCUMENTATION IN ANY FORM OR BY ANY MEANS INCLUDING,

HW-V7H-VC7222VIRTEX-7 HCG1155

ASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469

C

73

VC7222 V7 HCG1155 MGT CHAR

01

12-14-2012_16:02

1

Page 2: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

SHT XX

CONNECTORSHT XX

PMBUS

INTERFACE

5V & 3.3V

12V

SHT XX

SHT XX

SHT XX

SHT XXSHT XX

POWER MONITORING

SHT XX

USER CLOCKS

LEDS

PUSH BUTTONSDIP SWITCHES

I2C BUS MANAGEMENT

CONNECTORPMBUS CABLE

POWER IN 12V

PMBUS

SELECT I/O TERMINATION /

5V

3.3V

2.5V

INTERFACE 5V & 3.3V

12V

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

UTILITY POWER

ON-BOARD REGULATION:

5.0V @ 10 AMPS

DUT POWER

SAMTEC BULLSEYETEST CHANNELS

VCCBRAM 1.0V @ 10 AMPS

ON-BOARD REGULATION:

SHT XX

SHT XX

SHTS 24-27

SHT XX

SHT XX SHT XX

SHT XX

SHT XX

SHT XX

USB / UART

SHT XX

XADC

SHT XX

SYSTEMACE-2

SUPERCLOCK-2 MODULE INTERFACE

VCCAUX 1.8V @ 10 AMPSVCCAUX_IO 1.8V @ 10 AMPS

SHT XX

SHT XX

SHT XX

AFX SIDEBAND CONN

SHT XX

PMBUS

BLOCK DIAGRAM

FMC INTERFACE

VCCINT 1.0V @ 40 AMPS

3.3V @ 20 AMPS2.5V @ 20 AMPS

VCCO

VTT JACKS

SHT XX

HCG1155VIRTEX-7H

SHT XX

(FMC1, FMC2)

113114115213214 SHT XX215

GTH QUADS

SHT XX300

GTZ QUAD

GTZ & GTH

GTZ POWER MODULE

GTH POWER MODULE

PMBUS

GTZ JTAG

POWER PROBECONNECTORS

VCCO_HP 1.8V @ 10 AMPSVCCO_0 1.8V @ 6 AMPS

12-14-2012_16:02 C

01

2 73

VC7222 V7 HCG1155 MGT CHAR

Page 3: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

NOTES:

SHT 4

FMC1_TDI

TDI

TDO

TDI

TDO

JTAG CABLE

TDI

TDO

TDI

TDO

J1

CFGTDOTDI

TDO CFGTDI

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

JTAG CHAIN

JA2JA3

J112

U32 U1

J123J124

AFX TEST SYSTEMJA1

FMC1_TDI

CONNECTOR U23

SHT 4

SHT 4

SHT 24

SHT 52

SHT 48

SHT 56

FMC2 FMC1

SYSTEMACE-2 FPGA

J134J135

REMOVE JUMPERS WHEN BOARD IS INSTALLED ON AFX2 MOTHERBOARD

NEEDS TO BE UPDATED

733

VC7222 V7 HCG1155 MGT CHAR

01

C12-14-2012_16:02

1

1

Page 4: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

GND

I0

I1

S

VCC

Y

74LVC125A

VCC

GND

TSSOP_14

4Y

3Y

2Y

1Y

3OE_B

4A

4OE_B

2A

1OE_B

1A

3A

2OE_B

GPIO2_SRST

GPIO0

GND1

GND2

TCK

TDI

VREF

TDO

TMS 3V3

GPIO1

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

2 PLACES

JTAG DRIVER

EMBEDDED USB-JTAG MODULE

4 PLACES

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

MAIN BOARD JTAG CABLE CONNECTOR / JTAG DRIVER

JTAG CONNECTORS & DRIVERS

JTAG CHAIN SELECTIONJUMPER ON: FMC MODULES, SYSTEMACE-2 AND FPGAJUMPER OFF: SYSTEMACE-2 AND FPGA ONLY

JTAG HEADER

12-14-2012_16:02 C

01

VC7222 V7 HCG1155 MGT CHAR

4 73

FMC2_TDO

CABLE_TDI

2 1

R163

2 1

R137

2 1

R136

2 1

R135

101/10W

GND

UTIL_3V3

GND

11

9

1

7

2

3

6

5

4 8

10

U57

DIGILENT_USB_JTAG2

UTIL_3V3

UTIL_3V3

1 23 45 67 89 1011 1213 14

J1

87832-1420

14

7

11

8

6

3

10

12

13

5

1

2

9

4

U23GND

2

1 R20210.0K1/10W

UTIL_3V3

UTIL_3V3

2

1R16910.0K1/10W

2

1R168

1

2

J112

GND

1

225V0.1UFC98

GND

UTIL_3V3

GND

CABLE_TDI_RCABLE_TDO_R

CABLE_TDO

CABLE_TCK_R

CABLE_TCK

CABLE_TMS_R

CABLE_TMS

NC

NC

NC

NC

FMC_TCK

FMC_TMS

FMC1_TDI

NC

NC

UTIL_3V3

GND

2

3

1

6

5

4

U7SC70_6

NC7SV157

SYSACE_TDI

Page 5: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

GND

GND

A1

A2

B1

B2

DIR1

DIR2 1GND

OE_B

VCCA VCCB

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

1A1

1A2

1B1

1B2

1DIR

2A1

2A2

2B1

2B2

2DIR

VCCA VCCB

1OE_B

2OE_B

GND GND

RESET

4 PLACES

NOTES:

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

INSTALL SHUNT TO ENABLE ACCESS VIA MACGRAIGOR JTAG CONNECTOR

MACGRAIGOR JTAG CONNECTOR

GTZ MANUAL

MACGRAIGOR JTAG CONNECTOR / LEVEL TRANSLATION / GTZ RESET PUSHBUTTON

12-14-2012_16:02 C

01

VC7222 V7 HCG1155 MGT CHAR

5 73

VCCO_HP_EXT

6

7

15

14

4

8

9

13

12

5

10 11

3 2

1

16

U47 QFN_RSV_16

SN74AVC4T245

MAC_TCK

MAC_JTAG_TCKMAC_JTAG_TMS

MAC_JTAG_TRST

FMC2_LA10_P

MAC_JTAG_TDO

MAC_JTAG_TDI

FMC2_CLK0_M2C_P

FMC2_LA12_N

UTIL_3V3

FMC2_HB05_P

1234567891011121314

J3

N3314-6603RB

FMC1_LA00_CC_P

2

1 R31110.0K1/10W

MAC_JTAG_ENABLE_B

2

1R3191.00K1/16W

1

2

1 R16010.0K1/10W

UTIL_3V3

GND GND

1

225V0.1UF

C24

1

225V0.1UFC126

UTIL_3V3

8

9

5

4

10

3

2

7 6

U17 QFN_RSW_10

SN74AVC2T245

GND

2

1R3181.00K1/16W

GND

1

225V0.1UF

C6

NC

UTIL_3V3

1

UTIL_3V3

2

1

R309

2

1R310

2

1

R312

2

1R314DNP

UTIL_3V3

1

225V0.1UF

C30

GND

GND

GND

2

1 R31310.0K1/10W

2

1R31710.0K1/10W

UTIL_3V3

1

2

J6

GND2

1R3281.00K1/16W

GND

21

SW9

EVQ-11L07K

VCCO_HP_EXT

2

1 R50210.0K1/10W

Page 6: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

P

GND

GND

GNDGND

GND

P

GND

GND

GND

VCCBVCCA

SCLA

SDAA SDAB

SCLB

GND OE

GND

VCCBVCCA

SCLA

SDAA SDAB

SCLB

GND OE

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

P

COM1

COM2

COM3

COM4

GND

NC1

NC2

NC3

NC4

NO1

NO2

NO3

NO4

SEL12SEL34

VCC

IN_N

IN_P

VOUT

VS_P

VS_N

OP AMP

GNDNC

NO

SEL

VCC

COM

4 PLACES

PMBUS ACCESS

MANUAL

AFX MB

INHIBIT

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

PMBUS LEVEL TRANSLATION

PMBUS LEVEL TRANSLATION

4 PLACES

SHUNT 1-2 AFX ENABLE, SHUNT 2-3 DUT ENABLE

NOTES:

736

VC7222 V7 HCG1155 MGT CHAR

01

C12-14-2012_16:02

1

3

2

J64

4

6

5

2

1

3

U20

TS5A3159A

DUT_MBDETECT_3V3_B

1

1

4

3

1

5

2

U12

AD8615

4

12168

151357911

13

10

2

14

6

U3

TS3A44159

TP12

PMBUS_CTRL

2

1R173

2

1

R172

2

1

R171

10.0K1/10W

81

2

3 6

7

4 5

U30

PCA9517

81

2

3 6

7

4 5

U29

PCA9517

1

3

2

Q4NDS331N

UTIL_3V3

UTIL_3V3

1

2

C13247UF10V

UTIL_3V3

TP11

21

R257

21

R256

21

R255

21

R252

01/10W

1

2

C250.1UF25V 2

1R16210.0K1/10W

2

1R16110.0K1/10W

UTIL_3V3UTIL_3V3

UTIL_3V3

PMBUS_DATA

PMBUS_CLK

PMBUS_ALERT

AFX_PMB_REF

DUT_PMB_CTRL

DUT_PMB_ALERT

DUT_PMB_DATA

DUT_PMB_CLKAFX_PMB_CLK

AFX_PMB_DATA

AFX_PMB_ALERT

AFX_PMB_CTRL

2

1R174

TP13

VCCO_HP_EXT

UTIL_3V3

2

1R17010.0K1/10W

DUT_MBDETECT_3V3_B

Page 7: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

12VDC

GND

GND

B CB

CG3PSGCG2CG1

GND

GND

EPAD

EN2

EN1

TH1

TH0

VCC

CRESET

CDLY2

CDLY1

RST_B

OUT2

OUT1IN1

IN2

GND

TOL

MR_B

GND

GND

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

COM

N/C

12V

12V

N/C

COM

12V

5V

COM

COM

GND

GNDGND

GND

GND

NOTES:

FILTER

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

12V MAIN POWER IN

PLACE FAN POWER CONNECTOR WITHIN 9-INCHES OF DUT

INHIBITPOWER 3 PLACES

FAN POWER CONNECTOR

ATX 4-PIN MINI-FIT

POWER SUPERVISORY

NOISE SUPPRESSION6-PIN MINI-FITAC ADAPTER (BRICK)

POR_B2 USED BY UTILITY REGULATORS (VCC5V0, VCC3V3, VCC2V5)POR_B1 USED BY UCD9248 POWER CONTROLLERS AND REGULATORS

12V INPUT (EURO-MAG)

MASTER POWER-ON (12V)SLIDE SWITCH

INPUT POWER CONNECTORS / POWER SUPERVISORY / MASTER POWER SWITCH

FPGA INPUT POWER(EURO-MAG)

737

VC7222 V7 HCG1155 MGT CHAR

01

C12-14-2012_16:02

2

1

2

3

J121

22_11_2032

VCCO_HP_EXT

VCCINT1_EXT

VCCAUX_IO_EXT

VCCAUX_EXT

VCCBRAM_EXT

INPUT_GND

INPUT_GND

1

2

C30.068UF10V

1

2

C41

2

C2

0.1UF25V

POR_B2

2

1R3710.0K1/10W

1

1

32

Q19

NDS331N460MW

2

1R34110.0K1/10W

2

1R3810.0K1/10W

VCC12_P

1

2

1

2

3

4

J131

1

4

3

6

2

5

J2

1

32

4

65

SW1

1201M2S3AQE2

NC

NCNC

NC

NC

1

2

C73147UF10V

2

1 R3910.0K1/10W

1

2

C10.1UF25V

VCC12_P

NC

17

7

6

8

9

1

14

15

16

12

10

112

3

5

4

13

U42 TQFN_16

MAX16025

2

1R3001.00K1/16W

AFX_UCD9248_RST

UTIL_3V3

POR_B1

1

2

J27

1 8

5367

U8 50MOHM

1

2

C1181UF25V

VCC12_P

INPUT_GND

VCC12_P_SW

INPUT_GND

13

24

J12

65A

VCC12_P_IN

INPUT_GND1

3

2

4

5

6

7

8

10

9

11

12

13

14

J75

VCCINT2_EXT

VCCO_0_EXT

VCC12_P

NC

Page 8: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

GND

GND

GND

A Y

OE_B

VCC

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

GNDGNDGND

GND GND GND

GND

GNDGNDGNDGNDGND

GNDGND GND GNDGND

GND

GRN

RED

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

VCCAUX_IOVCCINT VCCAUX VCCBRAM

MASTERPOWER

UTIL_3V3 UTIL_5V0

POWER STATUS LEDS

UTIL_2V5

POWERGOOD

VCCO_HP

2 PLACES

FPGA POWER STATUS LEDS

VCCO_0

738

VC7222 V7 HCG1155 MGT CHAR

01

C12-14-2012_16:02

VCCO_HP_EXTVCCAUX_IO_EXTVCCBRAM_EXTVCCAUX_EXTVCCINT1_EXT

PGOOD

GND

GND

UTIL_3V3

UTIL_3V3

21

R385

21

R2

2611/10W

34

1 2

DS12

LED-GRN-RED

UTIL_3V3

2

1

DS6

1

32

Q11

NDS331N460MW

1

32

Q1

NDS331N460MW

1

32

Q2

NDS331N460MW

13

2

Q3

NDS331N460MW

1

32

Q6

NDS331N460MW

1

32

Q7

NDS331N460MW

1

32

Q8

NDS331N460MW

1

32

Q9

NDS331N460MW

1

32

Q10

NDS331N460MW

VCC12_P

2

1 R72611/10W

2

1 R62611/10W

2

1 R52611/10W

2

1 R42611/10W

2

1 R32611/10W

2

1 R92611/10W

2

1 R102611/10W

2

1 R112611/10W

2

1 R122611/10W

2

1

DS5

2

1R581.00K1/16W 2

1R591.00K1/16W 2

1R601.00K1/16W 2

1R611.00K1/16W 2

1R631.00K1/16W

2

1

DS22

1

DS32

1

DS4

2

1

DS8

2

1R641.00K1/16W

2

1R571.00K1/16W

2

1R671.00K1/16W 2

1R661.00K1/16W 2

1R651.00K1/16W

2

1

DS112

1

DS102

1

DS9

UTIL_2V5 UTIL_3V3 UTIL_5V0

UTIL_3V3

3

2 4

1

5

U60 SC70_5

NC7SV125

2

1R4410.0K1/10W

UTIL_3V3

GND

1

32

Q21

NDS331N460MW

2

1 R3272611/10W

2

1R3261.00K1/16W

2

1

DS30

VCCO_0

Page 9: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

GND

A Y

OE_B

VCC

S1

E_B

VEE

A3

A1A0

A2

A4A5A6A7

GND

S0

S2

A

VCC

GND

GND

S1

E_B

VEE

A3

A1A0

A2

A4A5A6A7

GND

S0

S2

A

VCC

AGND1

AGND1

AGND1

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

2 PLACES

POS 2-3: UCD9248 ALWAYS ONPOS 1-2: TI PMBUS CABLE

OFF: AFX

2 PLACES

PMBUS CTRL SELECT

4 PLACES

RESPECTIVE REGULATOR MUST BE DISABLED. TO DISABLE AIF A RAIL IS BEING SOURCED FROM AN EXTERNAL SUPPLY THECAUTION:

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

REGULATOR, PLACE ITS SWITCH IN THE OPEN POSITION.

2 PLACES

NOTES:

TEMP MUX / REGULATOR DISABLE / PMBUS CONN

PMBUS CONNECTOR / FPGA REGULATOR DISABLE / DIGITAL POWER TEMP SENSOR MUX

TI PMBUS CONNECTOR

FPGA REGULATOR DISABLE

TEMPERATURE SENSOR MUXCONTROLLER #1

TEMPERATURE SENSOR MUXCONTROLLER #2

739

VC7222 V7 HCG1155 MGT CHAR

01

C12-14-2012_16:02

1

3

2

J66

2

1 R4610.0K1/10W

2

1 R175710.0K1/10W

VCCO_0_INH_B

VCCINT_INH_B

2

1

R1758

10.0K1/10W

GND GND

GND

AGND2

C2_TMUX2C2_TMUX1C2_TMUX0

C21_C22_TEMPC23_TEMP

NCNC NC

NC

C12_VCCAUX_FLT

VCCO_HP_FLT

1

2

1

R269

1.00K1/16W

1

2

1

R1760

2

1

R1759

12345678

161514131211109

SW10

SDA08H1SBD

C12_C13_TEMPC11B_TEMP

1

2

C50.1UF25V

10

6

7

12

1413

15

1524

8

11

9

3

16

U4

CD74HC4051

C1_TMUX0C1_TMUX1C1_TMUX2

C1_TEMP

C11A_TEMP

PWRCTL1_VCC3V3A

GND

VCCAUX_IO_FLTVCCBRAM_FLTVCCAUX_FLT

2

1 R1761

C13_VCCBRAM_FLTC21_VCCAUX_IO_FLTC22_VCCO_HP_FLT

PWRCTL1_VCC3V3A

PWRCTL2_VCC3V3A

2

1

R270

2

1R4110.0K1/10W 2

1 R42

2

1

R43

10.0K1/10W

1 2

3

5 6

7 8

9 10

4

J26UTIL_3V3 UTIL_3V3

2

1R17510.0K1/10W

UTIL_3V3

NC

NC

NC

PMBUS_ALERT

PMBUS_DATA

NC

NC

PMBUS_CTRL PMBUS_CLK

2

1

R322

1.00K1/16W

1

2

C1270.1UF25V

10

6

7

12

1413

15

1524

8

11

9

3

16

U28

CD74HC4051

2

1

R321

C2_TEMP

PWRCTL2_VCC3V3A

AGND2

AGND2

3

2 4

1

5

U40 SC70_5

NC7SV125

POR_B1

UTIL_3V3

Page 10: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

DGND1

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

AGND1

DGND1AGND1

AGND1

AGND1

AGND1

TRST_B

ADC_REF

ADDR-0ADDR-1

AG

ND

3

AUX-IN_AD14AUX-IN_AD13

BPCAP

CS-1ACS-1B

CS-2ACS-2B

CS-3ACS-3B

CS-4ACS-4B

DG

ND

1D

GN

D2

DG

ND

3

DPWM-1ADPWM-1B

DPWM-2ADPWM-2B

DPWM-3ADPWM-3B

DPWM-4ADPWM-4B

EAN1

EAN2

EAN3

EAN4

EAP1

EAP2

EAP3

EAP4

SEQ-1

FAULT-1AFAULT-1B

FAULT-2AFAULT-2B

FAULT-3AFAULT-3B

FAULT-4AFAULT-4B

SRE-1ASRE-1B

SRE-2ASRE-2B

SRE-3ASRE-3B

SRE-4ASRE-4B

SYNC-INSYNC-OUT

TCK

TDITDO

TEMP

TMS

TMUX0TMUX1TMUX2

TRCK

V33

D

V33

DIO

1V

33D

IO2

V33

FB

AG

ND

2A

GN

D1

SEQ-2SEQ-3

PGOOD

V33

A

VIN_IIN

RESET_B

PMBUS_CTRLPMBUS_CLKPMBUS_DATAPMBUS_ALERT

VTRACK

O603_SHORT

O603_SHORT

AGND1

DGND1

GND

GND

GND

P

2 PLACES

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

2 PLACES

PMBUS ADDRESS

HEX DECIMAL

520x34

2 PLACES

PWM SYSTEM CONTROLLER #1

2 PLACES

3 PLACES

ALL PGOOD OUTPUTS WILL BE OPEN-DRAIN AND WIRE-ORED

NOTES:

PWM SYSTEM CONTROLLER #1

7310

VC7222 V7 HCG1155 MGT CHAR

01

C12-14-2012_16:02

1

3

2

J48

C13_VCCBRAM_EAP

C12_VCCAUX_EAP

C11_VCCINT_EAPC11B_VCCINT_FLT

CTRL3_SEQ_OUTCTRL2_SEQ_OUT

1

TP10

MGT_POR_B

UTIL_3V3

2

1

R178

2

1 R177

2

1R4910.0K1/10W

2

1R17557871/10W2

1

25V1500PF

C1159

UTIL_3V3

21

R691.00K1/16W

POR_B12

1 R2351.1K1/10W

PWRCTL1_VCC3V3A

2

1R41910.0K1/10W

1

32

Q31

NDS331N460MW

NC

VCCBRAM_EA_N

1

2

C754.7UF10VX5R

1

2

C744.7UF10VX5R

1

2

C310.01UF25VX5R

1

2

C90.1UF

25V

1

2

C80.1UF

25V

1

2

C10

1

2

C70.1UF25V

C11A_VCCINT_FLT

C11A_VCCINT_SRE

C11A_VCCINT_PWM

21

R681.00K1/16W

C11A_VCCINT_CS

1

2

C728

1

2

C370.068UF10V

VCCINT_SPY_N

C13_VCCBRAM_FLT

21 Z1

21 Z2

C13_VCCBRAM_SRE

2

1R922.00K1/16W

2

1R9675K1/10W

48

1

7776

80

7271

59

7579

478

374

273

9 3455

2122

2324

2526

2728

63

65

67

69

62

64

66

68

32

1516

1718

2941

4243

35

1936

20

1211

5137

3852

3350

3130

44

4645

7

47

394054

14

578 56

70

6160

5310

49

58

5

136

U9

UCD9248PFC

VCC12_P

C13_VCCBRAM_CS

2

1R9775K1/10W

2

1R47

10.0K1/10W

12

L1FERRITE-220

1

2C360.068UF10V

2

1R48

GND

1

1

PGOOD

NC

NCNC

NC

NC

NC

CTRL1_SEQ_OUT

NCC13_VCCBRAM_PWM

NC

PMBUS_ALERTPMBUS_DATAPMBUS_CLKPMBUS_CTRL

C1_TMUX2C1_TMUX1C1_TMUX0

C1_TEMP

NC

NCNC

NC

1

2C380.068UF10V

21

R711.00K1/16W

C12_VCCAUX_CSVCCAUX_EA_N

C12_VCCAUX_FLT

C12_VCCAUX_SRE

C12_VCCAUX_PWM

NC

21

R352

C11B_VCCINT_CS

C11B_VCCINT_PWM

C11B_VCCINT_SRE

NC

UTIL_3V3

UTIL_3V3

UTIL_3V3

2

1R17561.00K1/16W

UTIL_3V3

2

1R17610.0K1/10W

Page 11: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

O603_SHORT

O603_SHORT GND

TRST_B

ADC_REF

ADDR-0ADDR-1

AG

ND

3

AUX-IN_AD14AUX-IN_AD13

BPCAP

CS-1ACS-1B

CS-2ACS-2B

CS-3ACS-3B

CS-4ACS-4B

DG

ND

1D

GN

D2

DG

ND

3

DPWM-1ADPWM-1B

DPWM-2ADPWM-2B

DPWM-3ADPWM-3B

DPWM-4ADPWM-4B

EAN1

EAN2

EAN3

EAN4

EAP1

EAP2

EAP3

EAP4

SEQ-1

FAULT-1AFAULT-1B

FAULT-2AFAULT-2B

FAULT-3AFAULT-3B

FAULT-4AFAULT-4B

SRE-1ASRE-1B

SRE-2ASRE-2B

SRE-3ASRE-3B

SRE-4ASRE-4B

SYNC-INSYNC-OUT

TCK

TDITDO

TEMP

TMS

TMUX0TMUX1TMUX2

TRCK

V33

D

V33

DIO

1V

33D

IO2

V33

FB

AG

ND

2A

GN

D1

SEQ-2SEQ-3

PGOOD

V33

A

VIN_IIN

RESET_B

PMBUS_CTRLPMBUS_CLKPMBUS_DATAPMBUS_ALERT

VTRACK

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

PMBUS ADDRESS

HEX

2 PLACES

2 PLACES

530x35

DECIMAL

PWM SYSTEM CONTROLLER #2

ALL PGOOD OUTPUTS WILL BE OPEN-DRAIN AND WIRE-ORED

3 PLACES

NOTES:

PWM SYSTEM CONTROLLER #2

7311

VC7222 V7 HCG1155 MGT CHAR

01

C12-14-2012_16:02

1

3

2

J49

C23_VCCO_0_EAP

C22_VCCO_HP_EAP

DGND2

CTRL2_SEQ_OUT

C2_TMUX2C2_TEMP

VCCO_0_EA_NC23_VCCO_0_CS

C23_VCCO_0_FLTNCC23_VCCO_0_SRE

C23_VCCO_0_PWM

1

48

1

7776

80

7271

59

7579

478

374

273

9 3455

2122

2324

2526

2728

63

65

67

69

62

64

66

68

32

1516

1718

2941

4243

35

1936

20

1211

5137

3852

3350

3130

44

4645

7

47

394054

14

578 56

70

6160

5310

49

58

5

136

U10

UCD9248PFC

PWRCTL2_VCC3V3A

NC

POR_B1

VCC12_P

1

2

C774.7UF10VX5R

1

2

C764.7UF10VX5R

1

2

C130.1UF

25V

2

1R51

C22_VCCO_HP_CS

1

2C390.068UF10V

VCCO_HP_EA_N

C22_VCCO_HP_FLT

C21_VCCAUX_IO_CSVCCAUX_IO_EA_NC21_VCCAUX_IO_EAP

C21_VCCAUX_IO_FLT

C22_VCCO_HP_SRE

C21_VCCAUX_IO_SRE

NC

NC

AGND2PGOOD

1

2C420.068UF10V

21

R741.00K1/16W

21

R751.00K1/16W

AGND2

AGND2

AGND2

NC

2

1R9875K1/10W2

1R2786.6K1/10W

21 Z3

21 Z4

AGND2

AGND2

C22_VCCO_HP_PWM

C21_VCCAUX_IO_PWM

NC

2

1R50

10.0K1/10W

NC

NC

NC

12

L2FERRITE-220

DGND2

GND

2

1R5210.0K1/10W

2

1R932.00K1/16W

1

NCNC

PMBUS_CTRLPMBUS_CLKPMBUS_DATAPMBUS_ALERT

NC

NCNC

NC

NC

1

2

C140.1UF

25V

1

2

C12

1

2

C110.1UF25V

1

2

C320.01UF25VX5R

UTIL_3V3

UTIL_3V3

UTIL_3V3

2

1 R2451.1K1/10W

UTIL_3V3

2

1

R181

2

1 R180

2

1R17910.0K1/10W 1

2C1680.068UF10V

21

R3231.00K1/16W

NC

C2_TMUX1C2_TMUX0

CTRL1_SEQ_OUTCTRL4_SEQ_OUT

DGND2

Page 12: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

GND

O603_SHORT

TRST_B

ADC_REF

ADDR-0ADDR-1

AG

ND

3

AUX-IN_AD14AUX-IN_AD13

BPCAP

CS-1ACS-1B

CS-2ACS-2B

CS-3ACS-3B

CS-4ACS-4B

DG

ND

1D

GN

D2

DG

ND

3

DPWM-1ADPWM-1B

DPWM-2ADPWM-2B

DPWM-3ADPWM-3B

DPWM-4ADPWM-4B

EAN1

EAN2

EAN3

EAN4

EAP1

EAP2

EAP3

EAP4

SEQ-1

FAULT-1AFAULT-1B

FAULT-2AFAULT-2B

FAULT-3AFAULT-3B

FAULT-4AFAULT-4B

SRE-1ASRE-1B

SRE-2ASRE-2B

SRE-3ASRE-3B

SRE-4ASRE-4B

SYNC-INSYNC-OUT

TCK

TDITDO

TEMP

TMS

TMUX0TMUX1TMUX2

TRCK

V33

D

V33

DIO

1V

33D

IO2

V33

FB

AG

ND

2A

GN

D1

SEQ-2SEQ-3

PGOOD

V33

A

VIN_IIN

RESET_B

PMBUS_CTRLPMBUS_CLKPMBUS_DATAPMBUS_ALERT

VTRACK

O603_SHORT

3 PLACES

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

PMBUS ADDRESS

HEX DECIMAL

2 PLACES

540x36

PWM SYSTEM CONTROLLER #3

2 PLACES

NOTES:

ALL PGOOD OUTPUTS WILL BE OPEN-DRAIN AND WIRE-ORED

CO-LOCATE CONTROLLER WITH MGT POWER MODULES

PWM SYSTEM CONTROLLER #3

12-14-2012_16:02 C

01

VC7222 V7 HCG1155 MGT CHAR

12 73

1

3

2

J50

C33_MGTVCCAUX_EAP

C32_MGTAVTT_EAP

C31_MGTAVCC_EAP

DGND3

AGND3

NC

MGTVCCAUX_EA_N

MGTAVTT_SPY_N

MGTAVCC_SPY_N

2

1

POR_B1

PWRCTL3_VCC3V3A

AGND3

1

C32_MGTAVTT_CS

C31_MGTAVCC_CS

1

2

C794.7UF10VX5R

1

2

C784.7UF10VX5R

1

2

C150.1UF

25V

1

2C440.068UF10V

21 Z5

AGND3

AGND3

NC

NC

21

R761.00K1/16W

C33_MGTVCCAUX_CS

VCC12_P

48

1

7776

80

7271

59

7579

478

374

273

9 3455

2122

2324

2526

2728

63

65

67

69

62

64

66

68

32

1516

1718

2941

4243

35

1936

20

1211

5137

3852

3350

3130

44

4645

7

47

394054

14

578 56

70

6160

5310

49

58

5

136

U11

UCD9248PFC

NC

PGOOD

21

R771.00K1/16W

21

R781.00K1/16W

1

2C450.068UF10V

GND

2

1R54

10.0K1/10W

NC

2

1R9975K1/10W2

1R56100K1/10W

21 Z6

AGND3

AGND3

NC

NC

NC

NC

2

1R55

1

2C430.068UF10V

NC

12

L3FERRITE-220

DGND3

2

1R5310.0K1/10W

2

1R942.00K1/16W

AGND3

NC

NC

NC

NC

NC

NC

NC

NCNCNC

PMBUS_CTRLPMBUS_CLKPMBUS_DATAPMBUS_ALERT

NC

NC

NC

NCNC

NC

1

2

C17

1

2

C180.1UF25V

1

2

C160.1UF

25V

1

2

C330.01UF25VX5R

UTIL_3V3

UTIL_3V3

UTIL_3V3

2

1 R2551.1K1/10W

UTIL_3V3

2

1

R196

2

1 R187

2

1R18210.0K1/10W

CTRL3_SEQ_OUTNCNC

DGND3

Page 13: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

GND

O603_SHORT

TRST_B

ADC_REF

ADDR-0ADDR-1

AG

ND

3

AUX-IN_AD14AUX-IN_AD13

BPCAP

CS-1ACS-1B

CS-2ACS-2B

CS-3ACS-3B

CS-4ACS-4B

DG

ND

1D

GN

D2

DG

ND

3

DPWM-1ADPWM-1B

DPWM-2ADPWM-2B

DPWM-3ADPWM-3B

DPWM-4ADPWM-4B

EAN1

EAN2

EAN3

EAN4

EAP1

EAP2

EAP3

EAP4

SEQ-1

FAULT-1AFAULT-1B

FAULT-2AFAULT-2B

FAULT-3AFAULT-3B

FAULT-4AFAULT-4B

SRE-1ASRE-1B

SRE-2ASRE-2B

SRE-3ASRE-3B

SRE-4ASRE-4B

SYNC-INSYNC-OUT

TCK

TDITDO

TEMP

TMS

TMUX0TMUX1TMUX2

TRCK

V33

D

V33

DIO

1V

33D

IO2

V33

FB

AG

ND

2A

GN

D1

SEQ-2SEQ-3

PGOOD

V33

A

VIN_IIN

RESET_B

PMBUS_CTRLPMBUS_CLKPMBUS_DATAPMBUS_ALERT

VTRACK

O603_SHORT

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

NOTES:

ALL PGOOD OUTPUTS WILL BE OPEN-DRAIN AND WIRE-ORED

CO-LOCATE CONTROLLER WITH MGT POWER MODULES

3 PLACES

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

PMBUS ADDRESS

HEX DECIMAL

2 PLACES

2 PLACES

550x37

PWM SYSTEM CONTROLLER #4

PWM SYSTEM CONTROLLER #4

7313

VC7222 V7 HCG1155 MGT CHAR

01

C12-14-2012_16:02

1

3

2

J68

C43_MGTZAVCC_EAP

C42_MGTZVCCL_EAP

C41_MGTZVCCH_EAP

CTRL4_SEQ_OUTNC

MGTZAVCC_SPY_N

MGTZVCCL_SPY_N

MGTZVCCH_SPY_NC41_MGTZVCCH_CS

C42_MGTZVCCL_CS

DGND4

AGND4

DGND4

AGND4

1

1

2

C1504.7UF10VX5R

1

2

C1494.7UF10VX5R

1

2

C290.1UF

25V

1

2C1310.068UF10V

21 Z8

21

R2731.00K1/16W

VCC12_P

48

1

7776

80

7271

59

7579

478

374

273

9 3455

2122

2324

2526

2728

63

65

67

69

62

64

66

68

32

1516

1718

2941

4243

35

1936

20

1211

5137

3852

3350

3130

44

4645

7

47

394054

14

578 56

70

6160

5310

49

58

5

136

U18

UCD9248PFC

21

R2721.00K1/16W

21

R2711.00K1/16W

1

2C1300.068UF10V

GND

2

1R205

10.0K1/10W

2

1R30575K1/10W

21 Z7

2

1R204

1

2C1290.068UF10V

12

L5FERRITE-220

2

1R20110.0K1/10W

2

1R2822.00K1/16W

1

2

C28

1

2

C270.1UF25V

1

2

C260.1UF

25V

1

2

C1280.01UF25VX5R

UTIL_3V3

UTIL_3V3

UTIL_3V3

2

1 R28851.1K1/10W

UTIL_3V3

2

1

R200

2

1 R199

2

1R19810.0K1/10W

POR_B1

NC

NC

C43_MGTZAVCC_CS

NC

PGOOD

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NCNCNC

PMBUS_CTRLPMBUS_CLKPMBUS_DATAPMBUS_ALERT

NC

NC

NC

NCNC

NC

2

1

PWRCTL4_VCC3V3A

AGND4

AGND4

DGND4

AGND4

AGND4

AGND4

2

1R8115K1/10W

NCNC

Page 14: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXXPLACE LOW-PASS FILTER COMPONENTS ADJACENT TO CONTROLLER #1

PLACE LOW-PASS FILTER COMPONENTS ADJACENT TO CONTROLLER #2

ROUTE AS 100 OHM DIFFERENTIAL PAIR FROM LOAD SENSE POINT TO CONTROLLER

REMOTE VOLTAGE SENSE LOW-PASS FILTERS

CONTROLLER #1 RAILS CONTROLLER #2 RAILS

NOTES:

REMOTE VOLTAGE SENSE LOW-PASS FILTERS

12-14-2012_16:02 C

01

VC7222 V7 HCG1155 MGT CHAR

14 73

C23_VCCO_0_EAP

C22_VCCO_HP_EAP

C21_VCCAUX_IO_EAP

C13_VCCBRAM_EAP

C12_VCCAUX_EAP

C11_VCCINT_EAP VCCINT_SPY_P

VCCINT_SPY_N

VCCO_0

VCCO_0_EA_N

VCCAUX_IO_EA_N

VCCAUX_IO_EA_P

VCCBRAM_EA_N

VCCBRAM_EA_P

VCCAUX_EA_N

VCCAUX_EA_P

3

2

1

Z16

Z13

Z17

Z12

Z15

Z10

GND

GND

GND

GND

VCCAUX

2 1

R801.00K1/16W

VCCAUX_IO

VCCBRAM

2

1

J17

2

1

J16

2

1

J15

2

1

J14

2

1

25V1500PFC67

2 1

R831.00K1/16W

2

1

25V1500PFC66

2

1R157871/10W

2 1

R821.00K1/16W

2

1

25V1500PFC65

2 1

R811.00K1/16W

2

1

25V1500PFC64

2

1R147871/10W

VCCO_HP_EA_P

VCCO_HP_EA_N

2

1

J192 1

R841.00K1/16W

2

1

25V1500PFC68

2

1R167871/10W

1

1

1

1

2

3

3

3

3

3

VCCO_HP

Z9

Z14

Z32

Z31

GND

2 1

R3241.00K1/16W

2

1

J74

2

1

25V1500PFC197

2

1R2377871/10W

2

3

VCCO_0_EA_P

Page 15: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

REMOTE VOLTAGE SENSE LOW-PASS FILTERS

PLACE LOW-PASS FILTER COMPONENTS ADJACENT TO CONTROLLER #3

ROUTE AS 100 OHM DIFFERENTIAL PAIR FROM LOAD SENSE POINT TO CONTROLLER

---------------------

CONTROLLER #3 RAILS

NOTES:

REMOTE VOLTAGE SENSE LOW-PASS FILTERS

12-14-2012_16:02 C

01

VC7222 V7 HCG1155 MGT CHAR

15 73

C33_MGTVCCAUX_EAP

C32_MGTAVTT_EAP

C31_MGTAVCC_EAP

MGTAVTT_SPY_P

MGTAVTT_SPY_N

MGTAVCC_SPY_N

MGTAVCC_SPY_P

Z232 MGTVCCAUX

GND

2

1

3

2 1

R891.00K1/16W

2

1

J20

2

1

25V1500PFC71

2

1R197871/10W

3

MGTVCCAUX_EA_P

MGTVCCAUX_EA_N Z24

2

2

2 1

R881.00K1/16W

2

1

J21

2

1

25V1500PFC72 3

2

1

J222 1

R871.00K1/16W

2

1

25V1500PFC73 3

Page 16: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

REMOTE VOLTAGE SENSE LOW-PASS FILTERS

ROUTE AS 100 OHM DIFFERENTIAL PAIR FROM LOAD SENSE POINT TO CONTROLLER

---------------------

NOTES:

CONTROLLER #4 RAILS

PLACE LOW-PASS FILTER COMPONENTS ADJACENT TO CONTROLLER #4

REMOTE VOLTAGE SENSE LOW-PASS FILTERS

12-14-2012_16:02 C

01

VC7222 V7 HCG1155 MGT CHAR

16 73

C43_MGTZAVCC_EAP

C42_MGTZVCCL_EAP

C41_MGTZVCCH_EAP

MGTZAVCC_SPY_N

MGTZAVCC_SPY_P

MGTZVCCL_SPY_N

MGTZVCCL_SPY_P

MGTZVCCH_SPY_P

MGTZVCCH_SPY_N

2

2

1

3

2 1

R2761.00K1/16W

2

1

J11

2

1

25V1500PFC143 3

2

2

2 1

R2751.00K1/16W

2

1

J10

2

1

25V1500PFC142 3

2

1

J92 1

R2741.00K1/16W

2

1

25V1500PFC141 3

2

1R457871/10W

Page 17: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

22

AGND1

AGND1

AGND1

VCCINT

FAULT

PWM

GND_1

GND_0

IOUT

AGND

VOVI

SRE

VBIAS

INH_B

TEMP

AGND1

GND

RG1 RG2

V_PVIN_N

VIN_P VOUT

REFV_N

AGND1

1RG1 8RG2

7V_PVIN_N2

3VIN_P VOUT6

5REFV_N4

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

R2R1

S1 S2

VCCINT

FAULT

PWM

GND_1

GND_0

IOUT

AGND

VOVI

SRE

VBIAS

INH_B

TEMP

R2R1

S1 S2

AGND1

AGND1

AGND1

NOTES:

CONTROLLER 1

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

VCCINT TWO PHASE 20A/20A REG

2 PLACES

VCCINT, 1.0 VDC, 20A

VCCINT, 1.0 VDC, 20A

CHANNEL 1ACONTROLLER 1

CHANNEL 1B

PLACE COMPONENTS AS CLOSE AS POSSIBLE TO VI PIN ON REGULATOR

VCCINT 2-PHASE, 20A REGULATORS

7317

VC7222 V7 HCG1155 MGT CHAR

01

C12-14-2012_16:02

C11_VCCINT_EAP

C11_VCCINT_EAP

VCCINT_SPY_N

VCC12_P_C11B

C11A_VCCINT_FLT

VCCINT_INH_B

VCCINT1_EXT

C11B_VCCINT_PWM

C11B_VCCINT_CS

1J61

2

1

1/10W10

R367

2

1R307

C11A_TEMP

1

J188

21

S1 S2

R3030.0053W 1%

C11B_VCCINT_FLTC11B_VCCINT_SRE

911

32 6 7

41

1012 8

5U5

PTD08A020W

GNDGND

C11A_VCCINT_PWM

1 2

R905.23K1/16W

21

S1 S2

R10.0053W 1%

1

2

C6080.1UF25V

U53

INA333

2

1

D1

BAT54T1G

1

2

C4747UF10V

1

2C55330UF10VTANT

1

2

C190.1UF25V

1

J51

1 8

72

3 6

54

U14

INA333

PWRCTL1_VCC3V3A

1

2

C46647UF10V

GNDGND

911

32 6 7

41

1012 8

5U51

PTD08A020W

1

2

C73247UF10V

1

2C744330UF10VTANT

PWRCTL1_VCC3V3A

GND

1

2

C46747UF10V

NC

C11A_VCCINT_CS

1 2

R3165.23K1/16W

C11A_VCCINT_SRE

GND

NC

C11B_TEMP

VCCINT2_EXT

VCCINT_INH_B

1L13

FERRITE-78

GND

1

2

C133180UF

16VELEC 2

1

25V10UFC102

2

1

25V1UFC119

VCC12_P

1

2

C154330UF25VELEC

1

2

C11422UF25V

1

VCC12_P_C11A

1

L14FERRITE-78

1

2

C155330UF25VELEC

1

2

C11522UF25V

GND

1

2

C134180UF

16VELEC 2

1

25V10UFC103

2

1

25V1UFC120

VCC12_P

1

1

Page 18: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

2

AGND1

AGND1

AGND1

AGND1

AGND1

RG1 RG2

V_PVIN_N

VIN_P VOUT

REFV_N

R2R1

S1 S2

AGND1

1RG1 8RG2

7V_PVIN_N2

3VIN_P VOUT6

5REFV_N4

R2R1

S1 S2

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

PGND5

PGND4 VO_B2

VO_B1

FF_B

ISENSE_B

AGND2

PGND2

VIN2

VIN1

AGND1

TSENSE

ISENSE_A

PWM_A

PWM_B

SRE_A

SRE_B

FF_A

VO_A1

PGND3

VO_A2

PGND1

PAD_GND

AGND1

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

VCCBRAM/VCCAUX DUAL 10A REG

CONTROLLER 1CHANNELS 2A-3A

VCCAUX, 1.8 VDC, 10A

VCCBRAM, 1.0 VDC, 10A

PLACE COMPONENTS AS CLOSE AS POSSIBLE TO VI PIN ON REGULATOR

NOTES:

VCCAUX / VCCBRAM 10A REGULATORS

12-14-2012_16:02 C

01

VC7222 V7 HCG1155 MGT CHAR

18 73

VCC12_P_C12_C13

1

1

VCCAUX_FLTVCCBRAM_FLT

C12_VCCAUX_PWM

C12_VCCAUX_SRE

C13_VCCBRAM_PWM

C13_VCCBRAM_SRE

1

2

C73347UF10VX5R

2019

11

10

7

6 13 8

2

1

12 316 14

18 4 17 5 15

21

9

22

23U6

PTD08D210W

VCCBRAM_EXT VCCBRAM

21

S1 S2

R340.0053W 1%

1

2

C4947UF10V

21

R30

2.55K1/16W

1

2

C56330UF10VTANT

1

2

C210.1UF25V

GND

PWRCTL1_VCC3V3A

U54

INA333

1

J63

1

J54

21

S1 S2

R320.0053W 1%VCCAUX_EXT VCCAUX

1

2

C4647UF10V

21

R28

2.55K1/16W

1

2C54330UF10VTANT

1

2

C200.1UF25V

1

J52

GND

1 8

72

3 6

54

U15

INA333

PWRCTL1_VCC3V3A

1

J60

C12_VCCAUX_CS

C13_VCCBRAM_CS

1

2

C469

GND

GND

NC

NC

C12_C13_TEMP

1

L15FERRITE-78

1

2

C156330UF25VELEC

1

2

C11622UF25V

GND

1

2

C135180UF

16VELEC 2

1

25V10UFC104

2

1

25V1UFC121

VCC12_P

Page 19: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

2

PGND5

PGND4 VO_B2

VO_B1

FF_B

ISENSE_B

AGND2

PGND2

VIN2

VIN1

AGND1

TSENSE

ISENSE_A

PWM_A

PWM_B

SRE_A

SRE_B

FF_A

VO_A1

PGND3

VO_A2

PGND1

PAD_GND

1RG1 8RG2

7V_PVIN_N2

3VIN_P VOUT6

5REFV_N4

R2R1

S1 S2

VCCO_HP

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

R2R1

S1 S2

VCCAUX_IO

RG1 RG2

V_PVIN_N

VIN_P VOUT

REFV_N

NOTES:

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

VCCAUX_IO/VCCO_HP DUAL 10A REG

CONTROLLER 2CHANNELS 1A-2A

VCCO_HP, 1.2-1.8 VDC, 10A

PLACE COMPONENTS AS CLOSE AS POSSIBLE TO VI PIN ON REGULATOR

VCCAUX_IO / VCCO_HP 10A REGULATORS

VCCAUX_IO, 1.8 VDC, 10A

12-14-2012_16:02 C

01

VC7222 V7 HCG1155 MGT CHAR

19 73

VCCO_HP_EXT

VCC12_P_C21_C22

C21_VCCAUX_IO_PWM

C21_VCCAUX_IO_SRE

C22_VCCO_HP_PWM

C22_VCCO_HP_SRE

VCCAUX_IO_FLTVCCO_HP_FLT

AGND2

AGND2

1

2

C59330UF10VTANT

1 8

72

3 6

54

U16

INA333

VCCAUX_IO_EXT

21

S1 S2

R330.0053W 1%

1

2

C230.1UF25V

21

S1 S2

R350.0053W 1%

1

J62

J65

21

R31

2.55K1/16W

21

R29

2.55K1/16W

PWRCTL2_VCC3V3A

U55

INA333

PWRCTL2_VCC3V3A

1

2

C5147UF10V

1

2

C4847UF10V

1

2C57330UF10VTANT

1

2

C220.1UF25V

1

J53

1

J55

GND

GND

1

2

C47047UF10VX5R

2019

11

10

7

6 13 8

2

1

12 316 14

18 4 17 5 15

21

9

22

23U50

PTD08D210W

1

2

C468

GND

GND

NC

NC

C21_C22_TEMP

C22_VCCO_HP_CS

C21_VCCAUX_IO_CS

AGND2

AGND2

AGND2

AGND2

AGND2

1

1

1

L17FERRITE-78

1

2

C157330UF25VELEC

1

2

C11722UF25V

GND

1

2

C136180UF

16VELEC 2

1

25V10UFC105

2

1

25V1UFC122

VCC12_P

Page 20: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

2

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

R2R1

S1 S2

RG1 RG2

V_PVIN_N

VIN_P VOUT

REFV_N

INH

FAULT

SRE

PWM

GND_1

GND_0

TEMP

IOUT

AGND

VOVI

VBIAS

NOTES:

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

VCCAUX_IO/VCCO_HP DUAL 10A REG

CONTROLLER 2

PLACE COMPONENTS AS CLOSE AS POSSIBLE TO VI PIN ON REGULATOR

VCCO_0 REGULATOR

CHANNELS 3A

VCCO_0, 1.8 VDC, 10A

7320

VC7222 V7 HCG1155 MGT CHAR

01

C12-14-2012_16:02

C23_VCCO_0_CS

VCCO_0_INH_B

C23_VCCO_0_FLT

C23_VCCO_0_SRE

VCCO_0VCCO_0_EXT

1

2

C17747UF10V

8910

11

32 5 6 7

41

12

U46

PTD08A006W

GND AGND2

AGND2

1 8

72

3 6

54

U44

INA333

21

S1 S2

R620.0053W 1%

1

J104

21

R308

2.55K1/16W

PWRCTL2_VCC3V3A

1

2

C17147UF10V

1

2C200330UF10VTANT

1

2

C1640.1UF25V

1

J103

GND

AGND2

AGND2

1

1

1

L21FERRITE-78

1

2

C212330UF25VELEC

1

2

C16622UF25V

GND

1

2

C182180UF

16VELEC 2

1

25V10UFC165

2

1

25V1UFC167

VCC12_P

NC

C23_TEMP

C23_VCCO_0_PWM

VCC12_P_C23

GND

Page 21: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

22

2

MRG_UP

VI

TRACK

INH_B

VOMRG_DN

SENSE

VO_ADJ

GND

GND

MRG_UP

VI

TRACK

INH_B

VOMRG_DN

SENSE

VO_ADJ

GND

GND

MRG_UP

VI

TRACK

INH_B

VOMRG_DN

SENSE

VO_ADJ

GND

GND

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

PLACE COMPONENTS AS CLOSE AS POSSIBLE TO VI PIN ON REGULATOR

2 PLACES

2 PLACES

2 PLACES

NOTES:

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

UTIL_3V3, 18A

UTILITY REGULATORS

INH_B AN OPEN-DRAIN DRIVER

UTILITY REGULATORS

UTIL_5V0, 10A

UTIL_2V5, 18A

7321

VC7222 V7 HCG1155 MGT CHAR

01

C12-14-2012_16:02

1

J58

GND

UTIL_2V5VCC12_P_2V5

VCC12_P_3V3

VCC12_P_5V0

1

2

C11110UF25V

1

2

C10910UF25V

1

1

1

POR_B2

POR_B2

POR_B2 1

3

2

J24

1

2

C5347UF10V

1

2C61330UF10VTANT

10

2

1

8

3

7

6

9 5

4U13

PTH12020W

10

2

1

8

3

7

6

9 5

4U2

PTH12060WAD

GND

1

2

C47347UF10V

1

J59

21

1/16W2.00KR95

21

R2982801/10W

1

2

C47647UF10V

1

2

C3447UF10V

UTIL_3V3

UTIL_5V0

GND

1

2C62330UF10VTANT

GND

GND

GND

GND

NC

NC

NC

NC

1

3

2

J4

GND

GND

21

R3154.32K1/10W

1

2

C73547UF10V

1

2

C73447UF10V

GND

1

2C745330UF10VTANT

GND

1

J187

GND1

3

2

J184

10

2

1

8

3

7

6

9 5

4U52

PTH12020W

NC

NC

1

2

C159

330UF25VELEC

1

2

C158

1

L18FERRITE-78

2GND

1

2

C137180UF

16VELEC 2

1

25V10UFC108

2

1

25V1UFC123

VCC12_P

2

1

1

2

C161

330UF25VELEC

1

2

C160

1

L19FERRITE-78

2GND

1

2

C138180UF

16VELEC 2

1

25V10UFC110

2

1

25V1UFC124

VCC12_P

1

2

C11310UF25V

1

2

C163

330UF25VELEC

1

2

C162

1

L20FERRITE-78

2GND

1

2

C139180UF

16VELEC 2

1

25V10UFC112

2

1

25V1UFC125

VCC12_P

Page 22: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

GNDGND

GND GNDGND

RG1 RG2

V_PVIN_N

VIN_P VOUT

REFV_N

R2R1

S1 S2

RG1 RG2

V_PVIN_N

VIN_P VOUT

REFV_N

RG1 RG2

V_PVIN_N

VIN_P VOUT

REFV_N

R2R1

S1 S2

R2R1

S1 S2

GND

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

MGTAVCC MGTAVTT MGTVCCAUX

TO LOCAL UCD9248

TO LOCAL UCD9248

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

NOTES:

PLACE TEST POINTS AS CLOSE AS POSSIBLE TO SENSE RESISTOR

TO LOCAL UCD9248

GTH POWER STATUS LEDS

GTH CURR SENSE / PWR IN / LEDS

TO GTH POWER MODULE TO GTH POWER MODULE

TO GTH POWER MODULE

GTH POWER - CURRENT SENSE, STATUS LEDS, INPUT CONNECTOR

12-14-2012_16:02 C

01

VC7222 V7 HCG1155 MGT CHAR

22 73

2 1

R3256491/10W

2 1

R1382.05K1/10W

2 1

R2683.16K1/10W

MGTAVTT_MOD

MGTVCCAUX_MOD

MGTAVCC_MOD

21

S1 S2

R1450.0053W 1%

1

AGND3 AGND3

MGTAVTTMGTAVCC

1

2

C8290.1UF25V

C32_MGTAVTT_CS

21

S1 S2

R1440.0053W 1%

1 8

72

3 6

54

U36 MSOP_8

INA333_MSOP-81 8

72

3 6

54

U37 MSOP_8

INA333_MSOP-8

MGTAVCC_CS_N

MGTAVCC_CS_P

MGTAVTT_CS_P

MGTAVTT_CS_N

1

J189

C31_MGTAVCC_CS

1

J190

PWRCTL3_VCC3V3A PWRCTL3_VCC3V3A

1

2

C8300.1UF25V

1

J224

1

J225

1

1

J226

1

J227

1

AGND3AGND3

AGND3

MGTVCCAUX

1

J191

21

S1 S2

R1460.0053W 1%

1 8

72

3 6

54

U38 MSOP_8

INA333_MSOP-8

PWRCTL3_VCC3V3A

1

2

C8310.1UF25V

1

J228

1

J229

1

AGND3

C33_MGTVCCAUX_CS

MGTVCCAUX_CS_P

MGTVCCAUX_CS_N

MGTVCCAUX_MODMGTAVTT_MOD

2

1

DS27

1

32

Q16

NDS331N460MW

1

32

Q17

NDS331N460MW

1

32

Q18

NDS331N460MW

2

1

DS26

2

1 R2242611/10W

2

1 R2232611/10W

2

1 R2222611/10W

2

1R2211.00K1/16W 2

1R2201.00K1/16W 2

1R2191.00K1/16W

2

1

DS28

UTIL_3V3

MGTAVCC_MOD

Page 23: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

GND

MGTAVCC12V

5V

3.3V

GND

NC

MGTAVTT

POWER INTERFACE

MGTVCCAUX

7-SERIES GTH HI-CUR PWR MOD

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

5V INPUT FILTER

4 PLACES

12V INPUT FILTER

4 PLACES

3.3V INPUT FILTER

(EURO-MAG)GTH NPUT POWER

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469

MGTAVCC: 1.0V @ 12.0A

MGTAVTT: 1.2V @ 8.0A

MGTVCCAUX: 1.8V @ 2.6A

RESPECTIVE PIN ON THE POWER CONNECTOR.PLACE ALL FILTER COMPONENTS AS CLOSE AS POSSIBLE TO THEIR

NOTES:

GTH POWER MODULE INTERFACE - POWER CONNECTOR

GTH POWER MODULE INTERFACE

TEST P/N: TSS0XXX

7323

VC7222 V7 HCG1155 MGT CHAR

01

C12-14-2012_16:02

GTH_3V3

GTH_5V0

GTH_VCC12_P

A2

A3

A4

A5

A6

B1

B2

B3

B4

B5

B6

C1

C2

C3

C4

C5

C6

D5

D6

D1

D2

D3

D4

E1

E2

E3

E4

E5

E6

F1

F2

F3

F4

F5

F6

H1

H2

H3

H4

H5

H6

A1

G4

G5

G6

G1

G2

G3

J102 SAMTEC_MPT-08_GTH

1

GND

NC

NC

MGTVCCAUX_MOD

MGTAVTT_MOD

MGTAVCC_MOD

NC

NC

NC

NC

1

3

2

4

5

6

J72

MGTAVCC_MOD

MGTAVTT_MOD

MGTVCCAUX_MOD

1

2 C496100UF6.3V

1

2

C4951

2

C4941

2

C493

1

2 C175100UF6.3V

1

2

C1741

2

C1731

2

C172

1

2

C1850.1UF25V

1

2

1

25V10UFC2321

2 25V1UFC238 1

2 25V0.1UFC184

1

2

C243180UF

16VELEC

1

2

C605330UF25VELEC

1

2

1

25V1UFC237

VCC12_P

UTIL_3V3

1 2

L64.9UH6.5A

UTIL_5V0

1 2

L164.3UH

8.0A

1

2

C176DNP

1

2

C499DNP

1 2

L22FERRITE-78

1

GND

GND

GND

1

2

C1000.1UF25V2

1

25V1UFC236

2

1

25V10UFC191

2

1

25V10UFC190

GTH_VCC12_P

GTH_5V0

GTH_3V3

Page 24: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

MGTAVCC_CS-

MGTAVCC_CS+

MGTAVCC_SNS-

MGTAVTT_SNS+

MGTAVCC_SNS+

MGTAVTT_SNS-

SPI_CLK

SPI_D

SPI_Q

SPI_CS

PMBUS_CLK

PMBUS_CTRL

POR_B

INSTALLED BYPASS

MGTVCCAUX_CS+

MGTVCCAUX_CS-

MGTVCCAUX_SNS+

I2C_SDA

I2C_SCL

N/C

N/C

N/C

N/C

N/C

GND

GND

GND

GND

GND

GND

N/C

N/C

GND

GND

GND

GND

GND

GND

PMBUS_DATA

PMBUS_ALERT

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

N/C

N/C

GND

GND

GND

GND

GND

GND

GND

GND

N/C

N/C

MGTAVTT_CS+

MGTAVTT_CS-

GND

GND

N/C

ALT_PMBUS_ADDR

N/C

N/C N/C

MGTAVCCAUX_SNS-

N/C

SIGNAL INTERFACE

GND

N/C

N/C

N/C

N/C

N/C

7-SERIES GTH HI-CUR PWR MOD

GND

GND

GND

VCCB VCCA

SCLA

SDAASDAB

SCLB

GNDOE

GND

GND

VCCB VCCA

SCLA

SDAASDAB

SCLB

GNDOE

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

NOTES:

4 PLACES

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

SPI LEVELTRANSLATION

4 PLACES

REMOVE RESISTORS TO ISOLATE MGT MODULE ON PMBUS

ROUTE AS 100 OHM DIFFERENTIAL PAIR FROM PINS TO PWR/GND

ROUTE AS 100 OHM DIFFEENTIAL PAIR

PINS OF A MGT DECOUPLING CAP NEAREST THE DUT.

ALTERNATE PMBUS ADDRESS.PULL DOWN ON ALT_PMBUS_ADDR PIN SWITCHES MODULE TO

4 PLACES

MGT POWER MODULE INTERFACE

GTH POWER MODULE INTERFACE - SIGNAL CONNECTOR

I2C INTERFACE CONNECTORGTH POWER MODULE

12-14-2012_16:02 C

01

VC7222 V7 HCG1155 MGT CHAR

24 73

MGTAVTT_SPY_N

MGTAVTT_SPY_P

1

1

MGTAVCC_SPY_N

MGTAVCC_SPY_P

GTH_PM_PMBUS_CTRL

GTH_PM_PMBUS_DATA

GTH_PM_PMBUS_CLK

GTH_MOD_SPI_CS

MGT_MOD_SPI_Q

MGT_MOD_SPI_D

MGT_MOD_SPI_SCK

MGT_POR_B

2

1

1/10W10R388

2

1

1/10W10R389

2

1

1/10W10R3864

Z36

Z35

4

1

MGTAVTT_CS_P

MGTVCCAUX_CS_P

21

R244

GTH_PMBUS_ALERT

3

3

2

2

MGTVCCAUX

VCCO_HP_EXT

8 1

2

36

7

45

U48

PCA95171

2

C6070.1UF25VX5R

UTIL_3V3

12

J23NC

NC

NC

NC

NC

NC

NC

NC

PMBUS_ALERT

PMBUS_CTRL

PMBUS_DATA

PMBUS_CLK

21

R243

21

R242

21

R241

01/10W

MGTAVCC_CS_N

GNDGND

NC

NC

MGTVCCAUX_CS_N

NC

MGTAVTT_CS_N

MGTAVCC_CS_P

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

8 1

2

36

7

45

U49

PCA9517

1

2

C5232.2UF10VX5R

2

1

R291

2

1

R292

2

1R293

2

1 R29010.0K1/10W

2

1

R295

2

1

R296

2

1R297

2

1 R29410.0K1/10W

UTIL_3V3

VCCO_HP_EXT

MGTVCCAUX_SNS_P

MGTVCCAUX_SNS_N

GND

2

1R361DNP

GND

MGTAVTT_MODMGTAVCC_MOD

2

1

1/10W10R387

24

28

43

72

15

20

23

31

21

17

13

18

22

1

9

11

6

10

12

14

16

3

5

2

4

19

7 8

26

32

27

25

30

3635

39 40

44

4645

34

47 48

53

52

54

56

58

60

62

6463

65

67

66

69

71

73 74

75

77

79 80

37

41

38

42

70

33

29

51

49 50

68

61

76

78

55

57

59

J29 SAMTEC_BTE-040_GTH

1

2

3

4

J231

GND

GTH_MOD_I2C_SCL

GTH_MOD_I2C_SDA

Page 25: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

GNDGND

GND GNDGND

RG1 RG2

V_PVIN_N

VIN_P VOUT

REFV_N

R2R1

S1 S2

RG1 RG2

V_PVIN_N

VIN_P VOUT

REFV_N

RG1 RG2

V_PVIN_N

VIN_P VOUT

REFV_N

R2R1

S1 S2

R2R1

S1 S2

GND

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

TO LOCAL UCD9248

TO LOCAL UCD9248

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

NOTES:

PLACE TEST POINTS AS CLOSE AS POSSIBLE TO SENSE RESISTOR

TO LOCAL UCD9248

TO GTZ POWER MODULE

TO GTZ POWER MODULE

GTZ POWER STATUS LEDS

TO GTZ POWER MODULE

MGTZVCCH MGTZVCCL MGTZAVCC

GTZ CURR SENSE / PWR IN / LEDS

MGTZVCCH, MGTZVCCL AND MGTZAVCC CURRENT SENSE, STATUS LEDS, POWER INPUT CONNECTOR

12-14-2012_16:02 C

01

VC7222 V7 HCG1155 MGT CHAR

25 73

2 1

R2161691/10W

2 1

R218331/10W

2 1

R3066981/10W

MGTZVCCH_CS_P

MGTZAVCC_MOD

MGTZVCCL_MOD

MGTZVCCH_MOD

MGTZAVCC_MODMGTZVCCL_MODMGTZVCCH_MOD

PWRCTL4_VCC3V3A

AGND4 AGND4

MGTZAVCC

MGTZVCCL_CS_N

AGND4 AGND4

PWRCTL4_VCC3V3A

MGTZVCCL

MGTZVCCH_CS_N

C41_MGTZVCCH_CS

MGTZVCCH

21

S1 S2

R180.0053W 1%

1

1

2

C410.1UF25V

21

S1 S2

R170.0053W 1%

1 8

72

3 6

54

U27 MSOP_8

INA333_MSOP-81 8

72

3 6

54

U25 MSOP_8

INA333_MSOP-8

1

J97

1

J95

1

2

C400.1UF25V

1

J84

1

J83

1

1

J81

1

J80

1

1

J78

21

S1 S2

R130.0053W 1%

1 8

72

3 6

54

U24 MSOP_8

INA333_MSOP-8

1

2

C350.1UF25V

1

J77

1

J76

1

2

1

DS29

1

32

Q20

NDS331N460MW

1

32

Q14

NDS331N460MW

1

32

Q5

NDS331N460MW

2

1

DS7

2

1 R2872611/10W

2

1 R2862611/10W

2

1 R2852611/10W

2

1R2791.00K1/16W 2

1R2781.00K1/16W 2

1R2771.00K1/16W

2

1

DS1

UTIL_3V3

C43_MGTZAVCC_CS

MGTZAVCC_CS_P

MGTZAVCC_CS_N

C42_MGTZVCCL_CS

MGTZVCCL_CS_P

PWRCTL4_VCC3V3A

AGND4 AGND4

Page 26: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

GND

12V

5V

3.3V

GND

NC

POWER INTERFACE7-SERIES GTZ PWR MOD

MGTZVCCH

MGTZAVCC

MGTZVCCL

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

5V INPUT FILTER

4 PLACES

12V INPUT FILTER

4 PLACES

3.3V INPUT FILTER

(EURO-MAG)GTZ INPUT POWER

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

RESPECTIVE PIN ON THE POWER CONNECTOR.PLACE ALL FILTER COMPONENTS AS CLOSE AS POSSIBLE TO THEIR

NOTES:

GTZ POWER MODULE INTERFACE - POWER CONNECTOR

GTZ POWER MODULE INTERFACE

MGTZAVCC: 1.025V @ 6.0A

MGTZVCCL: 1.025V @ 1.3A

MGTZVCCH: 1.8V @ 0.300A

12-14-2012_16:02 C

01

VC7222 V7 HCG1155 MGT CHAR

26 73

GTZ_3V3

GTZ_5V0

1

MGTZAVCC_MOD

MGTZVCCH_MOD

GND

NC

NC

NC

NC

NC

NC

A2

A3

A4

A5

A6

B1

B2

B3

B4

B5

B6

C1

C2

C3

C4

C5

C6

D5

D6

D1

D2

D3

D4

E1

E2

E3

E4

E5

E6

F1

F2

F3

F4

F5

F6

H1

H2

H3

H4

H5

H6

A1

G4

G5

G6

G1

G2

G3

J5 SAMTEC_MPT-08_GTZ

MGTZVCCL_MOD

1

3

2

4

5

6

J73

MGTZVCCH_MOD

MGTZVCCL_MOD

MGTZAVCC_MOD

1

2 C85100UF6.3V

1

2

C841

2

C831

2

C82

1

2 C95100UF6.3V

1

2

C881

2

C871

2

C86

1

2

C1880.1UF25V

1

2

1

25V10UFC2351

2 25V1UFC241 1

2 25V0.1UFC187

1

2

C140180UF16VELEC

1

2

C244330UF25VELEC

1

2

1

25V1UFC240

VCC12_P

UTIL_3V3

1 2

L124.9UH6.5A

UTIL_5V0

1 2

L44.3UH

8.0A

1

2

C189DNP

1

2

C99DNP

1 2

L23FERRITE-78

1

GND

GND

GND

1

2

C1860.1UF25V2

1

25V1UFC239

2

1

25V10UFC234

2

1

25V10UFC233

GTZ_VCC12_P

GTZ_VCC12_P

GTZ_5V0

GTZ_3V3

Page 27: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

MGTZAVCC_CS-

MGTZAVCC_CS+

MGTZAVCC_SNS-

MGTZVCCL_SNS+

MGTZAVCC_SNS+

MGTZVCCL_SNS-

SPI_CLK

SPI_D

SPI_Q

SPI_CS

PMBUS_CLK

PMBUS_CTRL

POR_B

INSTALLED BYPASS

MGTZVCCH_CS+

MGTZVCCH_CS-

MGTZVCCH_SNS+

I2C_SDA

I2C_SCL

N/C

N/C

N/C

N/C

N/C

GND

GND

GND

GND

GND

GND

N/C

N/C

GND

GND

GND

GND

GND

GND

PMBUS_DATA

PMBUS_ALERT

GND

GND

GND

GND

GND

GND

GND

GND

GND

N/C

N/C

GND

GND

GND

GND

GND

GND

GND

N/C

N/C

GND

GND

N/C

ALT_PMBUS_ADDR

N/C

N/C N/C

N/C

SIGNAL INTERFACE

GND

N/C

N/C

N/C

N/C

N/C

GND

GND

7-SERIES GTZ PWR MOD

MGTZVCCH_SNS-

MGTZVCCL_CS+

MGTZVCCL_CS-

GND

GND

GND

VCCB VCCA

SCLA

SDAASDAB

SCLB

GNDOE

GND

GND

VCCB VCCA

SCLA

SDAASDAB

SCLB

GNDOE

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

2 PLACES

2 PLACES

NOTES:

4 PLACES

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

REMOVE RESISTORS TO ISOLATE MGT MODULE ON PMBUS

ALTERNATE PMBUS ADDRESS.PULL DOWN ON ALT_PMBUS_ADDR PIN SWITCHES MODULE TO

GTZ POWER MODULE INTERFACE - SIGNAL CONNECTOR

GTZ POWER MODULE INTERFACE

4 PLACES

SPI LEVELTRANSLATION

4 PLACES

GTZ POWER MODULEI2C INTERFACE CONNECTOR

2 PLACES

-----

LOCATE INLINE 0 OHM AND DNP RESISTORS AS CLOSE AS POSSIBLETO THEIR RESPECTIVE PIN ON THE POWER MODULE

2 PLACES

4 PLACES 4 PLACES

12-14-2012_16:02 C

01

VC7222 V7 HCG1155 MGT CHAR

27 73

MGTZ_SENSE_GND_300

MGTZAVCC_MOD

MGTZ_SENSE_GNDL_300

MGTZ_SENSE_VCCL_300MGTZ_SENSE_VCCL_P

MGTZVCCL_MOD_SPY_P

MGTZ_SENSE_AVCC_N

MGTZAVCC_MOD_SPY_N

MGTZ_SENSE_AVCC_300

MGTZAVCC_SPY_P

R238

R265

DNP

R250 R263R262

MGTZVCCL_SNS_N

DNPR240 1/10W

0R264R239

R249

2

Z19

Z11

Z20

Z18

R266

MGTZAVCC_CS_P MGTZ_SENSE_AVCC_P

MGTZ_SENSE_VCCL_N

MGTZVCCL_MOD_SPY_N

MGTZAVCC_SPY_N

MGTZVCCL_SPY_N

MGTZVCCL_SPY_P

2

MGTZ_SENSE_VCCH_N

MGTZ_SENSE_VCCH_P

MGTZVCCH_MOD_SPY_N

MGTZVCCH_MOD_SPY_P

Z26

GND

GTZ_MOD_I2C_SCL

GTZ_MOD_I2C_SDA

1

2

3

4

J13

GND

2

1

1/10W10R40

MGTZVCCH_SNS_N

MGTZVCCH_SNS_P

MGTZ_SENSE_AGND_300

Z25

Z22

MGTZVCCH_MOD

MGTZVCCH_CS_N

MGTZVCCH_CS_P

MGTZVCCL_CS_N

GTZ_PM_PMBUS_CLK

3

GTZ__PMBUS_CTRL

GTZ_PMBUS_ALERT

GTZ_PM_PMBUS_DATA21

R258

01/10W

21

R259

21

R260

21

R261

PMBUS_ALERT

PMBUS_CTRL

PMBUS_DATA

PMBUS_CLK

MGT_MOD_SPI_D

MGT_MOD_SPI_SCK

GTZ_MOD_SPI_CS

MGT_MOD_SPI_Q

GND

2

1R22

2

1R21

2

1

1/10W10R26

4

4

1

3

VCCO_HP_EXT

8 1

2

36

7

45

U33

PCA95171

2

C500.1UF25VX5R

UTIL_3V3

12

J8

GNDGND

8 1

2

36

7

45

U31

PCA9517

1

2

C1442.2UF10VX5R

2

1

R236

2

1

R235

2

1R234

2

1 R23010.0K1/10W

2

1

R225

2

1

R217

2

1R207

2

1 R20610.0K1/10W

UTIL_3V3

VCCO_HP_EXT

2

1

1/10W10R20

MGTZVCCL_CS_P

NC

NC

NC

NC

NC

NC

NC

NC

MGTZAVCC_CS_N

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

MGT_POR_B

2

1

1/10W10R36

2

1R2801.00K1/16W

Z21

MGTZVCCH_SPY_P

MGTZVCCH_SPY_N

MGTZ_SENSE_VCCH_300

MGTZAVCC_MOD_SPY_P

1/10W0

R267

MGTZAVCC_SNS_P

MGTZAVCC_SNS_N

Z27

Z28

Z29

Z30

MGTZVCCL_SNS_P

2

24

28

43

72

15

20

23

31

21

17

13

18

22

1

9

11

6

10

12

14

16

3

5

2

4

19

7 8

26

32

27

25

30

3635

39 40

44

4645

34

47 48

53

52

54

56

58

60

62

6463

65

67

66

69

71

73 74

75

77

79 80

37

41

38

42

70

33

29

51

49 50

68

61

76

78

55

57

59

J71 SAMTEC_BTE-040_GTZ

R251

MGTZVCCL_MOD

Page 28: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

GNDGNDGND

VCCO_HP

GNDGND

GND

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

VCCINT

GNDGND

GNDGNDGND

NOTES:

RN

ASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

POWER PROBE CHANNELS

SCHEM, ROHS COMPLIANTPOWER PROBE CHANNELS

DUT POWER PROBE CHANNELS

MGT POWER PROBE CHANNELS

PLACE POWER PROBE CHANNELS AS CLOSE AS POSSIBLE TO THE DUT

7328

VC7222 V7 HCG1155 MGT CHAR

01

C12-14-2012_16:02

1

MGTZAVCCMGTZVCCLMGTZVCCH

1

1

MGTVCCAUX

12

3

J91

CON_SMA_SCREW_ON

12

3

J90

CON_SMA_SCREW_ON

12

3

J92

CON_SMA_SCREW_ON

12

3

J93

CON_SMA_SCREW_ON

VCCAUX_IOVCCBRAM

VCCAUX

MGTAVTT MGTAVCC

12

3

J94

CON_SMA_SCREW_ON

12

3

J88

CON_SMA_SCREW_ON

12

3

J89

CON_SMA_SCREW_ON

12

3

J96

CON_SMA_SCREW_ON

12

3

J33

CON_SMA_SCREW_ON

12

3

J32

CON_SMA_SCREW_ON

12

3

J31

CON_SMA_SCREW_ON

Page 29: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

IP_0_E6IO_L20P_0/VREF_0_C4IO_L20N_0/PUDC_B_D5

IO_L19P_0_A3IO_L19N_0_B3

IP_0_D6IO_L18P_0_A4IO_L18N_0_B4IO_L17P_0_A5IO_L17N_0_C5

IP_0_F7IO_L16P_0_D7IO_L16N_0_C6IO_L15P_0_A6IO_L15N_0_B6IO_L14P_0_F8

IO_L14N_0/VREF_0_E7IO_L13P_0_A7IO_L13N_0_C7

IP_0_F9IO_L12P_0/GCLK10_A8IO_L12N_0/GCLK11_B8IO_L11P_0/GCLK8_C8IO_L11N_0/GCLK9_D8

IP_0/VREF_0_E9IO_L10P_0/GCLK6_C9IO_L10N_0/GCLK7_A9IO_L09P_0/GCLK4_C10IO_L09N_0/GCLK5_D9

IP_0_F10IO_L08P_0_B10IO_L08N_0_A10IO_L07P_0_C11IO_L07N_0_A11IO_L06P_0_D10

IO_L06N_0/VREF_0_E10IO_L05P_0_B12IO_L05N_0_A12IO_L04P_0_A14IO_L04N_0_A13IO_L03P_0_C12IO_L03N_0_D11

IP_0_D12IO_L02P_0/VREF_0_B15

IO_L02N_0_B14IO_L01P_0_D13IO_L01N_0_C13

VCCO_0_B5VCCO_0_E8VCCO_0_B9

VCCO_0_B13

IP_L25N_1_F11IP_L25P_1/VREF_1_F12

IO_L24N_1/A25_C15IO_L24P_1/A24_C16IO_L23N_1/A23_D14IO_L23P_1/A22_E13IO_L22N_1/A21_D15IO_L22P_1/A20_D16

IP_L21N_1_G11IP_L21P_1/VREF_1_G12

IO_L20N_1/A19_F13IO_L20P_1/A18_E14IO_L19N_1/A17_F14IO_L19P_1/A16_G13IO_L18N_1/A15_F15IO_L18P_1/A14_E16IO_L17N_1/A13_G14IO_L17P_1/A12_H13IO_L16N_1/A11_F16IO_L16P_1/A10_G16

IO_L15N_1/RHCLK7_H16IO_L15P_1/IRDY1/RHCLK6_H15

IO_L14N_1/RHCLK5_H14IO_L14P_1/RHCLK4_J14

IP_L13N_1_H11IP_L13P_1_H10

IO_L12N_1/TRDY1/RHCLK3_J16IO_L12P_1/RHCLK2_K16IO_L11N_1/RHCLK1_K14IO_L11P_1/RHCLK0_K15

IO_L10N_1/A9_J13IO_L10P_1/A8_J12

IP_L09N_1_J11IP_L09P_1/VREF_1_J10

IO_L08N_1/A7_L16IO_L08P_1/A6_L14IO_L07N_1/A5_M16IO_L07P_1/A4_M15IO_L06N_1/A3_K13IO_L06P_1/A2_L13

IO_L05N_1/VREF_1_M14IO_L05P_1_M13

IP_L04N_1/VREF_1_K12IP_L04P_1_K11

IO_L03N_1/A1_N16IO_L03P_1/A0_P16

IO_L02N_1/LDC0_P15IO_L02P_1/LDC1_R15IO_L01N_1/LDC2_N14IO_L01P_1/HDC_N13

VCCO_1_J15VCCO_1_H12VCCO_1_E15VCCO_1_N15

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

SYSTEMACE-2 - S3AN FPGA BANKS 0, 1

SYSTEMACE-2 S3AN BANKS 0, 1

7329

VC7222 V7 HCG1155 MGT CHAR

01

C12-14-2012_16:02

J15H12E15N15

U32 FTG256

3S200AN

F11F12C15C16D14E13D15D16G11G12F13E14F14G13F15E16G14H13F16G16H16H15H14J14H11H10J16K16K14K15J13J12J11J10L16L14M16M15K13L13M14M13K12K11N16P16P15R15N14N13

U32 FTG256

3S200AN

B5E8B9B13

U32 FTG256

3S200AN

E6C4D5A3B3D6A4B4A5C5F7D7C6A6B6F8E7A7C7F9A8B8C8D8E9C9A9C10D9F10B10A10C11A11D10E10B12A12A14A13C12D11D12B15B14D13C13

U32 FTG256

3S200AN

TDO_0

TDI_0

TMS_0

SYSACE_TCK_0

NCGND

UTIL_3V3

2

1 R1885101/10W1%

NC

SDCARD_WP

SDCARD_D2

SDCARD_D0

SDCARD_CMD

SDCARD_CLK

SDCARD_D3

SDCARD_D1NC

NCNCNCNC

NCNC

NC

NCNCNCNCNCNC

NCNCNC

NCNC

NC

NC

NCNCNCNC

NC

NC

NCNC

NCNCNC

NCNCNCNCNC

NCNC

NCNCNCNCNCNC

NCNCNCNC

NC

NC

NCNCNC

NCNCNCNCNCNC

NC

NC

NCNCNCNCNCNC

NCNCNCNC

NCNCNCNCNC

NC

NCNC

NC

SDCARD_DET

VCCO_0

2 1

R43801/10W

DUT_MBDETECT_3V3_B

Page 30: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

IP_2/VREF_2_N5IO_L01N_2/M0_P4IO_L01P_2/M1_N4

IO_L02N_2/CSO_B_T2IO_L02P_2/M2_R2

IP_2_L7IO_L03N_2/VS2_T3

IO_L03P_2/RDWR_B_R3IP_2/VREF_2_M7

IO_L04N_2/VS0_P5IO_L04P_2/VS1_N6

IO_L05N_2_R5IO_L05P_2_T4

IO_L06N_2/D6_T6IO_L06P_2/D7_T5

IO_L07N_2_P6IO_L07P_2_N7

IO_L08N_2/D4_N8IO_L08P_2/D5_P7IP_2/VREF_2_M8

IO_L09N_2/GCLK13_T7IO_L09P_2/GCLK12_R7IO_L10N_2/GCLK15_T8IO_L10P_2/GCLK14_P8

IP_2_L8IO_L11N_2/GCLK1_P9IO_L11P_2/GCLK0_N9IO_L12N_2/GCLK3_T9IO_L12P_2/GCLK2_R9

IP_2/VREF_2_L9IO_L13N_2_M10IO_L13P_2_N10

IO_L14N_2/MOSI/CSI_B_P10IO_L14P_2_T10

IO_L15N_2/DOUT_R11IO_L15P_2/AWAKE_T11

IP_2/VREF_2_L10IO_L16N_2_N11IO_L16P_2_P11

IO_L17N_2/D3_P12IO_L17P_2/INIT_B_T12

IO_L18N_2/D1_R13IO_L18P_2/D2_T13IP_2/VREF_2_M11IO_L19N_2_P13IO_L19P_2_N12

IO_L20N_2/CCLK_R14IO_L20P_2/D0/DIN/MISO_T14

VCCO_2_R4VCCO_2_R8VCCO_2_M9

VCCO_2_R12

IO_L01P_3_C2IO_L01N_3_C1IO_L02P_3_D4IO_L02N_3_D3IO_L03P_3_D1IO_L03N_3_E1IP_L04P_3_E4

IP_L04N_3/VREF_3_F4IO_L05P_3_E3IO_L05N_3_E2IP_L06P_3_G6

IP_L06N_3/VREF_3_G5IO_L07P_3_F3IO_L07N_3_G4IO_L08P_3_F1

IO_L08N_3/VREF_3_G1IO_L09P_3_G3IO_L09N_3_H4IO_L10P_3_H6IO_L10N_3_H5

IO_L11P_3/LHCLK0_G2IO_L11N_3/LHCLK1_H1IO_L12P_3/LHCLK2_H3

IO_L12N_3/IRDY2/LHCLK3_J3IP_L13P_3_H7IP_L13N_3_J7

IO_L14P_3/LHCLK4_J2IO_L14N_3/LHCLK5_J1

IO_L15P_3/TRDY2/LHCLK6_K3IO_L15N_3/LHCLK7_K1IO_L16P_3/VREF_3_L1

IO_L16N_3_L2IO_L17P_3_J4IO_L17N_3_J6IO_L18P_3_K4IO_L18N_3_L3IO_L19P_3_M3IO_L19N_3_L4IO_L20P_3_M1IO_L20N_3_N1IP_L21P_3_K5IP_L21N_3_K6IO_L22P_3_N2IO_L22N_3_P1IO_L23P_3_R1IO_L23N_3_P2IO_L24P_3_N3IO_L24N_3_M4IP_L25P_3_L5

IP_L25N_3/VREF_3_L6

VCCO_3_J5VCCO_3_D2VCCO_3_M2VCCO_3_H2

RN

ASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

SCHEM, ROHS COMPLIANTSYSTEMACE-2 S3AN BANKS 2, 3

SYSTEMACE-2 - S3AN FPGA BANKS 2, 3

SYSTEMACE-2 FAILSAFE MODE JUMPERS

12-14-2012_16:02 C

01

30 73

VC7222 V7 HCG1155 MGT CHAR

J5D2M2H2

U32 FTG256

3S200AN

C2C1D4D3D1E1E4F4E3E2G6G5F3G4F1G1G3H4H6H5G2H1H3J3H7J7J2J1K3K1L1L2J4J6K4L3M3L4M1N1K5K6N2P1R1P2N3M4L5L6

U32 FTG256

3S200AN

R4R8M9R12

U32 FTG256

3S200AN

N5P4N4T2R2L7T3R3M7P5N6R5T4T6T5P6N7N8P7M8T7R7T8P8L8P9N9T9R9L9M10N10P10T10R11T11L10N11P11P12T12R13T13M11P13N12R14T14

U32 FTG256

3S200AN

CABLE_TMS

GND

12J69

DNP

VCCO_HP_EXT VCCO_HP_EXT

SA2_RESET_B

UTIL_3V3

SA2_MODE1

SA2_MODE2

SA2_MODE0

2

1 R1054.7K1/10W5%

SA2_SDHOST_CMD

SA2_SDHOST_D1

SA2_SDHOST_CLK

SA2_SDHOST_D2

SA2_SDHOST_D3

SA2_SDHOST_D0

SA2_CFGADDR2

SA2_CLK

SA2_STAT_LED

SA2_CFGMODEPINSA2_CFGADDR0

SA2_CFGADDR1SA2_ERR_LEDSA2_RESET_B

NC

2

1 R1044.7K1/10W5%

12J70

DNP

2

1 R1034.7K1/10W5%

2

1 R1895101/10W

NC

NCNC

NC

NCNC

NC

NC

NCNCNC

NCNCNCNCNC

NCNCNC

NCNCNCNCNCNC

NCNC

NC

NC

NC

NCNCNC

CABLE_TDONC

CABLE_TCKNC

NCNCNC

SYSACE_TDINCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNC

SA2_PROG_B

VCCO_HP_EXT

Page 31: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

UTIL_3V3

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

VIN

GND

EN ADJ

VOUT

VCCAUX_E11VCCAUX_F5

VCCAUX_L12VCCAUX_M6

VCCINT_J9VCCINT_H8VCCINT_G7VCCINT_G9VCCINT_K8

VCCINT_K10

GND_J8GND_R10GND_M12GND_A16GND_A1GND_K9GND_T1

GND_L11GND_F2

GND_G15GND_K2GND_G8GND_C3GND_H9GND_P3

GND_G10GND_E5

GND_B11GND_M5

GND_E12GND_F6

GND_C14GND_R6

GND_L15GND_B7

GND_T16GND_K7

GND_P14

DONE_T15PROG_B_A2

SUSPEND_R16TCK_A15TDI_B1

TDO_B16TMS_B2

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

SYSTEMACE-2 S3AN CONFIG, PWR/GND

DEDICATED SYSTEMACE-2 JTAG

SYSTEMACE-2 - S3AN FPGA CONFIGURATION, PWR/GND

ADD SILKSCREEN TEXT "3AN DONE" BESIDE LED

BANKS 0 & 3 / VCCAUX

BANK 1

BANKS 0 & 3 / VCCAUX VCCINT

BANK 2

NOTES:

7331

VC7222 V7 HCG1155 MGT CHAR

01

C12-14-2012_16:02

T15A2R16A15B1B16B2

U32 FTG256

3S200AN

J8R10M12A16A1K9T1L11F2G15K2G8C3H9P3G10E5B11M5E12F6C14R6L15B7T16K7P14

U32 FTG256

3S200AN

J9H8G7G9K8K10

U32 FTG256

3S200AN

E11F5L12M6

U32 FTG256

3S200AN

1

1

2

C1791UF25VX5R

1

2

C920.1UF25VX5R

1

2

C8230.01UF25VX5R

GND

1

J207

1

2

3 4

5

U21TSOT_5

ADP123

VCCO_HP_EXT

1

2

1

DS22LED-GRN-SMT

1

2

C5960.01UF25VX5R

1

2

C5950.01UF25VX5R

UTIL_3V3

2

1 R1414.7K1/10W5%

2

1 R1396.81K1/10W1%

1

2

C5001UF25VX5R

UTIL_3V3

1

2

C2050.01UF25VX5R

1

2

C2030.01UF25VX5R

1

2

C312470UF6.3VTANT

2

1 R10227.41/10W1%

2

1 R19701/10W5%

2

1 R1473301/10W5%

1

2

C2110.01UF25VX5R

GND

1

2

C17010UF25VX5R

VCC1V2

1

2

C1781UF25VX5R

1

2

C900.1UF25VX5R

1

2

C890.1UF25VX5R

1

2

C2100.01UF25VX5R

1

2

C2090.01UF25VX5R

1

2

C310470UF6.3VTANT

1

2

C1801UF25VX5R

1

2

C930.1UF25VX5R

1

2

C960.1UF25VX5R

1

2

C910.1UF25VX5R

1

2

C2080.01UF25VX5R

1

2

C2070.01UF25VX5R

1

2

C2060.01UF25VX5R

1

2

C2040.01UF25VX5R

1

2

C2020.01UF25VX5R

VCC1V2

1

2

C16910UF25VX5R

GND

UTIL_3V3

UTIL_3V3

GND

GND

GND

GND GND

VCC1V2

1

2

C501470UF6.3VTANT

GND

GND

1

2

C940.01UF25VX5R

SA2_TMSSA2_TDOSA2_TDISA2_TCK

SA2_PROG_B

1

2

C8221UF25VX5R

1

2

C825470UF6.3VTANT

VCCO_0

Page 32: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

IOGND2

GNDTAB1GNDTAB2GNDTAB3

CMDVSS1

CLKVSS2DAT0DAT1DAT2

CD_DAT3

DETECT

VDD

PROTECTDETECT_PROTECT

GNDTAB4IOGND1

GND

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

OE

GND OUT

VCC

RN

ASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

JTAG CABLE CONNECTOR

SD CARDCONNECTOR

ADDRESS DIP SWITCH

PROGRAM RESET

STATUS LED

SYSTEMACE-2 - USER INTERFACE

SCHEM, ROHS COMPLIANTSYSTEMACE-2 USER INTERFACE

SYSTEMACE-2

SYSTEMACE-2 SYSTEMACE-2

SYSTEMACE-2 CONFIG

DEDICATED SYSTEMACE-2

SYSTEMACE-2 CLOCK

SYSTEMACE-2ERROR LED

7332

VC7222 V7 HCG1155 MGT CHAR

01

C12-14-2012_16:02

GNDGND

1234 5

678

SW8

SDA04H1SBD

SA2_CFGADDR1

SA2_CFGMODEPINSA2_CFGADDR2

VCCO_HP_EXT

SA2_TDOSA2_TDI

SA2_TCK

1

2 3

4

U22

50.00000MHZ

UTIL_3V3

UTIL_2V5

2

1

DS23

LED-GRN-SMT

SA2_RESET_B21

SW6

EVQ-11L07K

GNDGND

GND

1

2

C4630.1UF25VX5R

SA2_ERR_LED SA2_STAT_LED

2

1 R10751.1K1/10W1%

2

1 R10851.1K1/10W1% 2

1 R11351.1K1/10W1%

2

1 R11251.1K1/10W1%

2

1 R11151.1K1/10W1%

2

1 R10951.1K1/10W1%

2

1 R1164.7K1/10W5% 2

1 R1174.7K1/10W5%

2

1 R1154.7K1/10W5%

SDCARD_D3SDCARD_CMD

SDCARD_CLK

SDCARD_D0SDCARD_D1SDCARD_D2

SDCARD_DETSDCARD_WP

UTIL_3V3

2

1 R11051.1K1/10W1%

UTIL_3V3

SA2_TMS

21

SW7

EVQ-11L07K

2

1 R1064.7K1/10W5%

1234567891011121314

J67

87832-1420

1

2

C970.1UF25VX5R

NC

2

1 R1935101/10W1%2

1 R1905101/10W1%

UTIL_3V3

GND

21

DS24

LED-RED-SMT

NC

1

32

Q12

NDS331N460MW

2

1 R1941401/10W1%

GND

UTIL_3V3

1

32

Q13

NDS331N460MW

2

1 R1951401/10W1%

GND

GND

2

1 R1144.7K1/10W5%

2

1 R1915101/10W1% 2

1 R1925101/10W1%

SA2_PROG_B

2

1 R1184.7K1/10W5%

SA2_CLK

VCCO_HP_EXT

SA2_CFGADDR0

18

131415

23

56789

1

10

4

1112

1617

J30

67840-8001

Page 33: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

GND

GND

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

GND

REGIN

CN

R_G

ND

RT

S_O

_B

DT

R_O

_B

DC

D_I

_B

NC

1

NC10

NC

2

NC

3

NC4

GPIO3

GPIO2

GPIO1

GPIO0

NC9

RS

T_B

RX

D_I

TX

D_O

SU

SP

EN

D

SU

SP

EN

D_B

DS

R_I

_B

VB

US

VDD

CT

R_G

ND

CT

S_I

_B

D+

D-

GND1

VIO

RI_I_B

GND

SCLSDA

A0A1A2

WP

VCCGND

GND

GND

SHLD4

VBUS

D_N

D_P

SHLD1

SHLD2

SHLD3

ID

GND

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

AFX I2C EEPROM

RS-232

USB/UART, AFX EEPROM

USB/UART BRIDGE

12-14-2012_16:02 C

01

VC7222 V7 HCG1155 MGT CHAR

33 73

2

1 R1194.7K1/10W5%

USB_D_P

VCCO_HP_EXT

1

2

C6020.1UF25VX5R

USB_D_N

2

1

X5R25V1UFC181 1

2

C1010.1UF25VX5R

5

9

1

2

3

678

4

J79

CONN_USB_MINI_B_TH

1 2L8

FERRITE-220

1

2

C440DNPDNP

65

123

7

84

U19

24LC32A

VCC5_AFX

1 2L7

FERRITE-220

1

2 3

4

X1 SP0503BAHTG

12V

200MW

7

29

23

27

28

10

21

13

14

15

16

17

18

19

20

9

24

25

12

11

26

8

6

30

22

3

4

2

5

1

U34 QFN_28

CP2103GM_MLP-28

1

2

C1831UF25VX5R

GNDGND

I2C_SCLI2C_SDA

I2C_WP

2

1

X5R25V1UFC604 1

2

C6030.1UF25VX5R

CP2103_VBUS

USB_TXD_0

NC

NC

USB_GPIO_0

USB_GPIO_1

USB_GPIO_2

USB_GPIO_3

USB_RTS_0_B

USB_CTS_I_B

USB_RXD_I

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

USB_SHIELD

USB_RTS_B

USB_VBUS

USB_GND

CP2103_VDD

Page 34: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

UTIL_2V5

GNDGND

GND

GND

GND

A0A1

A2RESET_B

SC0

SC1

SC2

SC3 SC4

SC5

SC6

SC7

SCLSD0

SD1

SD2

SD3

SD4

SD5

SD6

SD7

SDAVDD

VSS

SPARE_40

SCL

SPARE_76SPARE_75SPARE_74SPARE_73SPARE_72SPARE_71SPARE_70SPARE_69SPARE_68SPARE_67SPARE_66SPARE_65SPARE_64SPARE_63SPARE_62SPARE_61SPARE_60SPARE_59SPARE_58SPARE_57SPARE_56SPARE_55SPARE_54SPARE_53SPARE_52SPARE_51

RESET

SPARE_45SPARE_44SPARE_43SPARE_42SPARE_41

SPARE_39SPARE_38SPARE_37SPARE_36SPARE_35SPARE_34SPARE_33SPARE_32

SDA

SPARE_50

VCCOVCCOVCCO

VCC2V5VCC2V5

VCC3V3VCC3V3VCC3V3

VCC5VCC5VCC5

GND

GND

GND

GND

VCC5

VCC3V3

VCC2V5

VCC2V5VCCO

QTH 120-PIN CONNECTOR

SUPERCLOCK-2 MODULE, B1

SPARE_15

CONTROL_0

CONTROL_3

SPARE_31SPARE_30SPARE_29SPARE_28SPARE_27SPARE_26

CONTROL_23CONTROL_22CONTROL_21CONTROL_20CONTROL_19CONTROL_18CONTROL_17CONTROL_16CONTROL_15CONTROL_14CONTROL_13CONTROL_12CONTROL_11CONTROL_10CONTROL_9CONTROL_8CONTROL_7CONTROL_6CONTROL_5CONTROL_4

CONTROL_2

SPARE_24SPARE_23SPARE_22

SPARE_20SPARE_19SPARE_18SPARE_17SPARE_16

SPARE_14SPARE_13SPARE_12SPARE_11

GCLK_NGCLK_P

LVDS3_NLVDS3_P

LVDS2_NLVDS2_P

LVDS1_NLVDS1_P

CONTROL_1

SPARE_21

GND

GND

GND

GND

GND

GND

GNDGND

GND

GND

GND

GND

QTH 120-PIN CONNECTOR

SUPERCLOCK-2 MODULE, A1

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

GND

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

I2C BUS MUX

SUPERCLOCK-2 MODULE, I2C BUS MUX

SUPERCLOCK-2 MODULE INTERFACE

9 PLACES 2 PLACES 4 PLACES

7334

VC7222 V7 HCG1155 MGT CHAR

01

C12-14-2012_16:02

GTZ_MOD_I2C_SDAGTZ_MOD_I2C_SCL

FMC3_I2C_SDAFMC3_I2C_SCL

UTIL_3V3

2

1

R283

2

1R365

DUT_I2C_SDADUT_I2C_SCL

GTH_MOD_I2C_SCLGTH_MOD_I2C_SDACM_I2C_SCL

VCCO_HP_EXT

UTIL_3V3

2

1

R154

CM_I2C_SDA

2

1R151

2

1 R1522.00K1/16W

2

1

R159

UTIL_5V0

41

61

67

11911711511311110910710510310199979593918987858381797775737169

65

595755

5149474543

3937353331292725

211917

13119

531

63

53

7

15

23

123

125

127

121

J82

SAMTEC_QTH-060

42

62

120118116114112110108106104102100989694929088868482807876747270

66

60585654

5250484644

40383634

32302826

24222018

16141210

64

8

64

124

126

68

122

128

2

J82

SAMTEC_QTH-060

CM_RSTCM_I2C_SDA

2

1R149

2

1 R1502.00K1/16W

2

1

R153

2

1

R155

2

1R156

2

1

R157

2

1

R158

1

2

C1060.1UF25VX5R

12

213

5

7

9

11 14

16

18

20

224

6

8

10

13

15

17

19

2324

12

U39

PCA9547

UTIL_3V3UTIL_2V5

CM_LVDS3_NCM_LVDS3_P

CM_CTRL_0

CM_GCLK_NCM_GCLK_P

CM_LVDS2_NCM_LVDS2_P

CM_LVDS1_NCM_LVDS1_P CM_I2C_SCL

NC

NC

NCNCNCNC

NCNCNCNCNCNCNCNCNC

NCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNC

NC

NC

CM_CTRL_1

NCNCNCNC

NCNCNCNCNC

NCNC

CM_CTRL_2

CM_CTRL_4CM_CTRL_5CM_CTRL_6CM_CTRL_7CM_CTRL_8CM_CTRL_9CM_CTRL_10CM_CTRL_11CM_CTRL_12CM_CTRL_13CM_CTRL_14CM_CTRL_15CM_CTRL_16CM_CTRL_17CM_CTRL_18CM_CTRL_19CM_CTRL_20CM_CTRL_21CM_CTRL_22

NCNCNCNCNCNC

CM_CTRL_3

NC

CM_CTRL_23

FMC2_I2C_SDAFMC2_I2C_SCL

FMC1_I2C_SDAFMC1_I2C_SCL

2

1 R3642.00K1/16W

VCCO_HP_EXT

1

2

J230

2

1

R284

NCNCNCNC

Page 35: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

GND

GND

GND

GND

SIG

GND1

GND4

GND3

GND2

SIG

GND1

GND4

GND3

GND2

SIG

GND1

GND4

GND3

GND2

SIG

GND1

GND4

GND3

GND2

GND

NCGND

VCCOUT_B

OUT

OE

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

200MHz LVDS CLOCK

DIFFERENTIAL SMA CLOCKS

USER CLOCKS

12-14-2012_16:02 C

01

VC7222 V7 HCG1155 MGT CHAR

35 73

FMC1_CLK2_BIDIR_N

FMC1_CLK2_BIDIR_P

FMC2_LA00_CC_N

FMC2_LA00_CC_P

CLK_DIFF_2_N

CLK_DIFF_2_P

CLK_DIFF_1_P

12

J237

23

654

1

U35

200MHZ

UTIL_2V5

NC LVDS_OSC_NLVDS_OSC_P

1

2

C1070.1UF25VX5R

1

2

5

4

3

J101

32K10K-400L5

1

2

5

4

3

J98

32K10K-400L5

1

2

5

4

3

J99

32K10K-400L5

1

2

5

4

3

J100

32K10K-400L512

J238

CLK_DIFF_1_N

12

J239

12

J240

Page 36: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

UTIL_5V0

VCCAUX

IN OUT

GND

REF3012

GND

VIN

GND

EN ADJ

VOUT

NOTES:

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

XADC INTERFACE

SELECT

SELECT

XADC TEST INTERFACE

VCCADC

VREF

DUT THERMAL DIODE TEST POINTS

TO FPGA(BANK 0)

TO AFX SIDEBANDCONNECTOR

STAR CONNECTION, SEE XADC

7336

VC7222 V7 HCG1155 MGT CHAR

01

C12-14-2012_16:02

1

1

J105

1

2

3 4

5

U43TSOT_5

ADP123VCCADC

1 2

L9

FERRITE-600

AV_5V

1 2

3U45 SOT23_3

REF3012AIDBZT_SOT23_3

1

2

C46210UF25VX5R

NC

DXN_ADC

DXP_ADC

J150

VN_ADC_AFX

VP_ADC_AFX

VN_ADC

21

R254100

1/10W1%

21

R253100

1/10W1%

VP_ADC

J149

VREFP_ADC

XADC_AGND

2

1 R2451.00K1/16W1%

ADJ_ADP

2

1 R2462.00K1/16W1%

2

31

R2331K

1/4W10%

VCCADC_ADP

1

2

C4410.1UF25VX5R

XADC_AGND

1

2

C46110UF25VX5R

1 2

L10

FERRITE-600

1

2

C46010UF25VX5R

AV_5V

1

3

2

J142

1

3

2

J141

1 2

L11

FERRITE-600

VCCADC_FILTER

XADC_AGND

XADC_AGND

XADC_AGND

1

2

C4800.01UF25VX5R

1

1

J106

VREFP_3012

Page 37: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

UTIL_3V3

UTIL_3V3

GNDGND

GND

GRN

RED

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

UTIL_3V3

DIR

VCCB

B

VCCA

GND

A

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

USER PUSH BUTTONSUSER SWITCHES

INIT_B LED DONE LED

8 PLACES

PROG_B PUSH BUTTON

I/O HEADER

CONFIG AND USER I/O

CONFIGURATION AND USER I/O

12-14-2012_16:02 C

01

VC7222 V7 HCG1155 MGT CHAR

37 73

5

6

4

1

2

3

U26 SC70_6

SN74AVC1T45

2

1R1214.7K

1/10W5%

DONE_0 1

32

Q15

NDS331N460MW

1

J139YELLOW

VCCO_HP_EXT

1 2

34

DS25LED-GRN-RED

2

1R1204.7K

1/10W5%

INIT_B_0

2

1R2264.7K1/10W

5%

21

SW5

EVQ-11L07K

21

SW4

EVQ-11L07K

2

1R1224.7K

1/10W5%

GND

GND

1 2

3

5 6

7 8

9 10

4

1211

J125

HDR_2X6

21

R248

261

1/10W1%

21

R247

261

1/10W1%

USER_SW7

USER_SW2

2

1 R1402611/10W

2

1 R1483301/10W5%

USER_SW8

USER_SW6USER_SW5USER_SW4USER_SW3

USER_SW1

2

1

R130

2

1

R129

2

1

R128

2

1

R127

2

1

R126

2

1R125

2

1 R1244.7K1/10W5%

GND

GND

GND

21

DS21LED-GRN-SMT

21

SW3

EVQ-11L07K

12345678

161514131211109

SW2

SDA08H1SBD

GND

USER_PB1

USER_PB2

USER_SW1

USER_SW6

USER_SW5

USER_SW4

USER_SW3

USER_SW2

2

1

R131

VCCO_HP_EXT

PROGRAM_B_0

VCCO_0

VCCO_0

VCCO_0 VCCO_0

Page 38: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

USER APPLICATION LEDS

USER APPLICATION LEDS

12-14-2012_16:02 C

01

VC7222 V7 HCG1155 MGT CHAR

38 73

APP_LED1 APP_LED2 APP_LED3 APP_LED4 APP_LED5 APP_LED6 APP_LED7 APP_LED8

GND

UTIL_3V3

1

3

2

Q29

NDS331N460MW

2

1

DS14LED-GRN-SMT

2

1R4104.7K

1/10W

2

1 R2152611/10W

GND

UTIL_3V3

1

3

2

Q28

NDS331N460MW

2

1

DS13LED-GRN-SMT

2

1R4094.7K1/10W

2

1 R2142611/10W

GND

UTIL_3V3

1

3

2

Q27

NDS331N460MW

2

1

DS15LED-GRN-SMT

2

1R4084.7K

1/10W

2

1 R2132611/10W

GND

UTIL_3V3

1

3

2

Q26

NDS331N460MW

2

1

DS16LED-GRN-SMT

2

1R4074.7K

1/10W

2

1 R2122611/10W

GND

UTIL_3V3

1

3

2

Q25

NDS331N460MW

2

1

DS18LED-GRN-SMT

2

1R4064.7K

1/10W

2

1 R2112611/10W

GND

UTIL_3V3

1

3

2

Q24

NDS331N460MW

2

1

DS17LED-GRN-SMT

2

1R4054.7K1/10W

2

1 R2102611/10W

GND

UTIL_3V3

1

3

2

Q23

NDS331N460MW

2

1

DS20LED-GRN-SMT

2

1R4044.7K

1/10W

2

1 R2092611/10W

GND

UTIL_3V3

1

3

2

Q22

NDS331N460MW

2

1

DS19LED-GRN-SMT

2

1R4034.7K1/10W

2

1 R2082611/10W

Page 39: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

SIG

GND1

GND4

GND3

GND2

GND

GND

SIG

GND1

GND4

GND3

GND2

GND

GND

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

SIG

GND1

GND4

GND3

GND2

SIG

GND1

GND4

GND3

GND2

MGTZAGND_300_D30MGTZAGND_300_D29MGTZAGND_300_D28MGTZAGND_300_D27MGTZAGND_300_D26MGTZAGND_300_D25MGTZAGND_300_D24MGTZAGND_300_D23MGTZAGND_300_D22MGTZAGND_300_D21MGTZAGND_300_D20MGTZAGND_300_D19MGTZAGND_300_D18MGTZAGND_300_D17MGTZAGND_300_D16MGTZAGND_300_D15MGTZAGND_300_D14MGTZAGND_300_D13MGTZAGND_300_D12MGTZAGND_300_D11MGTZAGND_300_D10MGTZAGND_300_D9MGTZAGND_300_D8MGTZAGND_300_D7MGTZAGND_300_D6MGTZAGND_300_D5

MGTZAGND_300_C30MGTZAGND_300_C27MGTZAGND_300_C24MGTZAGND_300_C21MGTZAGND_300_C18MGTZAGND_300_C15MGTZAGND_300_C12MGTZAGND_300_C9MGTZAGND_300_C6MGTZAGND_300_C5

MGTZAGND_300_B30MGTZAGND_300_B29MGTZAGND_300_B27MGTZAGND_300_B25MGTZAGND_300_B23MGTZAGND_300_B21MGTZAGND_300_B19MGTZAGND_300_B17MGTZAGND_300_B15MGTZAGND_300_B13MGTZAGND_300_B11MGTZAGND_300_B9MGTZAGND_300_B7MGTZAGND_300_B5

MGTZAGND_300_A30MGTZAGND_300_A29MGTZAGND_300_A26MGTZAGND_300_A23MGTZAGND_300_A20MGTZAGND_300_A17MGTZAGND_300_A14MGTZAGND_300_A11MGTZAGND_300_A8MGTZAGND_300_A5

MGTZVCCL_300_L20MGTZVCCL_300_L18MGTZVCCL_300_L16MGTZVCCL_300_L14MGTZVCCH_300_J21MGTZVCCH_300_J19MGTZVCCH_300_J17MGTZVCCH_300_J15MGTZVCCH_300_G14MGTZVCCH_300_F20MGTZVCCH_300_F18MGTZVCCH_300_F16MGTZAVCC_300_B28MGTZAVCC_300_B26MGTZAVCC_300_B24MGTZAVCC_300_B22MGTZAVCC_300_B20MGTZAVCC_300_B18MGTZAVCC_300_B16MGTZAVCC_300_B14MGTZAVCC_300_B12MGTZAVCC_300_B10MGTZAVCC_300_B8MGTZAVCC_300_B6

TDO_0_K20MGTZ_THERM_OUT_300_G16MGTZ_THERM_IN_300_G17MGTZ_SENSE_GNDL_300_K14MGTZ_SENSE_GND_300_G20MGTZ_SENSE_AGND_300_F14MGTZ_SENSE_AVCC_300_E14MGTZ_SENSE_VCC_300_H20MGTZ_SENSE_VCCH_300_G21MGTZ_SENSE_VCCL_300_K15MGTZ_OBS_CLK_N_300_H18MGTZ_OBS_CLK_P_300_J18MGTZREFCLK1N_300_E20MGTZREFCLK1P_300_E21MGTZREFCLK0N_300_E16MGTZREFCLK0P_300_E17MGTZRXN7_300_A6MGTZRXP7_300_A7MGTZTXN7_300_A12MGTZTXP7_300_A13MGTZRXN6_300_C7MGTZRXP6_300_C8MGTZTXN6_300_C13MGTZTXP6_300_C14MGTZRXN5_300_A9MGTZRXP5_300_A10MGTZTXN5_300_A15MGTZTXP5_300_A16MGTZRXN4_300_C10MGTZRXP4_300_C11MGTZTXN4_300_C16MGTZTXP4_300_C17MGTZRXN3_300_A18MGTZRXP3_300_A19MGTZTXN3_300_A24MGTZTXP3_300_A25MGTZRXN2_300_C19MGTZRXP2_300_C20MGTZTXN2_300_C25MGTZTXP2_300_C26MGTZRXN1_300_A21MGTZRXP1_300_A22MGTZTXN1_300_A27MGTZTXP1_300_A28MGTZRXN0_300_C22MGTZRXP0_300_C23MGTZTXN0_300_C28MGTZTXP0_300_C29

XC7VH580THCG1155BANK 300

GND2

NC2

NC1

GND1

P20P19P18P17P16P15P14P13P12P11P10P9P8P7P6P5P4P3P2P1

SAMTEC

GND2

NC2

NC1

GND1

P20P19P18P17P16P15P14P13P12P11P10P9P8P7P6P5P4P3P2P1

SAMTEC

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

GTZ BANK 300

GTZ BANK 300

GTZ SUPPLY DECOUPLING

12-14-2012_16:02 C

01

VC7222 V7 HCG1155 MGT CHAR

39 7321

R20301/10W

300_RX3_P300_RX3_N300_TX3_P300_TX3_N300_TX2_P300_TX2_N300_RX2_P300_RX2_N300_RX1_N300_RX1_P300_TX1_N300_TX1_P300_TX0_N300_TX0_P300_RX0_N300_RX0_P

300_RX7_P300_RX7_N

300_TX7_N300_TX7_P

300_TX6_N300_TX6_P

300_RX6_N300_RX6_P

300_RX5_N300_RX5_P300_TX5_N300_TX5_P300_TX4_N300_TX4_P300_RX4_N300_RX4_P

24

23

22

21

2019181716151413121110987654321

J25

CCC-J-XXX

24

23

22

21

2019181716151413121110987654321

J18

CCC-J-XXX

MGTZVCCL_SPY_P

D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16D15D14D13D12D11D10D9D8D7D6D5C30C27C24C21C18C15C12C9C6C5B30B29B27B25B23B21B19B17B15B13B11B9B7B5A30A29A26A23A20A17A14A11A8A5L20L18L16L14J21J19J17J15G14F20F18F16B28B26B24B22B20B18B16B14B12B10B8B6

K20G16G17K14G20F14E14H20G21K15H18J18E20E21E16E17A6A7A12A13C7C8C13C14A9A10A15A16C10C11C16C17A18A19A24A25C19C20C25C26A21A22A27A28C22C23C28C29

U1SOC_OZ_IRON_FF1156

SOC_IRON_IDI_HC1155

MGTZAVCC_SPY_N

MGTZVCCH_SPY_P

MGTZAVCC_SPY_P

300_REFCLK0_P

300_REFCLK0_N

NCNC

NCNC

1 2

25V0.1UFC58

300_REFCLK0_C_N

1 2

25V0.1UFC52

300_REFCLK1_C_P 300_REFCLK1_P

1

2

5

4

3

J57

32K10K-400L5

1

2

5

4

3

J46

32K10K-400L5

300_MGTZ_OBS_CLK_P

MGTZ_THERM_IN_300MGTZ_THERM_OUT_300

MGTZ_SENSE_GNDL_300MGTZ_SENSE_GND_300MGTZ_SENSE_AGND_300MGTZ_SENSE_AVCC_300MGTZ_SENSE_VCC_300MGTZ_SENSE_VCCH_300MGTZ_SENSE_VCCL_300300_MGTZ_OBS_CLK_N

GND

MGTZVCCLMGTZVCCH

GND

1

2

C1514.7UF10V

MGTZAVCC

MGTZVCCL

MGTZVCCH

MGTZAVCC

GND

NC

NC

300_TX0_P300_TX0_N300_RX0_P300_RX0_N300_TX1_P300_TX1_N300_RX1_P300_RX1_N300_TX2_P300_TX2_N300_RX2_P300_RX2_N300_TX3_P300_TX3_N300_RX3_P300_RX3_N300_TX4_P300_TX4_N300_RX4_P300_RX4_N300_TX5_P300_TX5_N300_RX5_P300_RX5_N300_TX6_P300_TX6_N300_RX6_P300_RX6_N300_TX7_P300_TX7_N300_RX7_P300_RX7_N300_REFCLK0_P300_REFCLK0_N300_REFCLK1_P300_REFCLK1_N

NC

NC

GND

1

2

C1524.7UF10V

GND

1

2

C1534.7UF10V

GND

1

2

5

4

3

J47

32K10K-400L5

1

2

5

4

3

J56

32K10K-400L5

300_REFCLK1_C_N 300_REFCLK1_N

1 2

25V0.1UFC60

300_REFCLK0_C_P 1 2

25V0.1UFC63

NCNC

NCNC

AFX_TDO_0

TDO_0

Page 40: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

NOTES:

KEEP NETS AS SHORT AS POSSIBLE

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

GTZ SENSE AND THERMAL SIGNALS

GTZ BANK 300 - SENSE AND THERMAL SIGNAL CONNECTORS

ROUTE DIFFERENTIALLY WITH 100-OHM CONTROLLED IMPEDANCE

12-14-2012_16:02 C

01

VC7222 V7 HCG1155 MGT CHAR

40 73

12

3

J42

CON_SMA_SCREW_ON

1

J40

2

2

1

12

3

J45

CON_SMA_SCREW_ON

12

3

J44

CON_SMA_SCREW_ON

GND

GND

12

3

J43

CON_SMA_SCREW_ON

12

3

J39

CON_SMA_SCREW_ON

12

3

J38

CON_SMA_SCREW_ON

GND

GND

12

3

J37

CON_SMA_SCREW_ON

12

3

J36

CON_SMA_SCREW_ON

12

3

J35

CON_SMA_SCREW_ON

12

3

J34

CON_SMA_SCREW_ON

GND

MGTZ_SENSE_VCC_300

MGTZ_SENSE_GND_300

300_MGTZ_OBS_CLK_P

300_MGTZ_OBS_CLK_N

MGTZ_SENSE_VCCL_300

MGTZ_SENSE_GNDL_300

MGTZ_SENSE_VCCH_300

MGTZ_SENSE_GND_300

MGTZ_SENSE_AGND_300

MGTZ_SENSE_AVCC_300

MGTZ_THERM_IN_300

MGTZ_THERM_OUT_300

1

1

J41

Page 41: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

GND2

NC2

NC1

GND1

P20P19P18P17P16P15P14P13P12P11P10P9P8P7P6P5P4P3P2P1

SAMTEC

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

MGTREFCLK1N_113_AA5MGTREFCLK1P_113_AA6MGTREFCLK0N_113_AC5MGTREFCLK0P_113_AC6MGTHRXN3_113_V3MGTHRXP3_113_V4MGTHTXN3_113_U1MGTHTXP3_113_U2MGTHRXN2_113_AB3MGTHRXP2_113_AB4MGTHTXN2_113_W1MGTHTXP2_113_W2MGTHRXN1_113_AD3MGTHRXP1_113_AD4MGTHTXN1_113_AA1MGTHTXP1_113_AA2MGTHRXN0_113_Y3MGTHRXP0_113_Y4MGTHTXN0_113_AC1MGTHTXP0_113_AC2

XC7VH580THCG1155BANK 1132 PLACES

2 PLACES

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

GTH BANK 113

GTH BANK 113

12-14-2012_16:02 C

01

VC7222 V7 HCG1155 MGT CHAR

41 73

AA5AA6AC5AC6V3V4U1U2AB3AB4W1W2AD3AD4AA1AA2Y3Y4AC1AC2

U1SOC_OZ_IRON_FF1156

SOC_IRON_IDI_HC1155

1 2

C81

1 2

C80

0.1UF

1 2

C70

1 2

C690.1UF

24

23

22

21

2019181716151413121110987654321

J28

CCC-J-020

GND

113_REFCLK0_N113_REFCLK0_C_P

113_REFCLK1_C_P

113_REFCLK0_C_N

113_REFCLK1_P

113_REFCLK0_P

NC

NC

113_TX3_N113_TX3_P

113_TX2_N113_TX2_P

113_TX0_N113_TX0_P

113_RX0_P

113_TX1_P113_TX1_N

113_RX1_P113_RX1_N

113_RX2_P113_RX2_N

113_RX3_P113_RX3_N

113_RX0_N

113_REFCLK1_N113_REFCLK1_C_N113_TX0_P113_TX0_N113_RX0_P113_RX0_N113_TX1_P113_TX1_N113_RX1_P113_RX1_N113_TX2_P113_TX2_N113_RX2_P113_RX2_N113_TX3_P113_TX3_N113_RX3_P113_RX3_N113_REFCLK0_P113_REFCLK0_N113_REFCLK1_P113_REFCLK1_N

Page 42: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

GND2

NC2

NC1

GND1

P20P19P18P17P16P15P14P13P12P11P10P9P8P7P6P5P4P3P2P1

SAMTEC

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

MGTREFCLK1N_114_U5MGTREFCLK1P_114_U6MGTREFCLK0N_114_W5MGTREFCLK0P_114_W6MGTHRXN3_114_M3MGTHRXP3_114_M4MGTHTXN3_114_J1MGTHTXP3_114_J2MGTHRXN2_114_K3MGTHRXP2_114_K4MGTHTXN2_114_L1MGTHTXP2_114_L2MGTHRXN1_114_P3MGTHRXP1_114_P4MGTHTXN1_114_N1MGTHTXP1_114_N2MGTHRXN0_114_T3MGTHRXP0_114_T4MGTHTXN0_114_R1MGTHTXP0_114_R2

XC7VH580THCG1155BANK 1142 PLACES

2 PLACES

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

GTH BANK 114

GTH BANK 114

12-14-2012_16:02 C

01

VC7222 V7 HCG1155 MGT CHAR

42 73

U5U6W5W6M3M4J1J2K3K4L1L2P3P4N1N2T3T4R1R2

U1SOC_OZ_IRON_FF1156

SOC_IRON_IDI_HC1155

1 2

C617

1 2

C616

0.1UF

1 2

C615

1 2

C6140.1UF

24

23

22

21

2019181716151413121110987654321

J85

CCC-J-020

GND

114_REFCLK0_N114_REFCLK0_C_P

114_REFCLK1_C_P

114_REFCLK0_C_N

114_REFCLK1_P

114_REFCLK0_P

114_TX1_N114_TX1_P

114_RX1_P114_RX1_N

114_TX2_N114_TX2_P

114_RX2_P114_RX2_N

114_TX3_N114_TX3_P

114_RX3_P114_RX3_N

114_REFCLK0_N114_REFCLK0_P

114_REFCLK1_P114_REFCLK1_N

114_TX0_N114_TX0_P

114_RX0_P114_RX0_N

NC

NC

114_TX3_N114_TX3_P

114_TX2_N114_TX2_P

114_TX0_N114_TX0_P

114_RX0_P

114_TX1_P114_TX1_N

114_RX1_P114_RX1_N

114_RX2_P114_RX2_N

114_RX3_P114_RX3_N

114_RX0_N

114_REFCLK1_N114_REFCLK1_C_N

Page 43: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

MGTAVTT

GND2

NC2

NC1

GND1

P20P19P18P17P16P15P14P13P12P11P10P9P8P7P6P5P4P3P2P1

SAMTEC

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

MGTRREF_115_AE1MGTAVTTRCAL_115_AE2MGTREFCLK1N_115_R5MGTREFCLK1P_115_R6MGTREFCLK0N_115_N5MGTREFCLK0P_115_N6MGTHRXN3_115_B3MGTHRXP3_115_B4MGTHTXN3_115_A1MGTHTXP3_115_A2MGTHRXN2_115_D3MGTHRXP2_115_D4MGTHTXN2_115_C1MGTHTXP2_115_C2MGTHRXN1_115_F3MGTHRXP1_115_F4MGTHTXN1_115_E1MGTHTXP1_115_E2MGTHRXN0_115_H3MGTHRXP0_115_H4MGTHTXN0_115_G1MGTHTXP0_115_G2

XC7VH580THCG1155BANK 1152 PLACES

2 PLACES

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

GTH BANK 115

GTH BANK 115

TRACE LENGTH FROM RESISTOR PINS TO FPGA PINS MGTRREFAND MGTAVTTRCAL MUST BE OF EQUAL LENGTH AND GEOMETRY.

NOTES: 12-14-2012_16:02 C

01

VC7222 V7 HCG1155 MGT CHAR

43 73

AE1AE2R5R6N5N6B3B4A1A2D3D4C1C2F3F4E1E2H3H4G1G2

U1SOC_OZ_IRON_FF1156

SOC_IRON_IDI_HC1155

1

1

1 2

C621

1 2

C620

0.1UF

1 2

C619

1 2

C6180.1UF

24

23

22

21

2019181716151413121110987654321

J86

CCC-J-020

GND

115_TX1_N115_TX1_P

115_RX1_P115_RX1_N

115_TX2_N115_TX2_P

115_RX2_P115_RX2_N

115_TX3_N115_TX3_P

115_RX3_P115_RX3_N

115_REFCLK0_N115_REFCLK0_P

115_REFCLK1_P115_REFCLK1_N

115_TX0_N115_TX0_P

115_RX0_P115_RX0_N

115_REFCLK0_N115_REFCLK0_C_P

115_REFCLK1_C_P

115_REFCLK0_C_N

115_REFCLK1_P

115_REFCLK0_P

NC

NC

115_TX3_N115_TX3_P

115_TX2_N115_TX2_P

115_TX0_N115_TX0_P

115_RX0_P

115_TX1_P115_TX1_N

115_RX1_P115_RX1_N

115_RX2_P115_RX2_N

115_RX3_P115_RX3_N

115_RX0_N

115_REFCLK1_N115_REFCLK1_C_N

2

1 R3401001/10W

115_MGTRREF

Page 44: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

GND2

NC2

NC1

GND1

P20P19P18P17P16P15P14P13P12P11P10P9P8P7P6P5P4P3P2P1

SAMTEC

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

MGTREFCLK1N_213_AA30MGTREFCLK1P_213_AA29MGTREFCLK0N_213_AC30MGTREFCLK0P_213_AC29MGTHRXN3_213_V32MGTHRXP3_213_V31MGTHTXN3_213_U34MGTHTXP3_213_U33MGTHRXN2_213_AB32MGTHRXP2_213_AB31MGTHTXN2_213_W34MGTHTXP2_213_W33MGTHRXN1_213_AD32MGTHRXP1_213_AD31MGTHTXN1_213_AA34MGTHTXP1_213_AA33MGTHRXN0_213_Y32MGTHRXP0_213_Y31MGTHTXN0_213_AC34MGTHTXP0_213_AC33

XC7VH580THCG1155BANK 2132 PLACES

2 PLACES

RN

ASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

SCHEM, ROHS COMPLIANT

GTH BANK 213

GTH BANK 213

12-14-2012_16:02 C

01

VC7222 V7 HCG1155 MGT CHAR

44 73

AA30AA29AC30AC29V32V31U34U33

AB32AB31W34W33

AD32AD31AA34AA33Y32Y31

AC34AC33

U1SOC_OZ_IRON_FF1156

SOC_IRON_IDI_HC1155

1 2

C625

1 2

C624

0.1UF

1 2

C623

1 2

C6220.1UF

24

23

22

21

2019181716151413121110987654321

J158

CCC-J-020

GND

213_TX1_N213_TX1_P

213_RX1_P213_RX1_N

213_TX2_N213_TX2_P

213_RX2_P213_RX2_N

213_TX3_N213_TX3_P

213_RX3_P213_RX3_N

213_REFCLK0_N213_REFCLK0_P

213_REFCLK1_P213_REFCLK1_N

213_TX0_N213_TX0_P

213_RX0_P213_RX0_N

213_REFCLK0_N213_REFCLK0_C_P

213_REFCLK1_C_P

213_REFCLK0_C_N

213_REFCLK1_P

213_REFCLK0_P

NC

NC

213_TX3_N213_TX3_P

213_TX2_N213_TX2_P

213_TX0_N213_TX0_P

213_RX0_P

213_TX1_P213_TX1_N

213_RX1_P213_RX1_N

213_RX2_P213_RX2_N

213_RX3_P213_RX3_N

213_RX0_N

213_REFCLK1_N213_REFCLK1_C_N

Page 45: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

GND2

NC2

NC1

GND1

P20P19P18P17P16P15P14P13P12P11P10P9P8P7P6P5P4P3P2P1

SAMTEC

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

MGTREFCLK1N_214_U30MGTREFCLK1P_214_U29MGTREFCLK0N_214_W30MGTREFCLK0P_214_W29MGTHRXN3_214_M32MGTHRXP3_214_M31MGTHTXN3_214_J34MGTHTXP3_214_J33MGTHRXN2_214_K32MGTHRXP2_214_K31MGTHTXN2_214_L34MGTHTXP2_214_L33MGTHRXN1_214_P32MGTHRXP1_214_P31MGTHTXN1_214_N34MGTHTXP1_214_N33MGTHRXN0_214_T32MGTHRXP0_214_T31MGTHTXN0_214_R34MGTHTXP0_214_R33

XC7VH580THCG1155BANK 2142 PLACES

2 PLACES

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

GTH BANK 214

GTH BANK 214

12-14-2012_16:02 C

01

VC7222 V7 HCG1155 MGT CHAR

45 73

U30U29W30W29M32M31J34J33K32K31L34L33P32P31N34N33T32T31R34R33

U1SOC_OZ_IRON_FF1156

SOC_IRON_IDI_HC1155

GND

1 2

C629

1 2

C628

0.1UF

1 2

C627

1 2

C6260.1UF

24

23

22

21

2019181716151413121110987654321

J159

CCC-J-020

214_TX1_N214_TX1_P

214_RX1_P214_RX1_N

214_TX2_N214_TX2_P

214_RX2_P214_RX2_N

214_TX3_N214_TX3_P

214_RX3_P214_RX3_N

214_REFCLK0_N214_REFCLK0_P

214_REFCLK1_P214_REFCLK1_N

214_TX0_N214_TX0_P

214_RX0_P214_RX0_N

214_REFCLK0_N214_REFCLK0_C_P

214_REFCLK1_C_P

214_REFCLK0_C_N

214_REFCLK1_P

214_REFCLK0_P

NC

NC

214_TX3_N214_TX3_P

214_TX2_N214_TX2_P

214_TX0_N214_TX0_P

214_RX0_P

214_TX1_P214_TX1_N

214_RX1_P214_RX1_N

214_RX2_P214_RX2_N

214_RX3_P214_RX3_N

214_RX0_N

214_REFCLK1_N214_REFCLK1_C_N

Page 46: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

MGTAVTT

GND2

NC2

NC1

GND1

P20P19P18P17P16P15P14P13P12P11P10P9P8P7P6P5P4P3P2P1

SAMTEC

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

MGTRREF_215_AE34MGTAVTTRCAL_215_AE33MGTREFCLK1N_215_R30MGTREFCLK1P_215_R29MGTREFCLK0N_215_N30MGTREFCLK0P_215_N29MGTHRXN3_215_B32MGTHRXP3_215_B31MGTHTXN3_215_A34MGTHTXP3_215_A33MGTHRXN2_215_D32MGTHRXP2_215_D31MGTHTXN2_215_C34MGTHTXP2_215_C33MGTHRXN1_215_F32MGTHRXP1_215_F31MGTHTXN1_215_E34MGTHTXP1_215_E33MGTHRXN0_215_H32MGTHRXP0_215_H31MGTHTXN0_215_G34MGTHTXP0_215_G33

XC7VH580THCG1155BANK 2152 PLACES

2 PLACES

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

GTH BANK 215

GTH BANK 215

NOTES:

AND MGTAVTTRCAL MUST BE OF EQUAL LENGTH AND GEOMETRY.TRACE LENGTH FROM RESISTOR PINS TO FPGA PINS MGTRREF

12-14-2012_16:02 C

01

VC7222 V7 HCG1155 MGT CHAR

46 73

AE34AE33R30R29N30N29B32B31A34A33D32D31C34C33F32F31E34E33H32H31G34G33

U1SOC_OZ_IRON_FF1156

SOC_IRON_IDI_HC1155

1

GND

215_MGTRREF

1 2

C1178

1 2

C1177

0.1UF

1 2

C1176

1 2

C11750.1UF

24

23

22

21

2019181716151413121110987654321

J241

CCC-J-020

215_TX1_N215_TX1_P

215_RX1_P215_RX1_N

215_TX2_N215_TX2_P

215_RX2_P215_RX2_N

215_TX3_N215_TX3_P

215_RX3_P215_RX3_N

215_REFCLK0_N215_REFCLK0_P

215_REFCLK1_P215_REFCLK1_N

215_TX0_N215_TX0_P

215_RX0_P215_RX0_N

215_REFCLK0_N215_REFCLK0_C_P

215_REFCLK1_C_P

215_REFCLK0_C_N

215_REFCLK1_P

215_REFCLK0_P

NC

NC

215_TX3_N215_TX3_P

215_TX2_N215_TX2_P

215_TX0_N215_TX0_P

215_RX0_P

215_TX1_P215_TX1_N

215_RX1_P215_RX1_N

215_RX2_P215_RX2_N

215_RX3_P215_RX3_N

215_RX0_N

215_REFCLK1_N215_REFCLK1_C_N

2

1 R701001/10W

1

Page 47: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

MGTVCCAUX

MGTVCCAUX

MGTVCCAUX_G20_V29

XC7VH580THCG1155BANK MGTVCCAUX_G20

MGTVCCAUX_G10_V6

XC7VH580THCG1155BANK MGTVCCAUX_G10

MGTAVTT

MGTAVTT

MGTAVTT_G10_B2MGTAVTT_G10_F2MGTAVTT_G10_K2MGTAVTT_G10_P2MGTAVTT_G10_V2

MGTAVTT_G10_AB2MGTAVTT_G10_AD2

XC7VH580THCG1155BANK MGTAVTT_G10

MGTAVCC

MGTAVCC

MGTAVCC

MGTAVCC_G10_C4MGTAVCC_G10_G4MGTAVCC_G10_L4MGTAVCC_G10_P5MGTAVCC_G10_R4MGTAVCC_G10_W4MGTAVCC_G10_AB5MGTAVCC_G10_AC4

XC7VH580THCG1155BANK MGTAVCC_G10

MGTAVTT_G20_B33MGTAVTT_G20_F33MGTAVTT_G20_K33MGTAVTT_G20_P33MGTAVTT_G20_V33

MGTAVTT_G20_AB33MGTAVTT_G20_AD33

XC7VH580THCG1155BANK MGTAVTT_G20

MGTAVCC_G20_C31MGTAVCC_G20_G31MGTAVCC_G20_L31MGTAVCC_G20_P30MGTAVCC_G20_R31MGTAVCC_G20_W31MGTAVCC_G20_AB30MGTAVCC_G20_AC31

XC7VH580THCG1155BANK MGTAVCC_G20

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

RN

ASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

SCHEM, ROHS COMPLIANTMGT POWER DECOUPLING

GTH POWER, MGTAVCC DECOUPLING

NOTES:

RECOMMENDED MGT DECOUPLING PER UG476 (v1.6) SEPTEMBER 11, 2012

7347

VC7222 V7 HCG1155 MGT CHAR

01

C12-14-2012_16:02

MGTAVTT_SPY_P

MGTAVTT_R_SPY_PMGTAVTT_L_SPY_P

MGTAVCC_SPY_P

MGTAVCC_L_SPY_P

MGTAVCC_L_SPY_P

21

1/10W10R441

MGTAVTT_L_SPY_P

MGTAVCC_R_SPY_P MGTAVTT_R_SPY_P

C31G31L31P30R31W31AB30AC31

U1 SOC_OZ_IRON_FF1156

SOC_IRON_IDI_HC1155

B33F33K33P33V33AB33AD33

U1 SOC_OZ_IRON_FF1156

SOC_IRON_IDI_HC1155

C4G4L4P5R4W4AB5AC4

U1 SOC_OZ_IRON_FF1156

SOC_IRON_IDI_HC1155

1

1

2

C9074.7UF10VX5R

GND

2

1 C9064.7UF10VX5R

B2F2K2P2V2AB2AD2

U1 SOC_OZ_IRON_FF1156

SOC_IRON_IDI_HC1155

V6

U1 SOC_OZ_IRON_FF1156

SOC_IRON_IDI_HC1155

V29

U1 SOC_OZ_IRON_FF1156

SOC_IRON_IDI_HC1155

1

2

C1924.7UF10VX5R

1

2

C1934.7UF10VX5R

GND

MGTAVTT

1

2

C1954.7UF10VX5R

1

2

C1944.7UF10VX5R

MGTVCCAUX

GND

21

1/10W10R454

21

1/10W10R456

21

1/10W10R455

MGTAVCC_R_SPY_P

Page 48: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

GND2

NC2

NC1

GND1P20

P19P18P17P16P15P14P13P12P11P10P9P8P7P6P5P4P3P2P1

SAMTEC

GND2

NC2

NC1

GND1

P20P19P18P17P16P15P14P13P12P11P10P9P8P7P6P5P4P3P2P1

SAMTEC

GND2

NC2

NC1

GND1

P20P19P18P17P16P15P14P13P12P11P10P9P8P7P6P5P4P3P2P1

SAMTEC

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

USE "FIGURE 8" PATTERN TO MATCH P AND N PAIRS. SEE LAYOUTGUIDELINES FOR DETAILS.

NOTES:

GTH TEST STRUCTURE

SAMTEC BULLSEYE TEST STRUCTURES

SAMTEC BULLSEYE TEST STRUCTURES

GTZ TEST STRUCTURE

12-14-2012_16:02 C

01

VC7222 V7 HCG1155 MGT CHAR

48 73

1

J145

1

J135

1

J134

1

J133

1

J117

1

J116

1

J115

1

J120

1

J119

1

J118

1

J127

1

J126

1

J132

1

J172

1

J171

1

J180

1

J179

1

J178

1

J177

1

J176

1

J175

1

J174

1

J173

1

J164

1

J161

MGT_TEST4_PMGT_TEST4_NMGT_TEST5_P

MGT_TEST1_P

MGT_TEST3_N

MGT_TEST5_N

1

MGT_TEST1_N

24

23

22

21

2019181716151413121110987654321

J7

CCC-J-020

24

23

22

21

2019181716151413121110987654321

J87

CCC-J-020

1

GND

NC

NC

GND GND

24232221

2019181716151413121110987654321

J107

CCC-J-020

NC

NC

NC

NC

GTZ_TEST1_PGTZ_TEST1_NGTZ_TEST2_PGTZ_TEST2_NGTZ_TEST3_PGTZ_TEST3_NGTZ_TEST4_PGTZ_TEST4_NGTZ_TEST5_PGTZ_TEST5_N

GTZ_TEST10_NGTZ_TEST10_PGTZ_TEST9_NGTZ_TEST9_PGTZ_TEST8_NGTZ_TEST8_PGTZ_TEST7_NGTZ_TEST7_PGTZ_TEST6_NGTZ_TEST6_P

MGT_TEST2_PMGT_TEST2_NMGT_TEST3_P

1

J111

1

J113

1

J114

1

J110

1

J109

1

J108

1

J128

1

J129

1

J130

1

J122

1

J137

1

J136

1

J140

1

J138

1

J144

1

J143

1

J146

1

J148

1

J147

1

J152

1

J151

1

J154

1

J153

1

J156

1

J155

1

J160

1

J157

Page 49: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

VCCAUX

VCCO_0_U10VCCO_0_AA10

M1_0_Y8M0_0_AB26M2_0_AA27DONE_0_U27

PROGRAM_B_0_W27INIT_B_0_V8TDI_0_P14TMS_0_R15TCK_0_N17CCLK_0_P18

VCCBATT_0_P20VN_0_V17VP_0_U18

VREFP_0_V18VREFN_0_U17DXP_0_W18

GNDADC_0_T17VCCADC_0_T18

DXN_0_W17

XC7VH580THCG1155BANK 0

GND

I0

I1

S

VCC

Y

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

BANK 0PLACE CAPACITORS NEAR THE CENTER OF THE DUT BGA, AS CLOSEAS POSSIBLE TO THEIR RESPECTIVE DUT PINS

STAR CONNECTION, SEE XADC

2 PLACES

BANKS 14/15 ARE CONNECTED TO VCCO_HPTHE CVGBVS IS PULLED HIGH SINCE BANK 0 IS 2.5V AND CONFIGURATION

2 PLACES

2 PLACES

2 PLACES

PLACE MUX AS CLOSE AS POSSIBLE TO THE DUT

12-14-2012_16:02 C

01

VC7222 V7 HCG1155 MGT CHAR

49 73

VCCO_0

1

2

1 R1651001/10W

2

1 R1641001/10W

21

R32001/10W

2

3

1

6

5

4

U41SC70_6

NC7SV157

4

DXN_ADC

DXP_ADC

VP_ADCVN_ADC

DONE_0PROGRAM_B_0

INIT_B_0TDI_0TMS_0

VCCADC

AFX_TDI_0

AFX_TMS_021

R281

21

R439

01/10W

TCK_0

3

U10AA10

Y8AB26AA27U27W27V8P14R15N17P18P20V17U18V18U17W18T17T18W17

U1 SOC_OZ_IRON_FF1156

SOC_IRON_IDI_HC1155

1

GND

GND 2

1R232

2

1R229DNP

2

1R227

2

1 R228DNP

2

XADC_AGND

1

2

C4581

2

C4590.1UF25V

2

XADC_AGND

2

1 R2311001/10W

VCCO_0

VCCO_0

GND

4

GND

SYSACE_TCK_0

CCLK_0

M2_0M0_0M1_0

VREFP_ADC

DUT_MBDETECT_3V3_B

AFX_TCK_0

VCCO_0

VCCO_0

Page 50: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

VCCO_HP

VCCO_HP

VCCO_HP

GND

VCCO_HP

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

VCCO_13_AP22VCCO_13_AN25VCCO_13_AK24VCCO_13_AJ27VCCO_13_AF26VCCO_13_AC25VCCO_13_AG23

IO_25_VRP_13_AN22IO_L24N_T3_13_AM22IO_L24P_T3_13_AL22IO_L23N_T3_13_AN24IO_L23P_T3_13_AM24IO_L22N_T3_13_AP26IO_L22P_T3_13_AN26

IO_L21N_T3_DQS_13_AP23IO_L21P_T3_DQS_13_AN23

IO_L20N_T3_13_AL23IO_L20P_T3_13_AK23

IO_L19N_T3_VREF_13_AP25IO_L19P_T3_13_AP24IO_L18N_T2_13_AJ23IO_L18P_T2_13_AH23IO_L17N_T2_13_AF25IO_L17P_T2_13_AE25IO_L16N_T2_13_AF23IO_L16P_T2_13_AE23

IO_L15N_T2_DQS_13_AG24IO_L15P_T2_DQS_13_AF24

IO_L14N_T2_SRCC_13_AG26IO_L14P_T2_SRCC_13_AG25IO_L13N_T2_MRCC_13_AJ24IO_L13P_T2_MRCC_13_AH24IO_L12N_T1_MRCC_13_AL25IO_L12P_T1_MRCC_13_AL24IO_L11N_T1_SRCC_13_AK25IO_L11P_T1_SRCC_13_AJ25

IO_L10N_T1_13_AM26IO_L10P_T1_13_AM25

IO_L9N_T1_DQS_13_AJ26IO_L9P_T1_DQS_13_AH26

IO_L8N_T1_13_AK27IO_L8P_T1_13_AK26IO_L7N_T1_13_AH27IO_L7P_T1_13_AG27

IO_L6N_T0_VREF_13_AF27IO_L6P_T0_13_AE27IO_L5N_T0_13_AC24IO_L5P_T0_13_AB24IO_L4N_T0_13_AC27IO_L4P_T0_13_AC26

IO_L3N_T0_DQS_13_AE26IO_L3P_T0_DQS_13_AD26

IO_L2N_T0_13_AD25IO_L2P_T0_13_AD24IO_L1N_T0_13_AD23IO_L1P_T0_13_AC23IO_0_VRN_13_AL27

XC7VH580THCG1155BANK 13

VCCO_14_AP32VCCO_14_AM28VCCO_14_AL31VCCO_14_AK34VCCO_14_AH30VCCO_14_AG33VCCO_14_AE29

IO_25_VRP_14_AP31IO_L24N_T3_A00_D16_14_AP28IO_L24P_T3_A01_D17_14_AN28IO_L23N_T3_A02_D18_14_AN31IO_L23P_T3_A03_D19_14_AM31IO_L22N_T3_A04_D20_14_AP30IO_L22P_T3_A05_D21_14_AP29

IO_L21N_T3_DQS_A06_D22_14_AM30IO_L21P_T3_DQS_14_AL30

IO_L20N_T3_A07_D23_14_AN27IO_L20P_T3_A08_D24_14_AM27

IO_L19N_T3A09D25_VREF_14_AN29IO_L19P_T3_A10_D26_14_AM29IO_L18N_T2_A11_D27_14_AP33IO_L18P_T2_A12_D28_14_AN33IO_L17N_T2_A13_D29_14_AJ34IO_L17P_T2_A14_D30_14_AJ33IO_L16N_T2_A15_D31_14_AM34

IO_L16P_T2_CSI_B_14_AL34IO_L15N_T2_DQSDOUT_CSOB_14_AN32

IO_L15P_T2_DQS_RDWR_B_14_AM32IO_L14N_T2_SRCC_14_AL33IO_L14P_T2_SRCC_14_AK33IO_L13N_T2_MRCC_14_AL32IO_L13P_T2_MRCC_14_AK32IO_L12N_T1_MRCC_14_AK31IO_L12P_T1_MRCC_14_AK30IO_L11N_T1_SRCC_14_AJ31IO_L11P_T1_SRCC_14_AH31IO_L10N_T1_D15_14_AH34IO_L10P_T1_D14_14_AG34

IO_L9N_T1_DQS_D13_14_AH33IO_L9P_T1_DQS_14_AH32IO_L8N_T1_D12_14_AG32IO_L8P_T1_D11_14_AG31IO_L7N_T1_D10_14_AG30IO_L7P_T1_D09_14_AF30

IO_L6N_T0_D08_VREF_14_AL29IO_L6P_T0_FCS_B_14_AL28IO_L5N_T0_D07_14_AK28IO_L5P_T0_D06_14_AJ28IO_L4N_T0_D05_14_AH29IO_L4P_T0_D04_14_AH28

IO_L3N_T0_DQS_EMCCLK_14_AG29IO_L3P_T0_DQS_PUDC_B_14_AF29

IO_L2N_T0_D03_14_AJ30IO_L2P_T0_D02_14_AJ29

IO_L1N_T0_D01_DIN_14_AF28IO_L1P_T0_D00_MOSI_14_AE28

IO_0_VRN_14_AN34

XC7VH580THCG1155BANK 14

GND

AB0

B1

S VCC

USER IO (PUSH BUTTONS)

SYSTEM CLOCK

I2C (DUT MASTER)

PMBUS (DUT MASTER)

USER IO (LEDS)

USER IO (SWITCHES)

DEDICATED PINS

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

USER IO (LEDS)

I/O BANKS

USER DIFFSMA CLOCK

USER IO (SWITCHES)

GTZ RESET

DEDICATED PINS

GTZ JTAG (TMS)

GTZ JTAG (TRST)

GTZ JTAG (TDI)

GTZ JTAG (TDO)

GTZ JTAG (TCK)

2 PLACES

PLACE ANALOG SWITCH AS CLOSE AS POSSIBLETO THE DUT

7350

VC7222 V7 HCG1155 MGT CHAR

01

C12-14-2012_16:02

VCCO_HP_EXT

1

MAC_JTAG_ENABLE_B

IO_L11N_T1_SRCC_14 21

R44001/10W

2

1R167

2

1 R166DNP

MAC_TCK

GND

UTIL_3V3

2

43

1

65

U56 SC70_6

FSA4157P6X

AP32AM28AL31AK34AH30AG33AE29

AP31AP28AN28AN31AM31AP30AP29AM30AL30AN27AM27AN29AM29AP33AN33AJ34AJ33AM34AL34AN32AM32AL33AK33AL32AK32AK31AK30AJ31AH31AH34AG34AH33AH32AG32AG31AG30AF30AL29AL28AK28AJ28AH29AH28AG29AF29AJ30AJ29AF28AE28AN34

U1 SOC_OZ_IRON_FF1156

SOC_IRON_IDI_HC1155

AP22AN25AK24AJ27AF26AC25AG23

AN22AM22AL22AN24AM24AP26AN26AP23AN23AL23AK23AP25AP24AJ23AH23AF25AE25AF23AE23AG24AF24AG26AG25AJ24AH24AL25AL24AK25AJ25AM26AM25AJ26AH26AK27AK26AH27AG27AF27AE27AC24AB24AC27AC26AE26AD26AD25AD24AD23AC23AL27

U1 SOC_OZ_IRON_FF1156

SOC_IRON_IDI_HC1155

1

IO_L11N_T1_SRCC_14

FMC2_LA10_P

IO_0_VRN_13

IO_25_VRP_13

2

1 R30110.0K1/10W

2

1

1/10W100R72

2

1

1/10W100R73

FMC2_PRSNT_M2C_LFMC2_LA02_PFMC2_LA02_NFMC2_LA03_PFMC2_LA03_N

FMC2_LA04_NFMC2_LA05_PFMC2_LA05_NFMC2_LA06_PFMC2_LA06_NFMC2_LA07_PFMC2_LA07_NFMC2_LA08_PFMC2_LA08_NFMC2_LA09_PFMC2_LA09_N

FMC2_LA10_NFMC2_LA11_PFMC2_LA11_N

FMC2_CLK0_M2C_P

FMC2_LA01_CC_PFMC2_LA01_CC_N

CLK_DIFF_1_PCLK_DIFF_1_N

FMC2_CLK1_M2C_PFMC2_CLK1_M2C_N

FMC2_LA12_PFMC2_LA12_NFMC2_LA13_PFMC2_LA13_NFMC2_LA14_PFMC2_LA14_NFMC2_LA15_PFMC2_LA15_NFMC2_LA16_PFMC2_LA16_NFMC2_HB04_PFMC2_HB04_NFMC2_HB05_PFMC2_HB05_NFMC2_HB07_PFMC2_HB07_NFMC2_HB08_PFMC2_HB08_NFMC2_HB09_PFMC2_HB09_N

IO_25_VRP_14

FMC2_LA04_P

IO_0_VRN_13FMC2_HB01_PFMC2_HB01_NFMC2_HB02_PFMC2_HB02_N

USER_SW1USER_SW2USER_SW3USER_SW4

FMC2_HB03_PFMC2_HB03_N

USER_SW5USER_SW6USER_SW7USER_SW8

FMC2_HA06_PFMC2_HA06_N

APP_LED1APP_LED2APP_LED3APP_LED4

FMC2_HB06_CC_PFMC2_HB06_CC_N

LVDS_OSC_PLVDS_OSC_N

FMC2_HB00_CC_PFMC2_HB00_CC_NFMC2_HB17_CC_PFMC2_HB17_CC_N

DUT_I2C_SCLDUT_I2C_SDAFMC2_HA07_PFMC2_HA07_N

DUT_PMB_ALERTDUT_PMB_CTRLDUT_PMB_CLK

DUT_PMB_DATAFMC2_HA08_PFMC2_HA08_NFMC2_HA09_PFMC2_HA09_NFMC2_HA10_PFMC2_HA10_N

APP_LED5APP_LED6APP_LED7APP_LED8USER_PB1USER_PB2

IO_25_VRP_13

GND

1

2

C242DNP

GND

FMC2_CLK0_M2C_N

Page 51: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

VCCO_HP

GND

VCCO_HP

VCCO_HP

GND

VCCO_HP

VCCO_15_AM18VCCO_15_AL21VCCO_15_AH20VCCO_15_AE19VCCO_15_AD22VCCO_15_AB18VCCO_15_AA22

IO_25_VRP_15_AG21IO_L24N_T3_RS0_15_AF22IO_L24P_T3_RS1_15_AE22

IO_L23N_T3_FWE_B_15_AH22IO_L23P_T3_FOE_B_15_AG22

IO_L22N_T3_A16_15_AC22IO_L22P_T3_A17_15_AB22

IO_L21N_T3_DQS_A18_15_AE21IO_L21P_T3_DQS_15_AD21IO_L20N_T3_A19_15_AC21IO_L20P_T3_A20_15_AB21

IO_L19N_T3_A21_VREF_15_AK22IO_L19P_T3_A22_15_AK21IO_L18N_T2_A23_15_AG20IO_L18P_T2_A24_15_AF20IO_L17N_T2_A25_15_AJ21IO_L17P_T2_A26_15_AH21IO_L16N_T2_A27_15_AE20IO_L16P_T2_A28_15_AD20

IO_L15N_T2_DQS_ADV_B_15_AJ19IO_L15P_T2_DQS_15_AJ18

IO_L14N_T2_SRCC_15_AL20IO_L14P_T2_SRCC_15_AL19IO_L13N_T2_MRCC_15_AK20IO_L13P_T2_MRCC_15_AJ20IO_L12N_T1_MRCC_15_AM20IO_L12P_T1_MRCC_15_AM19IO_L11N_T1_SRCC_15_AN21IO_L11P_T1_SRCC_15_AM21IO_L10N_T1_AD11N_15_AP18IO_L10P_T1_AD11P_15_AN18

IO_L9N_T1_DQS_AD3N_15_AP19IO_L9P_T1_DQS_AD3P_15_AN19

IO_L8N_T1_AD10N_15_AP21IO_L8P_T1_AD10P_15_AP20IO_L7N_T1_AD2N_15_AL18IO_L7P_T1_AD2P_15_AK18IO_L6N_T0_VREF_15_AG19

IO_L6P_T0_15_AF19IO_L5N_T0_AD9N_15_AB20IO_L5P_T0_AD9P_15_AA20

IO_L4N_T0_15_AF18IO_L4P_T0_15_AE18

IO_L3N_T0_DQS_AD1N_15_AD19IO_L3P_T0_DQS_AD1P_15_AC19

IO_L2N_T0_AD8N_15_AH19IO_L2P_T0_AD8P_15_AH18IO_L1N_T0_AD0N_15_AD18IO_L1P_T0_AD0P_15_AC18

IO_0_VRN_15_AB19

XC7VH580THCG1155BANK 15

VCCO_16_T25VCCO_16_N25VCCO_16_K24VCCO_16_J27VCCO_16_G23VCCO_16_F29VCCO_16_F26

IO_25_VRP_16_F23IO_L24N_T3_16_L29IO_L24P_T3_16_L28IO_L23N_T3_16_G29IO_L23P_T3_16_H29IO_L22N_T3_16_G27IO_L22P_T3_16_H27

IO_L21N_T3_DQS_16_H28IO_L21P_T3_DQS_16_J28

IO_L20N_T3_16_J29IO_L20P_T3_16_K28

IO_L19N_T3_VREF_16_F28IO_L19P_T3_16_F27IO_L18N_T2_16_M27IO_L18P_T2_16_N27IO_L17N_T2_16_L27IO_L17P_T2_16_M26IO_L16N_T2_16_R27IO_L16P_T2_16_R26

IO_L15N_T2_DQS_16_N26IO_L15P_T2_DQS_16_P26IO_L14N_T2_SRCC_16_L25IO_L14P_T2_SRCC_16_M25IO_L13N_T2_MRCC_16_K27IO_L13P_T2_MRCC_16_K26IO_L12N_T1_MRCC_16_H26IO_L12P_T1_MRCC_16_J26IO_L11N_T1_SRCC_16_J25IO_L11P_T1_SRCC_16_K25

IO_L10N_T1_16_G26IO_L10P_T1_16_G25

IO_L9N_T1_DQS_16_G24IO_L9P_T1_DQS_16_H24

IO_L8N_T1_16_F25IO_L8P_T1_16_F24IO_L7N_T1_16_J24IO_L7P_T1_16_H23

IO_L6N_T0_VREF_16_J23IO_L6P_T0_16_K23IO_L5N_T0_16_P25IO_L5P_T0_16_R25IO_L4N_T0_16_N23IO_L4P_T0_16_P23

IO_L3N_T0_DQS_16_N24IO_L3P_T0_DQS_16_P24

IO_L2N_T0_16_L24IO_L2P_T0_16_L23IO_L1N_T0_16_T24IO_L1P_T0_16_R23IO_0_VRN_16_M24

XC7VH580THCG1155BANK 16

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

DEDICATED PINS

DEDICATED PINS

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

I/O BANKS

THIS BANK IS NOT BONDED OUTON 290T DEVICE

7351

VC7222 V7 HCG1155 MGT CHAR

01

C12-14-2012_16:02

1

1

T25N25K24J27G23F29F26

F23L29L28G29H29G27H27H28J28J29K28F28F27M27N27L27M26R27R26N26P26L25M25K27K26H26J26J25K25G26G25G24H24F25F24J24H23J23K23P25R25N23P23N24P24L24L23T24R23M24

U1 SOC_OZ_IRON_FF1156

SOC_IRON_IDI_HC1155

AM18AL21AH20AE19AD22AB18AA22

AG21AF22AE22AH22AG22AC22AB22AE21AD21AC21AB21AK22AK21AG20AF20AJ21AH21AE20AD20AJ19AJ18AL20AL19AK20AJ20AM20AM19AN21AM21AP18AN18AP19AN19AP21AP20AL18AK18AG19AF19AB20AA20AF18AE18AD19AC19AH19AH18AD18AC18AB19

U1 SOC_OZ_IRON_FF1156

SOC_IRON_IDI_HC1155

2

1

1/10W100R86

2

1

1/10W100R91

IO_25_VRP_15

IO_0_VRN_15

IO_0_VRN_15

FMC2_HA05_NFMC2_HA05_PFMC2_HA04_N

FMC2_HA03_NFMC2_HA04_P

FMC2_HA03_PFMC2_HA02_NFMC2_HA02_P

FMC2_HA01_CC_NFMC2_HA01_CC_P

FMC2_HA00_CC_PFMC2_HA00_CC_NFMC2_LA17_CC_PFMC2_LA17_CC_N

FMC2_LA26_NFMC2_LA26_P

FMC2_LA21_NFMC2_LA21_PFMC2_LA20_NFMC2_LA20_P

FMC2_LA18_CC_PFMC2_LA18_CC_N

FMC2_LA19_PFMC2_LA19_N

FMC2_LA22_NFMC2_LA22_P

FMC2_LA23_NFMC2_LA23_P

FMC2_LA24_NFMC2_LA24_P

FMC2_LA25_NFMC2_LA25_P

FMC2_LA27_N

FMC2_LA28_NFMC2_LA28_P

FMC2_LA29_NFMC2_LA29_P

FMC2_LA30_NFMC2_LA30_P

FMC2_LA31_NFMC2_LA31_P

FMC2_LA32_NFMC2_LA32_P

FMC2_LA33_NFMC2_LA33_P

FMC2_LA27_P

FMC2_HA17_CC_NFMC2_HA17_CC_P

IO_25_VRP_15

2

1

1/10W100R85

2

1

1/10W100R79

IO_25_VRP_16

IO_0_VRN_16

IO_0_VRN_16

IO_25_VRP_16

IO_L1P_T0_16IO_L1N_T0_16IO_L2P_T0_16IO_L2N_T0_16

IO_L3P_T0_DQS_16IO_L3N_T0_DQS_16

IO_L4P_T0_16IO_L4N_T0_16IO_L5P_T0_16IO_L5N_T0_16IO_L6P_T0_16

IO_L6N_T0_VREF_16IO_L7P_T1_16IO_L7N_T1_16IO_L8P_T1_16IO_L8N_T1_16

IO_L9P_T1_DQS_16IO_L9N_T1_DQS_16

IO_L10P_T1_16IO_L10N_T1_16

IO_L11P_T1_SRCC_16IO_L11N_T1_SRCC_16IO_L12P_T1_MRCC_16IO_L12N_T1_MRCC_16IO_L13P_T2_MRCC_16IO_L13N_T2_MRCC_16IO_L14P_T2_SRCC_16IO_L14N_T2_SRCC_16IO_L15P_T2_DQS_16IO_L15N_T2_DQS_16

IO_L16P_T2_16IO_L16N_T2_16IO_L17P_T2_16IO_L17N_T2_16IO_L18P_T2_16IO_L18N_T2_16IO_L19P_T3_16

IO_L19N_T3_VREF_16IO_L20P_T3_16IO_L20N_T3_16

IO_L21P_T3_DQS_16IO_L21N_T3_DQS_16

IO_L22P_T3_16IO_L22N_T3_16IO_L23P_T3_16IO_L23N_T3_16IO_L24P_T3_16IO_L24N_T3_16

Page 52: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

VCCO_HP

GND

VCCO_HPVCCO_HP

VCCO_33_AP12VCCO_33_AM8VCCO_33_AL11VCCO_33_AH10VCCO_33_AE9VCCO_33_AD12

IO_25_VRP_33_AP11IO_L24N_T3_33_AM11IO_L24P_T3_33_AM12IO_L23N_T3_33_AP13IO_L23P_T3_33_AN13IO_L22N_T3_33_AN8IO_L22P_T3_33_AN9

IO_L21N_T3_DQS_33_AN11IO_L21P_T3_DQS_33_AN12

IO_L20N_T3_33_AL12IO_L20P_T3_33_AK12

IO_L19N_T3_VREF_33_AP9IO_L19P_T3_33_AP10IO_L18N_T2_33_AH12IO_L18P_T2_33_AG12IO_L17N_T2_33_AG9IO_L17P_T2_33_AF9

IO_L16N_T2_33_AF12IO_L16P_T2_33_AE12

IO_L15N_T2_DQS_33_AG10IO_L15P_T2_DQS_33_AF10

IO_L14N_T2_SRCC_33_AJ10IO_L14P_T2_SRCC_33_AJ11IO_L13N_T2_MRCC_33_AH11IO_L13P_T2_MRCC_33_AG11IO_L12N_T1_MRCC_33_AL9

IO_L12P_T1_MRCC_33_AL10IO_L11N_T1_SRCC_33_AK10IO_L11P_T1_SRCC_33_AK11

IO_L10N_T1_33_AM9IO_L10P_T1_33_AM10

IO_L9N_T1_DQS_33_AJ8IO_L9P_T1_DQS_33_AJ9

IO_L8N_T1_33_AL8IO_L8P_T1_33_AK8IO_L7N_T1_33_AH8IO_L7P_T1_33_AH9

IO_L6N_T0_VREF_33_AF8IO_L6P_T0_33_AE8IO_L5N_T0_33_AE10IO_L5P_T0_33_AE11IO_L4N_T0_33_AD8IO_L4P_T0_33_AC8

IO_L3N_T0_DQS_33_AD10IO_L3P_T0_DQS_33_AD11

IO_L2N_T0_33_AD9IO_L2P_T0_33_AC9IO_L1N_T0_33_AC11IO_L1P_T0_33_AC12IO_0_VRN_33_AP8

XC7VH580THCG1155BANK 33

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

VCCO_34_AP2VCCO_34_AN5VCCO_34_AL1VCCO_34_AK4VCCO_34_AJ7VCCO_34_AG3VCCO_34_AF6

IO_25_VRP_34_AP4IO_L24N_T3_34_AN6IO_L24P_T3_34_AN7IO_L23N_T3_34_AL4IO_L23P_T3_34_AL5IO_L22N_T3_34_AP5IO_L22P_T3_34_AP6

IO_L21N_T3_DQS_34_AN4IO_L21P_T3_DQS_34_AM4

IO_L20N_T3_34_AM7IO_L20P_T3_34_AL7

IO_L19N_T3_VREF_34_AM5IO_L19P_T3_34_AM6IO_L18N_T2_34_AP3IO_L18P_T2_34_AN3IO_L17N_T2_34_AK1IO_L17P_T2_34_AJ1IO_L16N_T2_34_AN1IO_L16P_T2_34_AM1

IO_L15N_T2_DQS_34_AN2IO_L15P_T2_DQS_34_AM2IO_L14N_T2_SRCC_34_AL2IO_L14P_T2_SRCC_34_AK2IO_L13N_T2_MRCC_34_AL3IO_L13P_T2_MRCC_34_AK3IO_L12N_T1_MRCC_34_AK5IO_L12P_T1_MRCC_34_AJ5IO_L11N_T1_SRCC_34_AJ3IO_L11P_T1_SRCC_34_AJ4

IO_L10N_T1_34_AH1IO_L10P_T1_34_AG1

IO_L9N_T1_DQS_34_AH2IO_L9P_T1_DQS_34_AG2

IO_L8N_T1_34_AH3IO_L8P_T1_34_AH4IO_L7N_T1_34_AG4IO_L7P_T1_34_AF4

IO_L6N_T0_VREF_34_AK6IO_L6P_T0_34_AK7IO_L5N_T0_34_AF7IO_L5P_T0_34_AE7IO_L4N_T0_34_AH7IO_L4P_T0_34_AG7

IO_L3N_T0_DQS_34_AJ6IO_L3P_T0_DQS_34_AH6

IO_L2N_T0_34_AG5IO_L2P_T0_34_AG6IO_L1N_T0_34_AF5IO_L1P_T0_34_AE6IO_0_VRN_34_AP1

XC7VH580THCG1155BANK 34

SYSTEMACE-2

SYSTEMACE-2

CLOCK MODULE

CLOCK MODULE

USB UART BRIDGE

CLOCK MODULE

USB UART BRIDGE

RECOVERY CLOCK

SPI - MGT PWR MODULE

RECOVERY CLOCK

RECOVERY CLOCK

USER DIFF SMA CLOCK

DEDICATED PINS

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

I/O BANKS

GTZ RESET

CLOCK MODULE

SYSTEMACE-2

7352

VC7222 V7 HCG1155 MGT CHAR

01

C12-14-2012_16:02

AP2AN5AL1AK4AJ7AG3AF6

AP4AN6AN7AL4AL5AP5AP6AN4AM4AM7AL7AM5AM6AP3AN3AK1AJ1AN1AM1AN2AM2AL2AK2AL3AK3AK5AJ5AJ3AJ4AH1AG1AH2AG2AH3AH4AG4AF4AK6AK7AF7AE7AH7AG7AJ6AH6AG5AG6AF5AE6AP1

U1 SOC_OZ_IRON_FF1156

SOC_IRON_IDI_HC1155

SA2_SDHOST_D1SA2_SDHOST_D0

SA2_SDHOST_CMD

IO_0_VRN_33

IO_25_VRP_34IO_L24N_T3_34

IO_L22P_T3_34IO_L22N_T3_34

FMC1_LA16_N

IO_0_VRN_33

IO_25_VRP_33

FMC1_CLK0_M2C_PFMC1_CLK0_M2C_N

FMC1_LA01_CC_NFMC1_LA01_CC_P

FMC1_LA00_CC_NFMC1_LA00_CC_P

FMC1_PRSNT_M2C_LCM_LVDS2_P

AP12AM8

AL11AH10AE9

AD12

AP11AM11AM12AP13AN13AN8AN9AN11AN12AL12AK12AP9AP10AH12AG12AG9AF9AF12AE12AG10AF10AJ10AJ11AH11AG11AL9AL10AK10AK11AM9AM10AJ8AJ9AL8AK8AH8AH9AF8AE8AE10AE11AD8AC8AD10AD11AD9AC9AC11AC12AP8

U1 SOC_OZ_IRON_FF1156

SOC_IRON_IDI_HC1155

CLK_DIFF_2_NCLK_DIFF_2_P

CM_LVDS2_N

CM_LVDS3_NCM_LVDS3_P

CM_LVDS1_NCM_LVDS1_P

CM_CTRL_20

CM_CTRL_23CM_CTRL_22CM_CTRL_21

CM_CTRL_17CM_CTRL_16CM_CTRL_15CM_CTRL_14CM_CTRL_13CM_CTRL_12CM_CTRL_11CM_CTRL_10CM_CTRL_9CM_CTRL_8CM_CTRL_7

CM_CTRL_18CM_CTRL_19

CM_CTRL_4CM_CTRL_3

CM_CTRL_6CM_CTRL_5

SA2_SDHOST_D2SA2_SDHOST_D3

USB_CTS_I_BUSB_RTS_0_BUSB_RXD_IUSB_TXD_0USB_GPIO_3

SA2_SDHOST_CLK

CM_CTRL_1

GTH_MOD_SPI_CS

CM_CTRL_2

CM_CTRL_0CM_RST

USB_GPIO_2USB_GPIO_1USB_GPIO_0

MGT_MOD_SPI_DMGT_MOD_SPI_Q

GTZ_MOD_SPI_CS

MGT_MOD_SPI_SCK

FMC1_LA04_PFMC1_LA03_NFMC1_LA03_P

FMC1_LA15_PFMC1_LA15_N

FMC1_LA02_NFMC1_LA02_P

FMC1_LA05_NFMC1_LA05_P

FMC1_LA06_NFMC1_LA06_P

FMC1_LA07_NFMC1_LA07_P

FMC1_LA08_NFMC1_LA08_P

FMC1_LA09_NFMC1_LA09_P

FMC1_LA10_NFMC1_LA10_P

FMC1_LA11_NFMC1_LA11_P

FMC1_LA12_NFMC1_LA12_P

FMC1_LA13_NFMC1_LA13_P

FMC1_LA14_NFMC1_LA14_P

FMC1_LA16_P

FMC1_LA04_N

2

1

1/10W100R101

2

1

1/10W100R100

IO_25_VRP_33

IO_L23P_T3_34IO_L23N_T3_34IO_L24P_T3_34

CM_GCLK_NCM_GCLK_P

Page 53: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

VCCO_HP VCCO_HP

VCCO_HP

GNDGND

VCCO_HP

VCCO_36_R9VCCO_36_P12VCCO_36_M8VCCO_36_L11VCCO_36_J7VCCO_36_H10VCCO_36_F6

IO_25_VRP_36_F10IO_L24N_T3_36_K7IO_L24P_T3_36_L7IO_L23N_T3_36_G6IO_L23P_T3_36_H6IO_L22N_T3_36_F7IO_L22P_T3_36_F8

IO_L21N_T3_DQS_36_G7IO_L21P_T3_DQS_36_H7

IO_L20N_T3_36_J6IO_L20P_T3_36_K6

IO_L19N_T3_VREF_36_H8IO_L19P_T3_36_J8IO_L18N_T2_36_N8IO_L18P_T2_36_P8IO_L17N_T2_36_K8IO_L17P_T2_36_L8IO_L16N_T2_36_R8IO_L16P_T2_36_T9

IO_L15N_T2_DQS_36_N9IO_L15P_T2_DQS_36_P9

IO_L14N_T2_SRCC_36_L10IO_L14P_T2_SRCC_36_M10IO_L13N_T2_MRCC_36_L9IO_L13P_T2_MRCC_36_M9IO_L12N_T1_MRCC_36_H9IO_L12P_T1_MRCC_36_J9IO_L11N_T1_SRCC_36_J10IO_L11P_T1_SRCC_36_K10

IO_L10N_T1_36_F9IO_L10P_T1_36_G9

IO_L9N_T1_DQS_36_G10IO_L9P_T1_DQS_36_G11

IO_L8N_T1_36_F12IO_L8P_T1_36_G12IO_L7N_T1_36_H11IO_L7P_T1_36_H12

IO_L6N_T0_VREF_36_J11IO_L6P_T0_36_K11IO_L5N_T0_36_P10IO_L5P_T0_36_R10IO_L4N_T0_36_M11IO_L4P_T0_36_M12

IO_L3N_T0_DQS_36_N11IO_L3P_T0_DQS_36_P11

IO_L2N_T0_36_K12IO_L2P_T0_36_L12IO_L1N_T0_36_R11IO_L1P_T0_36_R12IO_0_VRN_36_N12

XC7VH580THCG1155BANK 36

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

VCCO_35_AN15VCCO_35_AK14VCCO_35_AJ17VCCO_35_AG13VCCO_35_AF16VCCO_35_AC15

IO_25_VRP_35_AD14IO_L24N_T3_35_AF13IO_L24P_T3_35_AE13IO_L23N_T3_35_AJ13IO_L23P_T3_35_AH13IO_L22N_T3_35_AD13IO_L22P_T3_35_AC13

IO_L21N_T3_DQS_35_AG14IO_L21P_T3_DQS_35_AF14

IO_L20N_T3_35_AC14IO_L20P_T3_35_AB14

IO_L19N_T3_VREF_35_AJ14IO_L19P_T3_35_AH14IO_L18N_T2_35_AG15IO_L18P_T2_35_AF15IO_L17N_T2_35_AL13IO_L17P_T2_35_AK13IO_L16N_T2_35_AE15IO_L16P_T2_35_AD15

IO_L15N_T2_DQS_35_AK16IO_L15P_T2_DQS_35_AJ16

IO_L14N_T2_SRCC_35_AL14IO_L14P_T2_SRCC_35_AL15IO_L13N_T2_MRCC_35_AK15IO_L13P_T2_MRCC_35_AJ15IO_L12N_T1_MRCC_35_AM15IO_L12P_T1_MRCC_35_AM16IO_L11N_T1_SRCC_35_AN14IO_L11P_T1_SRCC_35_AM14IO_L10N_T1_AD15N_35_AP14IO_L10P_T1_AD15P_35_AP15

IO_L9N_T1_DQS_AD7N_35_AN17IO_L9P_T1_DQS_AD7P_35_AM17

IO_L8N_T1_AD14N_35_AP16IO_L8P_T1_AD14P_35_AN16IO_L7N_T1_AD6N_35_AL17IO_L7P_T1_AD6P_35_AK17IO_L6N_T0_VREF_35_AH16

IO_L6P_T0_35_AG16IO_L5N_T0_AD13N_35_AF17IO_L5P_T0_AD13P_35_AE17

IO_L4N_T0_35_AC16IO_L4P_T0_35_AB16

IO_L3N_T0_DQS_AD5N_35_AE16IO_L3P_T0_DQS_AD5P_35_AD16

IO_L2N_T0_AD12N_35_AH17IO_L2P_T0_AD12P_35_AG17IO_L1N_T0_AD4N_35_AC17IO_L1P_T0_AD4P_35_AB17

IO_0_VRN_35_AB15

XC7VH580THCG1155BANK 35

THIS BANK IS NOT BONDED OUTON 290T DEVICE

DEDICATED PINS

DEDICATED PINS

RN

ASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

SCHEM, ROHS COMPLIANTI/O BANKS

7353

VC7222 V7 HCG1155 MGT CHAR

01

C12-14-2012_16:02

1

AN15AK14AJ17AG13AF16AC15

AD14AF13AE13AJ13AH13AD13AC13AG14AF14AC14AB14AJ14AH14AG15AF15AL13AK13AE15AD15AK16AJ16AL14AL15AK15AJ15AM15AM16AN14AM14AP14AP15AN17AM17AP16AN16AL17AK17AH16AG16AF17AE17AC16AB16AE16AD16AH17AG17AC17AB17AB15

U1 SOC_OZ_IRON_FF1156

SOC_IRON_IDI_HC1155

IO_L24N_T3_35

R9P12M8L11J7H10F6

F10K7L7G6H6F7F8G7H7J6K6H8J8N8P8K8L8R8T9N9P9L10M10L9M9H9J9J10K10F9G9G10G11F12G12H11H12J11K11P10R10M11M12N11P11K12L12R11R12N12

U1 SOC_OZ_IRON_FF1156

SOC_IRON_IDI_HC1155

IO_0_VRN_36

IO_25_VRP_35

IO_0_VRN_35

IO_25_VRP_36

IO_0_VRN_36IO_L1P_T0_36IO_L1N_T0_36IO_L2P_T0_36IO_L2N_T0_36

IO_L3P_T0_DQS_36IO_L3N_T0_DQS_36

IO_L4P_T0_36IO_L4N_T0_36IO_L5P_T0_36IO_L5N_T0_36IO_L6P_T0_36

IO_L6N_T0_VREF_36IO_L7P_T1_36IO_L7N_T1_36IO_L8P_T1_36IO_L8N_T1_36

IO_L9P_T1_DQS_36IO_L9N_T1_DQS_36

IO_L10P_T1_36IO_L10N_T1_36

IO_L11P_T1_SRCC_36IO_L11N_T1_SRCC_36IO_L12P_T1_MRCC_36IO_L12N_T1_MRCC_36IO_L13P_T2_MRCC_36IO_L13N_T2_MRCC_36IO_L14P_T2_SRCC_36IO_L14N_T2_SRCC_36IO_L15P_T2_DQS_36IO_L15N_T2_DQS_36

IO_L16P_T2_36IO_L16N_T2_36IO_L17P_T2_36IO_L17N_T2_36IO_L18P_T2_36IO_L18N_T2_36IO_L19P_T3_36

IO_L19N_T3_VREF_36IO_L20P_T3_36IO_L20N_T3_36

IO_L21P_T3_DQS_36IO_L21N_T3_DQS_36

IO_L22P_T3_36IO_L22N_T3_36IO_L23P_T3_36IO_L23N_T3_36IO_L24P_T3_36IO_L24N_T3_36IO_25_VRP_36

2

1

1/10W100R134

2

1

1/10W100R123

2

1

1/10W100R143

2

1

1/10W100R142

IO_L24P_T3_35IO_L23N_T3_35IO_L23P_T3_35

IO_L22P_T3_35IO_L21N_T3_DQS_35IO_L21P_T3_DQS_35

IO_L20N_T3_35IO_L20P_T3_35

IO_0_VRN_35FMC1_LA19_PFMC1_LA19_NFMC1_LA20_PFMC1_LA20_NFMC1_LA21_PFMC1_LA21_NFMC1_LA22_PFMC1_LA22_NFMC1_LA23_PFMC1_LA23_NFMC1_LA24_PFMC1_LA24_NFMC1_LA25_PFMC1_LA25_NFMC1_LA26_PFMC1_LA26_NFMC1_LA27_PFMC1_LA27_NFMC1_LA28_PFMC1_LA28_N

FMC1_LA18_CC_PFMC1_LA18_CC_NFMC1_LA17_CC_PFMC1_LA17_CC_NFMC1_CLK1_M2C_PFMC1_CLK1_M2C_N

FMC1_CLK3_BIDIR_PFMC1_CLK3_BIDIR_N

FMC1_LA29_PFMC1_LA29_NFMC1_LA30_PFMC1_LA30_NFMC1_LA31_PFMC1_LA31_NFMC1_LA32_PFMC1_LA32_NFMC1_LA33_PFMC1_LA33_N

IO_25_VRP_35

IO_L22N_T3_35

1

Page 54: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

VCCBRAMVCCAUX_IO

VCCAUX_IO

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

VCCAUX

VCCAUX_IO_G1_R14VCCAUX_IO_G1_T13VCCAUX_IO_G1_V13VCCAUX_IO_G1_Y13

XC7VH580THCG1155BANK VCCAUX_IO_G1

VCCAUX_IO_G0_R20VCCAUX_IO_G0_T21VCCAUX_IO_G0_U20VCCAUX_IO_G0_W20

XC7VH580THCG1155BANK VCCAUX_IO_G0

VCCAUX_AB11VCCAUX_R22VCCAUX_U12VCCAUX_U22VCCAUX_V21VCCAUX_W12VCCAUX_Y21

VCCAUX_AA12

XC7VH580THCG1155BANK VCCAUX

VCCBRAM_P19VCCBRAM_T19VCCBRAM_V19VCCBRAM_Y17VCCBRAM_Y19

VCCBRAM_AA18

XC7VH580THCG1155BANK VCCBRAM

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

FPGA POWER

FPGA POWER, VCCAUX / VCCAUX_IO / VCCBRAM

7354

VC7222 V7 HCG1155 MGT CHAR

01

C12-14-2012_16:02

P19T19V19Y17Y19AA18

U1 SOC_OZ_IRON_FF1156

SOC_IRON_IDI_HC1155

AB11R22U12U22V21W12Y21AA12

U1 SOC_OZ_IRON_FF1156

SOC_IRON_IDI_HC1155

R20T21U20W20

U1 SOC_OZ_IRON_FF1156

SOC_IRON_IDI_HC1155

R14T13V13Y13

U1 SOC_OZ_IRON_FF1156

SOC_IRON_IDI_HC1155

Page 55: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

VCCINT

VCCINT_M13VCCINT_M15VCCINT_M17VCCINT_M19VCCINT_M21VCCINT_N14VCCINT_N16VCCINT_N18VCCINT_N20VCCINT_N22VCCINT_P13VCCINT_P15VCCINT_P17VCCINT_P21VCCINT_R16VCCINT_T11VCCINT_T15VCCINT_T23VCCINT_T27VCCINT_U8

VCCINT_U14VCCINT_U16VCCINT_U24VCCINT_U26VCCINT_V9

VCCINT_V11VCCINT_V15VCCINT_V23VCCINT_V25VCCINT_V27VCCINT_W8

VCCINT_W10VCCINT_W14VCCINT_W16VCCINT_W22VCCINT_W24VCCINT_W26VCCINT_Y9

VCCINT_Y11VCCINT_Y15VCCINT_Y23VCCINT_Y25VCCINT_Y27VCCINT_AA8

VCCINT_AA14VCCINT_AA24VCCINT_AA26VCCINT_AB9

VCCINT_AB25VCCINT_AB27

XC7VH580THCG1155BANK VCCINT

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

FPGA POWER

FPGA POWER, VCCINT

7355

VC7222 V7 HCG1155 MGT CHAR

01

C12-14-2012_16:02

VCCINT_SPY_P

M13M15M17M19M21N14N16N18N20N22P13P15P17P21R16T11T15T23T27U8U14U16U24U26V9V11V15V23V25V27W8W10W14W16W22W24W26Y9Y11Y15Y23Y25Y27AA8AA14AA24AA26AB9AB25AB27

U1 SOC_OZ_IRON_FF1156

SOC_IRON_IDI_HC1155

Page 56: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

GNDGND

GND

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

GND

GND_A3GND_A31GND_A32GND_A4

GND_AA11GND_AA13GND_AA15GND_AA16GND_AA17GND_AA19GND_AA21GND_AA23GND_AA25GND_AA28GND_AA3GND_AA31GND_AA32GND_AA4GND_AA7GND_AA9GND_AB1GND_AB10GND_AB12GND_AB23GND_AB28GND_AB29GND_AB34GND_AB6GND_AB7GND_AB8GND_AC10GND_AC20GND_AC28GND_AC3GND_AC32GND_AC7GND_AD1GND_AD17GND_AD27GND_AD28GND_AD29GND_AD30GND_AD34GND_AD5GND_AD6GND_AD7GND_AE14GND_AE24GND_AE3GND_AE30GND_AE31GND_AE32GND_AE4GND_AE5GND_AF1GND_AF11GND_AF2GND_AF21GND_AF3GND_AF31GND_AF32GND_AF33GND_AF34GND_AG18GND_AG28GND_AG8GND_AH15GND_AH25GND_AH5GND_AJ12GND_AJ2GND_AJ22GND_AJ32GND_AK19GND_AK29GND_AK9GND_AL16GND_AL26GND_AL6GND_AM13GND_AM23

GND_AM3GND_AM33GND_AN10GND_AN20GND_AN30GND_AP17GND_AP27GND_AP34GND_AP7GND_B1GND_B34GND_C3GND_C32GND_D1GND_D2GND_D33GND_D34GND_E10GND_E11GND_E12GND_E13GND_E15GND_E18GND_E19GND_E22GND_E23GND_E24GND_E25GND_E26GND_E27GND_E28GND_E29GND_E3GND_E30GND_E31GND_E32GND_E4GND_E5GND_E6GND_E7GND_E8GND_E9GND_F1GND_F11GND_F13GND_F15GND_F17GND_F19GND_F21GND_F22GND_F30GND_F34GND_F5GND_G13GND_G15GND_G18GND_G19GND_G22GND_G28GND_G3GND_G30GND_G32GND_G5GND_G8GND_H1GND_H13GND_H14GND_H15GND_H16GND_H17GND_H19GND_H2GND_H21GND_H22GND_H25GND_H30GND_H33GND_H34GND_H5GND_J12

XC7VH580THCG1155BANK GND1

GND_J13GND_J14GND_J16GND_J20GND_J22GND_J3

GND_J30GND_J31GND_J32GND_J4GND_J5GND_K1

GND_K13GND_K16GND_K17GND_K18GND_K19GND_K21GND_K22GND_K29GND_K30GND_K34GND_K5GND_K9

GND_L13GND_L15GND_L17GND_L19GND_L21GND_L22GND_L26GND_L3

GND_L30GND_L32GND_L5GND_L6GND_M1

GND_M14GND_M16GND_M18GND_M2

GND_M20GND_M22GND_M23GND_M28GND_M29GND_M30GND_M33GND_M34GND_M5GND_M6GND_M7

GND_N10GND_N13GND_N15GND_N19GND_N21GND_N28GND_N3

GND_N31GND_N32GND_N4GND_N7GND_P1

GND_P16GND_P22GND_P27GND_P28GND_P29GND_P34GND_P6GND_P7

GND_R13GND_R17GND_R18GND_R19GND_R21GND_R24GND_R28GND_R3

GND_R32

GND_R7GND_T1GND_T10GND_T12GND_T14GND_T16GND_T2GND_T20GND_T22GND_T26GND_T28GND_T29GND_T30GND_T33GND_T34GND_T5GND_T6GND_T7GND_T8GND_U11GND_U13GND_U15GND_U19GND_U21GND_U23GND_U25GND_U28GND_U3GND_U31GND_U32GND_U4GND_U7GND_U9GND_V1GND_V10GND_V12GND_V14GND_V16GND_V20GND_V22GND_V24GND_V26GND_V28GND_V30GND_V34GND_V5GND_V7GND_W11GND_W13GND_W15GND_W19GND_W21GND_W23GND_W25GND_W28GND_W3GND_W32GND_W7GND_W9GND_Y1GND_Y10GND_Y12GND_Y14GND_Y16GND_Y18GND_Y2GND_Y20GND_Y22GND_Y24GND_Y26GND_Y28GND_Y29GND_Y30GND_Y33GND_Y34GND_Y5GND_Y6GND_Y7GND_AB13

XC7VH580THCG1155BANK GND2

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

FPGA GROUND

FPGA GROUND

7356

VC7222 V7 HCG1155 MGT CHAR

01

C12-14-2012_16:04

MGTAVTT_SPY_N

MGTZVCCL_SPY_N

MGTAVCC_SPY_N

J13J14J16J20J22J3J30J31J32J4J5K1K13K16K17K18K19K21K22K29K30K34K5K9L13L15L17L19L21L22L26L3L30L32L5L6M1M14M16M18M2M20M22M23M28M29M30M33M34M5M6M7N10N13N15N19N21N28N3N31N32N4N7P1P16P22P27P28P29P34P6P7R13R17R18R19R21R24R28R3R32

R7T1

T10T12T14T16T2

T20T22T26T28T29T30T33T34T5T6T7T8

U11U13U15U19U21U23U25U28U3

U31U32U4U7U9V1

V10V12V14V16V20V22V24V26V28V30V34V5V7

W11W13W15W19W21W23W25W28W3

W32W7W9Y1

Y10Y12Y14Y16Y18Y2

Y20Y22Y24Y26Y28Y29Y30Y33Y34Y5Y6Y7

AB13

U1 SOC_OZ_IRON_FF1156

SOC_IRON_IDI_HC1155

A3A31A32A4AA11AA13AA15AA16AA17AA19AA21AA23AA25AA28AA3AA31AA32AA4AA7AA9AB1AB10AB12AB23AB28AB29AB34AB6AB7AB8AC10AC20AC28AC3AC32AC7AD1AD17AD27AD28AD29AD30AD34AD5AD6AD7AE14AE24AE3AE30AE31AE32AE4AE5AF1AF11AF2AF21AF3AF31AF32AF33AF34AG18AG28AG8AH15AH25AH5AJ12AJ2AJ22AJ32AK19AK29AK9AL16AL26AL6AM13AM23

AM3AM33AN10AN20AN30AP17AP27AP34AP7B1B34C3C32D1D2D33D34E10E11E12E13E15E18E19E22E23E24E25E26E27E28E29E3E30E31E32E4E5E6E7E8E9F1F11F13F15F17F19F21F22F30F34F5G13G15G18G19G22G28G3G30G32G5G8H1H13H14H15H16H17H19H2H21H22H25H30H33H34H5J12

U1 SOC_OZ_IRON_FF1156

SOC_IRON_IDI_HC1155

VCCINT_SPY_N

MGTZVCCH_SPY_N

Page 57: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

A

B

GND

OE

VCC

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

DP5_C2M_N

DP5_C2M_P

DP4_C2M_N

DP4_C2M_P

DP3_C2M_N

DP3_C2M_P

DP2_C2M_N

DP2_C2M_P

DP1_C2M_N

DP1_C2M_P

DP5_M2C_N

DP5_M2C_P

DP4_M2C_N

DP4_M2C_P

DP3_M2C_N

DP3_M2C_P

DP2_M2C_N

DP2_M2C_P

DP1_M2C_N

DP1_M2C_P

DP6_C2M_P

DP7_C2M_N

DP7_C2M_P

DP8_C2M_N

DP8_C2M_P

DP9_C2M_N

DP9_C2M_P

GBTCLK1_M2C_N

GBTCLK1_M2C_P

DP6_M2C_P

DP7_M2C_N

DP7_M2C_P

DP8_M2C_N

DP8_M2C_P

DP9_M2C_N

DP6_C2M_N

DP9_M2C_P

RES0

CLK_DIR

DP6_M2C_N

3P3V_4

GA1

TRST_L

TMS

3P3VAUX

TDO

TDI

TCK

LA26_N

LA26_P

LA23_N

LA17_N_CC

LA17_P_CC

LA13_N

LA13_P

LA09_N

LA09_P

LA05_N

LA05_P

LA01_N_CC

LA01_P_CC

GBTCLK0_M2C_N

GBTCLK0_M2C_P

PG_C2M

LA23_P

3P3V_2

3P3V_3

3P3V_1

12P0V_2

12P0V_1

GA0

SDA

SCL

LA27_N

LA27_P

LA18_N_CC

LA18_P_CC

LA14_N

LA14_P

LA10_N

LA10_P

LA06_N

LA06_P

DP0_M2C_N

DP0_M2C_P

DP0_C2M_N

DP0_C2M_P

RN

ASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

FMC1 DECOUPLING CAPS

SCHEM, ROHS COMPLIANTFMC1 (ROWS A, B, C, D)

FMC1 INTERFACE

FMC GLOBAL ADDRESS BIT GA[0:1]

12-14-2012_16:02 C

01

VC7222 V7 HCG1155 MGT CHAR

57 73

FMC1_PRSNT_M2C_LFMC2_TDI

FMC1_TDI

GND

VCCO_HP_EXT

1

UTIL_3V3UTIL_3V3

1

2

C1981UF25VX5R

NC

NC

NC

FMC1_LA17_CC_N

C39

C37

C35

C34

C31

C30

C27

C26

C23

C22

C19

C18

C15

C14

C11

C10

C7

C6

C3

C2

JA2 ASP_134486_01

D40

D35

D34

D33

D32

D31

D30

D29

D27

D26

D24

D21

D20

D18

D17

D15

D14

D12

D11

D9

D8

D5

D4

D1

D23

D36

D38

JA2 ASP_134486_01

B36

B33

B32

B29

B28

B25

B24

B21

B20

B16

B13

B12

B9

B8

B5

B37

B4

B40

B1

B17

JA2 ASP_134486_01

A39

A38

A35

A34

A31

A30

A27

A26

A23

A22

A19

A18

A15

A14

A11

A10

A7

A6

A3

A2

JA2 ASP_134486_01

1

2

C1961UF25VX5R

GND

VCC12_P

GND GND

VCC12_P

2

1 R18310.0K1/10W1%

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

FMC1_LA06_P

FMC1_LA06_N

FMC1_LA10_P

FMC1_LA10_N

FMC1_LA14_P

FMC1_LA14_N

FMC1_LA18_CC_P

FMC1_LA18_CC_N

FMC1_LA27_P

FMC1_LA27_N

FMC1_I2C_SCL

FMC1_I2C_SDA

FMC1_LA23_P

NC

FMC1_LA01_CC_P

FMC1_LA01_CC_N

FMC1_LA05_P

FMC1_LA05_N

FMC1_LA09_P

FMC1_LA09_N

FMC1_LA13_P

FMC1_LA13_N

FMC1_LA17_CC_P

FMC1_LA23_N

FMC1_LA26_P

FMC1_LA26_N

FMC_TCK

FMC_TMS

1

2

C5931UF25VX5R

GND

UTIL_3V3

1

1

VCCO_HP_EXT

1

2

3

4

5

U58 SC70_5

NC7SZ66

VCCO_HP_EXT

GND

Page 58: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

HA01_P_CC

HA01_N_CC

HA05_P

HA05_N

HA09_P

HA09_N

HA13_P

HA13_N

HA16_P

HA16_N

HA20_P

HA20_N

HB03_P

HB03_N

HB05_P

HB05_N

HB09_P

HB09_N

HB13_P

HB13_N

HB19_P

HB19_N

HB21_P

HB21_N

VADJ_1

VADJ_2

HB20_N

HB20_P

HB16_N

HB16_P

HB12_N

HB12_P

HB08_N

HB08_P

HB04_N

HB04_P

HB02_N

HB02_P

HA19_N

HA19_P

HA15_N

HA15_P

HA12_N

HA12_P

HA08_N

HA08_P

HA04_N

HA04_P

HA00_N_CC

PG_M2C

HA00_P_CC

VADJ_3

LA33_N

LA33_P

LA31_N

LA31_P

LA29_N

LA29_P

LA25_N

LA25_P

LA22_N

LA22_P

LA20_N

LA20_P

LA16_N

LA16_P

LA12_N

LA12_P

LA08_N

LA08_P

LA03_N

LA03_P

LA00_N_CC

LA00_P_CC

CLK1_M2C_N

CLK1_M2C_P

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

FMC1 (ROWS E, F, G)

FMC1 INTERFACE

12-14-2012_16:02 C

01

VC7222 V7 HCG1155 MGT CHAR

58 73

NC

NCNC

NC

NC

NC

NC

NC

G39

G37

G36

G34

G33

G31

G30

G28

G27

G25

G24

G22

G21

G19

G18

G16

G15

G13

G12

G10

G9

G7

G6

G3

G2

JA2 ASP_134486_01

F40

F38

F37

F35

F34

F32

F31

F29

F28

F26

F25

F23

F22

F20

F19

F17

F16

F14

F13

F11

F10

F8

F7

F5

F1

F4

JA2 ASP_134486_01

E2

E3

E6

E7

E9

E10

E12

E13

E15

E16

E18

E19

E21

E22

E24

E25

E27

E28

E30

E31

E33

E34

E36

E37

E39

JA2 ASP_134486_01

2

1 R18410.0K1/10W1%

FMC1_CLK1_M2C_N

FMC1_CLK1_M2C_P

FMC1_LA00_CC_P

FMC1_LA00_CC_N

FMC1_LA03_P

FMC1_LA03_N

FMC1_LA08_P

FMC1_LA08_N

FMC1_LA12_P

FMC1_LA12_N

FMC1_LA16_P

FMC1_LA16_N

FMC1_LA20_P

FMC1_LA20_N

FMC1_LA22_P

FMC1_LA22_N

FMC1_LA25_P

FMC1_LA25_N

FMC1_LA29_P

FMC1_LA29_N

FMC1_LA31_P

FMC1_LA31_N

FMC1_LA33_P

FMC1_LA33_N

NC

NC

VCCO_HP_EXT

VCCO_HP_EXT

VCCO_HP_EXT

VCCO_HP_EXT

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

Page 59: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

VADJ_4

LA32_N

LA32_P

LA30_N

LA30_P

LA28_N

LA28_P

LA24_N

LA24_P

LA21_N

LA21_P

LA19_N

LA19_P

LA15_N

LA15_P

LA11_N

LA11_P

LA07_N

LA07_P

LA04_N

LA04_P

LA02_N

LA02_P

CLK0_M2C_N

CLK0_M2C_P

PRSNT_M2C_L

VREF_A_M2C

VIO_B_M2C_1

HB18_N

HB18_P

HB15_N

HB15_P

HB11_N

HB11_P

HB07_N

HB07_P

HB01_N

HB01_P

HA22_N

HA22_P

HA18_N

HA18_P

HA14_N

HA14_P

HA11_N

HA11_P

HA07_N

HA07_P

HA03_N

HA03_P

CLK3_BIDIR_N

CLK3_BIDIR_P

VIO_B_M2C_2

HB17_N_CC

HB17_P_CC

HB14_N

HB14_P

HB10_N

HB10_P

HB06_N_CC

HB06_P_CC

HB00_N_CC

HB00_P_CC

HA23_N

HA23_P

HA21_N

HA21_P

HA17_N_CC

HA17_P_CC

HA10_N

HA10_P

HA06_N

HA06_P

HA02_N

HA02_P

CLK2_BIDIR_N

CLK2_BIDIR_P

VREF_B_M2C

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

FMC1 (ROWS H, J, K)

FMC1 INTERFACE

7359

VC7222 V7 HCG1155 MGT CHAR

01

C12-14-2012_16:02

FMC1_CLK2_BIDIR_N

FMC1_CLK2_BIDIR_PFMC1_CLK3_BIDIR_N

FMC1_CLK3_BIDIR_P

NC

NC

NC

NC

NC

NC

NC

FMC1_PRSNT_M2C_L

NC

NC

NC

K40

K38

K37

K35

K34

K32

K31

K29

K28

K26

K25

K23

K22

K20

K19

K17

K16

K14

K13

K11

K10

K8

K7

K5

K4

K1

JA2 ASP_134486_01

J39

J37

J36

J34

J33

J31

J30

J28

J27

J25

J24

J22

J21

J19

J18

J16

J15

J13

J12

J10

J9

J7

J6

J3

J2

JA2 ASP_134486_01H40

H38

H37

H35

H34

H32

H31

H29

H28

H26

H25

H23

H22

H20

H19

H17

H16

H14

H13

H11

H10

H8

H7

H5

H4

H2

H1

JA2 ASP_134486_01

2

1 R1324.7K1/10W5%

FMC1_CLK0_M2C_N

FMC1_CLK0_M2C_P

FMC1_LA02_P

FMC1_LA02_N

FMC1_LA04_P

FMC1_LA04_N

FMC1_LA07_P

FMC1_LA07_N

FMC1_LA11_P

FMC1_LA11_N

FMC1_LA15_P

FMC1_LA15_N

FMC1_LA19_P

FMC1_LA19_N

FMC1_LA21_P

FMC1_LA21_N

FMC1_LA24_P

FMC1_LA24_N

FMC1_LA28_P

FMC1_LA28_N

FMC1_LA30_P

FMC1_LA30_N

FMC1_LA32_P

FMC1_LA32_N

NC

NC

NC

NC

NC

NC

NC

VCCO_HP_EXT

VCCO_HP_EXT

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

Page 60: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

GND_1

GND_10

GND_100

GND_101

GND_102

GND_103

GND_104

GND_105

GND_106

GND_107

GND_108

GND_109

GND_11

GND_110

GND_111

GND_112

GND_113

GND_114

GND_115

GND_116

GND_117

GND_118

GND_119

GND_12

GND_120

GND_121

GND_122

GND_123

GND_124

GND_125

GND_126

GND_127

GND_128

GND_129

GND_13

GND_130

GND_131

GND_132

GND_133

GND_134

GND_135

GND_136

GND_137

GND_138

GND_139

GND_14

GND_140

GND_141

GND_142

GND_143

GND_144

GND_145

GND_146

GND_147

GND_148

GND_149

GND_15

GND_150

GND_151

GND_152

GND_153

GND_154

GND_155

GND_156

GND_157

GND_16

GND_17

GND_18

GND_19

GND_2

GND_20

GND_21

GND_22

GND_23

GND_24

GND_25

GND_26

GND_27

GND_28

GND_29

GND_3

GND_30

GND_31

GND_32

GND_33

GND_34

GND_35

GND_36

GND_37

GND_38

GND_39

GND_4

GND_40

GND_41

GND_42

GND_43

GND_44

GND_45

GND_46

GND_47

GND_48

GND_49

GND_5

GND_50

GND_51

GND_52

GND_53

GND_54

GND_55

GND_56

GND_57

GND_58

GND_59

GND_6

GND_60

GND_61

GND_62

GND_63

GND_64

GND_65

GND_66

GND_67

GND_68

GND_69

GND_7

GND_70

GND_71

GND_72

GND_73

GND_74

GND_75

GND_76

GND_77

GND_78

GND_79

GND_8

GND_80

GND_81

GND_82

GND_83

GND_84

GND_85

GND_86

GND_87

GND_88

GND_89

GND_9

GND_90

GND_91

GND_92

GND_93

GND_94

GND_95

GND_96

GND_97

GND_98

GND_99

GND_159

GND_158

GND_ST2

GND_ST1

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

FMC1 (GND)

FMC1 INTERFACE

12-14-2012_16:02 C

01

VC7222 V7 HCG1155 MGT CHAR

60 73

K39

K36

K33

K30

K27

K24

K21

K18

K15

K12

K9

K6

K3

K2

J40

J38

J35

J32

J29

J26

J23

J20

J17

J14

J11

J8

J5

J4

J1

H39

H36

H33

H30

H27

H24

H21

H18

H15

H12

H9

H6

H3

G40

G38

G35

G32

G29

G26

G23

G20

G17

G14

G11

G8

G5

G4

G1

F39

F36

F33

F30

F27

F24

F21

F18

F15

F12

F9

F6

F3

F2

E40

E38

E35

E32

E29

E26

E23

E20

E17

E14

E11

E8

E5

E4

E1

D25

D22

D19

D16

D13

D10

D7

D6

D3

D2

C40

C38

C36

C33

C32

C29

C28

C25

C24

C21

C20

C17

C16

C13

C12

C9

C8

C5

C4

C1

B39

B38

B35

B34

B31

B30

B27

B26

B23

B22

B19

B18

B15

B14

B11

B10

B7

B6

B3

B2

A40

A37

A36

A33

A32

A29

A28

A25

A24

A21

A20

A17

A16

A13

A12

A9

A8

A5

A4

A1

D28

D37

D39

ST2

ST1

JA2ASP_134486_01

GND

GND

2

1 C146100PF500V

GND

2

1 R2991.0M1/10W

2

1 C145100PF500V

GND

2

1 R2891.0M1/10W

Page 61: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

A

B

GND

OE

VCC

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

DP5_C2M_N

DP5_C2M_P

DP4_C2M_N

DP4_C2M_P

DP3_C2M_N

DP3_C2M_P

DP2_C2M_N

DP2_C2M_P

DP1_C2M_N

DP1_C2M_P

DP5_M2C_N

DP5_M2C_P

DP4_M2C_N

DP4_M2C_P

DP3_M2C_N

DP3_M2C_P

DP2_M2C_N

DP2_M2C_P

DP1_M2C_N

DP1_M2C_P

DP6_C2M_P

DP7_C2M_N

DP7_C2M_P

DP8_C2M_N

DP8_C2M_P

DP9_C2M_N

DP9_C2M_P

GBTCLK1_M2C_N

GBTCLK1_M2C_P

DP6_M2C_P

DP7_M2C_N

DP7_M2C_P

DP8_M2C_N

DP8_M2C_P

DP9_M2C_N

DP6_C2M_N

DP9_M2C_P

RES0

CLK_DIR

DP6_M2C_N

3P3V_4

GA1

TRST_L

TMS

3P3VAUX

TDO

TDI

TCK

LA26_N

LA26_P

LA23_N

LA17_N_CC

LA17_P_CC

LA13_N

LA13_P

LA09_N

LA09_P

LA05_N

LA05_P

LA01_N_CC

LA01_P_CC

GBTCLK0_M2C_N

GBTCLK0_M2C_P

PG_C2M

LA23_P

3P3V_2

3P3V_3

3P3V_1

12P0V_2

12P0V_1

GA0

SDA

SCL

LA27_N

LA27_P

LA18_N_CC

LA18_P_CC

LA14_N

LA14_P

LA10_N

LA10_P

LA06_N

LA06_P

DP0_M2C_N

DP0_M2C_P

DP0_C2M_N

DP0_C2M_P

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

FMC GLOBAL ADDRESS BIT GA[0:1]

FMC2 DECOUPLING CAPS

FMC2 (ROWS A, B, C, D)

FMC2 INTERFACE

12-14-2012_16:02 C

01

VC7222 V7 HCG1155 MGT CHAR

61 73

FMC2_LA26_N

FMC_TCK

FMC_TMS

FMC2_PRSNT_M2C_L

FMC2_TDI

FMC2_TDO

UTIL_3V3

UTIL_3V3

1

2

C2011UF25VX5R

UTIL_3V3

C39

C37

C35

C34

C31

C30

C27

C26

C23

C22

C19

C18

C15

C14

C11

C10

C7

C6

C3

C2

JA3 ASP_134486_01

D40

D35

D34

D33

D32

D31

D30

D29

D27

D26

D24

D21

D20

D18

D17

D15

D14

D12

D11

D9

D8

D5

D4

D1

D23

D36

D38

JA3 ASP_134486_01

B36

B33

B32

B29

B28

B25

B24

B21

B20

B16

B13

B12

B9

B8

B5

B37

B4

B40

B1

B17

JA3 ASP_134486_01

A39

A38

A35

A34

A31

A30

A27

A26

A23

A22

A19

A18

A15

A14

A11

A10

A7

A6

A3

A2

JA3 ASP_134486_01

1

2

C1991UF25VX5R

2

1 R18510.0K1/10W1%

VCC12_P

FMC2_I2C_SDA

FMC2_I2C_SCL

NC

NC

NC

NC

NC

NC

NC

FMC2_LA23_P

FMC2_LA01_CC_P

FMC2_LA01_CC_N

FMC2_LA05_P

FMC2_LA05_N

FMC2_LA09_P

FMC2_LA09_N

FMC2_LA13_P

FMC2_LA13_N

FMC2_LA17_CC_P

FMC2_LA17_CC_N

FMC2_LA23_N

FMC2_LA26_P

FMC2_LA06_P

FMC2_LA06_N

FMC2_LA10_P

FMC2_LA10_N

FMC2_LA14_P

FMC2_LA14_N

FMC2_LA18_CC_P

FMC2_LA18_CC_N

FMC2_LA27_P

FMC2_LA27_N

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

GND

VCC12_P

GND GND

GND

1

2

C5941UF25VX5R

GND

1

1

1

VCCO_HP_EXT

VCCO_HP_EXT

1

2

3

4

5

U59 SC70_5

NC7SZ66

VCCO_HP_EXT

GND

Page 62: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

HA01_P_CC

HA01_N_CC

HA05_P

HA05_N

HA09_P

HA09_N

HA13_P

HA13_N

HA16_P

HA16_N

HA20_P

HA20_N

HB03_P

HB03_N

HB05_P

HB05_N

HB09_P

HB09_N

HB13_P

HB13_N

HB19_P

HB19_N

HB21_P

HB21_N

VADJ_1

VADJ_2

HB20_N

HB20_P

HB16_N

HB16_P

HB12_N

HB12_P

HB08_N

HB08_P

HB04_N

HB04_P

HB02_N

HB02_P

HA19_N

HA19_P

HA15_N

HA15_P

HA12_N

HA12_P

HA08_N

HA08_P

HA04_N

HA04_P

HA00_N_CC

PG_M2C

HA00_P_CC

VADJ_3

LA33_N

LA33_P

LA31_N

LA31_P

LA29_N

LA29_P

LA25_N

LA25_P

LA22_N

LA22_P

LA20_N

LA20_P

LA16_N

LA16_P

LA12_N

LA12_P

LA08_N

LA08_P

LA03_N

LA03_P

LA00_N_CC

LA00_P_CC

CLK1_M2C_N

CLK1_M2C_P

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

FMC2 (ROWS E, F, G)

FMC2 INTERFACE

7362

VC7222 V7 HCG1155 MGT CHAR

01

C12-14-2012_16:02

NC

NC

NC

NC

NC

NCNC

NC

G39

G37

G36

G34

G33

G31

G30

G28

G27

G25

G24

G22

G21

G19

G18

G16

G15

G13

G12

G10

G9

G7

G6

G3

G2

JA3 ASP_134486_01

F40

F38

F37

F35

F34

F32

F31

F29

F28

F26

F25

F23

F22

F20

F19

F17

F16

F14

F13

F11

F10

F8

F7

F5

F1

F4

JA3 ASP_134486_01

E2

E3

E6

E7

E9

E10

E12

E13

E15

E16

E18

E19

E21

E22

E24

E25

E27

E28

E30

E31

E33

E34

E36

E37

E39

JA3 ASP_134486_01

2

1 R18610.0K1/10W1%

FMC2_HA00_CC_P

FMC2_HA00_CC_N

FMC2_CLK1_M2C_N

FMC2_CLK1_M2C_P

FMC2_HA08_P

FMC2_HA08_N

FMC2_HA04_P

FMC2_HA04_N

FMC2_HB09_P

FMC2_HB09_N

FMC2_HB05_P

FMC2_HB05_N

FMC2_HB03_P

FMC2_HB03_N

FMC2_HA09_P

FMC2_HA09_N

FMC2_HA05_P

FMC2_HA05_N

FMC2_HA01_CC_P

FMC2_HA01_CC_N

FMC2_LA00_CC_P

FMC2_LA00_CC_N

FMC2_LA03_P

FMC2_LA03_N

FMC2_LA08_P

FMC2_LA08_N

FMC2_LA12_P

FMC2_LA12_N

FMC2_LA16_P

FMC2_LA16_N

FMC2_LA20_P

FMC2_LA20_N

FMC2_LA22_P

FMC2_LA22_N

FMC2_LA25_P

FMC2_LA25_N

FMC2_LA29_P

FMC2_LA29_N

FMC2_LA31_P

FMC2_LA31_N

FMC2_LA33_P

FMC2_LA33_N

VCCO_HP_EXT

VCCO_HP_EXT

VCCO_HP_EXT

VCCO_HP_EXT

FMC2_HB02_N

FMC2_HB02_P

FMC2_HB04_N

FMC2_HB04_P

FMC2_HB08_N

FMC2_HB08_P

NC

NC

NC

NCNC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

Page 63: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

VADJ_4

LA32_N

LA32_P

LA30_N

LA30_P

LA28_N

LA28_P

LA24_N

LA24_P

LA21_N

LA21_P

LA19_N

LA19_P

LA15_N

LA15_P

LA11_N

LA11_P

LA07_N

LA07_P

LA04_N

LA04_P

LA02_N

LA02_P

CLK0_M2C_N

CLK0_M2C_P

PRSNT_M2C_L

VREF_A_M2C

VIO_B_M2C_1

HB18_N

HB18_P

HB15_N

HB15_P

HB11_N

HB11_P

HB07_N

HB07_P

HB01_N

HB01_P

HA22_N

HA22_P

HA18_N

HA18_P

HA14_N

HA14_P

HA11_N

HA11_P

HA07_N

HA07_P

HA03_N

HA03_P

CLK3_BIDIR_N

CLK3_BIDIR_P

VIO_B_M2C_2

HB17_N_CC

HB17_P_CC

HB14_N

HB14_P

HB10_N

HB10_P

HB06_N_CC

HB06_P_CC

HB00_N_CC

HB00_P_CC

HA23_N

HA23_P

HA21_N

HA21_P

HA17_N_CC

HA17_P_CC

HA10_N

HA10_P

HA06_N

HA06_P

HA02_N

HA02_P

CLK2_BIDIR_N

CLK2_BIDIR_P

VREF_B_M2C

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

FMC2 (ROWS H, J, K)

FMC2 INTERFACE

12-14-2012_16:02 C

01

VC7222 V7 HCG1155 MGT CHAR

63 73

NC

NC

NC

NC

NC FMC2_HA17_CC_N

FMC2_HA17_CC_P

NC

NC

NC

NC

NC

NC

NC

FMC2_HB17_CC_P

FMC2_HB17_CC_N

FMC2_PRSNT_M2C_L

K40

K38

K37

K35

K34

K32

K31

K29

K28

K26

K25

K23

K22

K20

K19

K17

K16

K14

K13

K11

K10

K8

K7

K5

K4

K1

JA3 ASP_134486_01

J39

J37

J36

J34

J33

J31

J30

J28

J27

J25

J24

J22

J21

J19

J18

J16

J15

J13

J12

J10

J9

J7

J6

J3

J2

JA3 ASP_134486_01H40

H38

H37

H35

H34

H32

H31

H29

H28

H26

H25

H23

H22

H20

H19

H17

H16

H14

H13

H11

H10

H8

H7

H5

H4

H2

H1

JA3 ASP_134486_01

2

1 R1334.7K1/10W5%

FMC2_CLK0_M2C_N

FMC2_CLK0_M2C_P

FMC2_HB07_P

FMC2_HB07_N

FMC2_HB01_P

FMC2_HB01_N

FMC2_HB06_CC_P

FMC2_HB06_CC_N

FMC2_HB00_CC_P

FMC2_HB00_CC_N

FMC2_HA10_P

FMC2_HA10_N

FMC2_HA06_P

FMC2_HA06_N

FMC2_HA02_P

FMC2_HA02_NFMC2_LA02_P

FMC2_LA02_N

FMC2_LA04_P

FMC2_LA04_N

FMC2_LA07_P

FMC2_LA07_N

FMC2_LA11_P

FMC2_LA11_N

FMC2_LA15_P

FMC2_LA15_N

FMC2_LA19_P

FMC2_LA19_N

FMC2_LA21_P

FMC2_LA21_N

FMC2_LA24_P

FMC2_LA24_N

FMC2_LA28_P

FMC2_LA28_N

FMC2_LA30_P

FMC2_LA30_N

FMC2_LA32_P

FMC2_LA32_N

NC

NC

VCCO_HP_EXT

VCCO_HP_EXT

FMC2_HA03_N

FMC2_HA03_P

FMC2_HA07_N

FMC2_HA07_P

NC

NCNC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

Page 64: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

GND_1

GND_10

GND_100

GND_101

GND_102

GND_103

GND_104

GND_105

GND_106

GND_107

GND_108

GND_109

GND_11

GND_110

GND_111

GND_112

GND_113

GND_114

GND_115

GND_116

GND_117

GND_118

GND_119

GND_12

GND_120

GND_121

GND_122

GND_123

GND_124

GND_125

GND_126

GND_127

GND_128

GND_129

GND_13

GND_130

GND_131

GND_132

GND_133

GND_134

GND_135

GND_136

GND_137

GND_138

GND_139

GND_14

GND_140

GND_141

GND_142

GND_143

GND_144

GND_145

GND_146

GND_147

GND_148

GND_149

GND_15

GND_150

GND_151

GND_152

GND_153

GND_154

GND_155

GND_156

GND_157

GND_16

GND_17

GND_18

GND_19

GND_2

GND_20

GND_21

GND_22

GND_23

GND_24

GND_25

GND_26

GND_27

GND_28

GND_29

GND_3

GND_30

GND_31

GND_32

GND_33

GND_34

GND_35

GND_36

GND_37

GND_38

GND_39

GND_4

GND_40

GND_41

GND_42

GND_43

GND_44

GND_45

GND_46

GND_47

GND_48

GND_49

GND_5

GND_50

GND_51

GND_52

GND_53

GND_54

GND_55

GND_56

GND_57

GND_58

GND_59

GND_6

GND_60

GND_61

GND_62

GND_63

GND_64

GND_65

GND_66

GND_67

GND_68

GND_69

GND_7

GND_70

GND_71

GND_72

GND_73

GND_74

GND_75

GND_76

GND_77

GND_78

GND_79

GND_8

GND_80

GND_81

GND_82

GND_83

GND_84

GND_85

GND_86

GND_87

GND_88

GND_89

GND_9

GND_90

GND_91

GND_92

GND_93

GND_94

GND_95

GND_96

GND_97

GND_98

GND_99

GND_159

GND_158

GND_ST2

GND_ST1

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

FMC2 (GND)

FMC2 INTERFACE

12-14-2012_16:02 C

01

VC7222 V7 HCG1155 MGT CHAR

64 73

2

1 C147100PF500V

GND

GND

K39

K36

K33

K30

K27

K24

K21

K18

K15

K12

K9

K6

K3

K2

J40

J38

J35

J32

J29

J26

J23

J20

J17

J14

J11

J8

J5

J4

J1

H39

H36

H33

H30

H27

H24

H21

H18

H15

H12

H9

H6

H3

G40

G38

G35

G32

G29

G26

G23

G20

G17

G14

G11

G8

G5

G4

G1

F39

F36

F33

F30

F27

F24

F21

F18

F15

F12

F9

F6

F3

F2

E40

E38

E35

E32

E29

E26

E23

E20

E17

E14

E11

E8

E5

E4

E1

D25

D22

D19

D16

D13

D10

D7

D6

D3

D2

C40

C38

C36

C33

C32

C29

C28

C25

C24

C21

C20

C17

C16

C13

C12

C9

C8

C5

C4

C1

B39

B38

B35

B34

B31

B30

B27

B26

B23

B22

B19

B18

B15

B14

B11

B10

B7

B6

B3

B2

A40

A37

A36

A33

A32

A29

A28

A25

A24

A21

A20

A17

A16

A13

A12

A9

A8

A5

A4

A1

D28

D37

D39

ST2

ST1

JA3ASP_134486_01

GND

2

1 R3021.0M1/10W

2

1 C148100PF500V

GND

2

1 R3041.0M1/10W

Page 65: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

P

P

P

P

P

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

DUTIFACE_01

DUTIFACE_02

DUTIFACE_03

DUTIFACE_12

DUTIFACE_13

DUTIFACE_VREF_14

DUT_DCDETECT_B

DUT_MBDETECT_3V3

DUT_MBDETECT_3V3_B

DUT_MBDETECT_5V0

DUT_MBDETECT_5V0_B

DUT_PWRDN_3V3

DUT_PWRDN_3V3_B

DUT_PWRDN_5V0

DUT_PWRDN_5V0_B

VCC12_P_AFX

VCC3V3_AFX

VCC5_AFX

VCC5_AFX

VCC3V3_AFX

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

SB_VREF

SB_VREF

GND

GND

GND

GND

GND

GND

GND

AFX_PMB_ALERT

AFX_PMB_CLK

AFX_PMB_CTRL

AFX_PMB_DATA

AFX_PMB_REF

DUTIFACE_04

DUTIFACE_05

DUTIFACE_06

DUTIFACE_07

DUTIFACE_08

DUTIFACE_09

DUTIFACE_10

DUTIFACE_11

I2C_CLAMP_DUT_SCL

I2C_CLAMP_DUT_SDA

I2C_CLAMP_DUT_WP

TCK

TDI

TDO

TMS

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

SB_VREF

SB_VREF

GND

DUTIFACE_15

DUTIFACE_16

DUTIFACE_17

DUTIFACE_18

DUTIFACE_19

DUTIFACE_20

DUTIFACE_21

DUTIFACE_22

DUTIFACE_23

DUTIFACE_24

DUTIFACE_25

DUTIFACE_26

DUTIFACE_27

DUTIFACE_28

DUTIFACE_29

DUTIFACE_30

DUTIFACE_31

DUTIFACE_32

HS_CLK_Q2

HS_CLK_Q2_N

P

P

P

P

P

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

AFX CONTROL SIGNALS

AFX SIDEBAND CONNECTOR

7365

VC7222 V7 HCG1155 MGT CHAR

01

C12-14-2012_16:02

AFX_TDI_0

AFX_TCK_0

AFX_TDO_0

VCCO_0

DUT_MBDETECT_3V3

1 TP9

POR_B2

1 TP7

1 TP5

1 TP8

DUT_MBDETECT_3V3_B

DUT_PWRDN_3V3_B

1 TP1

GND

GND

E1

E2

E3

E4

E5

E6

E7

E8

E9

E10

E11

E12

E13

E14

E15

E16

E17

E18

E19

E20

JA1SEAF_20_065_S_05_2_A

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

JA1SEAF_20_065_S_05_2_A

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

JA1SEAF_20_065_S_05_2_A

B1

B2

B3

B4

B5

B6

B7

B8

B9

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

JA1SEAF_20_065_S_05_2_A

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

JA1SEAF_20_065_S_05_2_A

PROGRAM_B_0

AFX_UCD9248_RST

NC

1

2

C6011UF25VX5R

NC

NC

VP_ADC_AFX

VN_ADC_AFX

NC

NC

I2C_SCL

I2C_SDA

I2C_WP

CCLK_0

INIT_B_0

DONE_0

M2_0

M1_0

M0_0

NC

NC

NC

NC

AFX_TMS_0

AFX_PMB_REF

AFX_PMB_CLK

AFX_PMB_DATA

AFX_PMB_CTRL

AFX_PMB_ALERT

GND

VCC5_AFX

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

GND

NC

1 TP3

1 TP2

1 TP4

1 TP6

1 TP14

VCCO_0

VCCO_0

Page 66: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

RN

ASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

SELECT I/O TERMINATIONSCHEM, ROHS COMPLIANT

SELECT I/O TERMINATION

12-14-2012_16:02 C

01

VC7222 V7 HCG1155 MGT CHAR

66 73

IO_L18N_T2_36

IO_L18P_T2_36

IO_L17N_T2_36

IO_L17P_T2_36

IO_L16N_T2_36

IO_L16P_T2_36

IO_L15N_T2_DQS_36

IO_L15P_T2_DQS_36

IO_L14N_T2_SRCC_36

IO_L14P_T2_SRCC_36

IO_L13N_T2_MRCC_36

IO_L13P_T2_MRCC_36

IO_L12N_T1_MRCC_36

IO_L12P_T1_MRCC_36

IO_L11N_T1_SRCC_36

IO_L11P_T1_SRCC_36

IO_L10N_T1_36

IO_L10P_T1_36

IO_L9N_T1_DQS_36

IO_L9P_T1_DQS_36

IO_L8N_T1_36

IO_L8P_T1_36

IO_L7N_T1_36

IO_L7P_T1_36

IO_L6N_T0_VREF_36

IO_L6P_T0_36

IO_L5N_T0_36

IO_L5P_T0_36

IO_L4N_T0_36

IO_L4P_T0_36

IO_L3N_T0_DQS_36

IO_L3P_T0_DQS_36

IO_L2N_T0_36

IO_L2P_T0_36

IO_L1N_T0_36

IO_L1P_T0_36

IO_25_VRP_14

GND

2

1 R7871001/10W

VTT_HP

GND

VTT_HP

GND

GND

VTT_HP

GND

VTT_HP

GND GND

VTT_HP VTT_HP

GND

VTT_HP

GND GND

VTT_HP VTT_HP

GND

VTT_HP

GND GND

VTT_HP VTT_HP

GND

VTT_HP

GND GND

VTT_HP VTT_HP

GND

VTT_HP

GND GND

VTT_HP VTT_HP

GND

VTT_HP

GND GND

VTT_HP VTT_HP

GND

VTT_HP

GND

VTT_HP

GND

VTT_HP

GND

VTT_HP

GND

VTT_HP

GND

VTT_HP

GND

VTT_HP

GND

VTT_HP

GND

VTT_HP

GND

VTT_HP

GND GND

VTT_HP VTT_HP

GND

VTT_HP

GND

VTT_HP VTT_HP

GND

VTT_HP

2

1 R7921001/10W2

1 R7941001/10W

2

1 R7931001/10W 2

1 R7911001/10W

2

1 R7901001/10W

2

1 R7891001/10W

2

1 R7881001/10W 2

1 R7861001/10W

2

1 R7851001/10W

2

1 R7841001/10W

2

1 R7831001/10W

2

1 R8521001/10W

2

1 R8511001/10W

2

1 R8441001/10W

2

1 R8431001/10W

2

1 R8261001/10W

2

1 R8251001/10W

2

1 R8241001/10W

2

1 R8231001/10W

2

1 R8221001/10W

2

1 R8211001/10W

2

1 R8021001/10W

2

1 R8011001/10W

2

1 R8001001/10W

2

1 R7991001/10W

2

1 R7961001/10W

2

1 R7951001/10W

2

1 R8541001/10W

2

1 R8531001/10W

2

1 R8461001/10W

2

1 R8451001/10W

2

1 R8321001/10W

2

1 R8311001/10W

2

1 R8301001/10W

2

1 R8291001/10W

2

1 R8281001/10W

2

1 R8271001/10W

2

1 R8081001/10W

2

1 R8071001/10W

2

1 R8061001/10W

2

1 R8051001/10W

2

1 R8041001/10W

2

1 R8031001/10W

2

1 R8561001/10W

2

1 R8551001/10W

2

1 R8481001/10W

2

1 R8471001/10W

2

1 R8361001/10W

2

1 R8351001/10W

2

1 R8341001/10W

2

1 R8331001/10W

2

1 R8141001/10W

2

1 R8131001/10W

2

1 R8121001/10W

2

1 R8111001/10W

2

1 R8101001/10W

2

1 R8091001/10W

2

1 R7981001/10W

2

1 R7971001/10W

2

1 R8581001/10W

2

1 R8571001/10W

2

1 R8501001/10W

2

1 R8491001/10W

2

1 R8401001/10W

2

1 R8391001/10W

2

1 R8381001/10W

2

1 R8371001/10W

2

1 R8201001/10W

2

1 R8191001/10W

2

1 R8181001/10W

2

1 R8171001/10W

2

1 R8161001/10W

2

1 R8151001/10W

GND

VTT_HP

2

1 R4771001/10W

2

1 R4761001/10W

IO_L23N_T3_35

Page 67: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

SELECT I/O TERMINATION

RN

SELECT I/O TERMINATION

12-14-2012_16:02 C

01

VC7222 V7 HCG1155 MGT CHAR

67 73

VTT_HP VTT_HP

GND GND

VTT_HP

GND

GND

VTT_HP

GND

VTT_HP

GND GND

VTT_HP VTT_HP

GND GND

VTT_HP VTT_HP

GND

VTT_HP

GND GND

VTT_HP VTT_HP

2

1 R8701001/10W

2

1 R8691001/10W

2

1 R8681001/10W

2

1 R8671001/10W

2

1 R9021001/10W

2

1 R9011001/10W

2

1 R9001001/10W

2

1 R8991001/10W

2

1 R9081001/10W

2

1 R9071001/10W

2

1 R9061001/10W

2

1 R9051001/10W

2

1 R9121001/10W

2

1 R9111001/10W

2

1 R9101001/10W

2

1 R9091001/10W

2

1 R8741001/10W

2

1 R8731001/10W

2

1 R9181001/10W

2

1 R9171001/10W

2

1 R9161001/10W

2

1 R9151001/10W

2

1 R9141001/10W

2

1 R9131001/10W

IO_L19P_T3_36

IO_L19N_T3_VREF_36

IO_L20P_T3_36

IO_L20N_T3_36

IO_L21P_T3_DQS_36

IO_L21N_T3_DQS_36

IO_L22P_T3_36

IO_L22N_T3_36

IO_L23P_T3_36

IO_L23N_T3_36

IO_L24P_T3_36

IO_L24N_T3_36

GND

VTT_HP

GND

VTT_HP

GND

VTT_HP

2

1 R4021001/10W

2

1 R4011001/10W

2

1 R3811001/10W

2

1 R3801001/10W

2

1 R3621001/10W

2

1 R3601001/10W

IO_L19N_T3_VREF_16

IO_L19P_T3_16

IO_L18N_T2_16

VTT_HP VTT_HP

GND GND

VTT_HP

GND

GND

VTT_HP

GND

VTT_HP

GND GND

VTT_HP VTT_HP

GND

VTT_HP

GND GND

VTT_HP VTT_HP

GND

VTT_HP

GND

VTT_HP

GND GND

VTT_HP VTT_HP

GND

VTT_HP

2

1 R4241001/10W2

1 R4231001/10W

2

1 R4221001/10W 2

1 R4211001/10W

2

1 R4201001/10W

2

1 R4181001/10W

2

1 R4001001/10W

2

1 R3991001/10W

2

1 R3981001/10W

2

1 R3971001/10W

2

1 R3961001/10W

2

1 R3951001/10W

2

1 R3791001/10W

2

1 R3781001/10W

2

1 R3771001/10W

2

1 R3761001/10W

2

1 R3751001/10W

2

1 R3741001/10W

2

1 R3591001/10W

2

1 R3581001/10W

2

1 R3571001/10W

2

1 R3561001/10W

2

1 R3481001/10W

2

1 R3471001/10W

2

1 R3421001/10W

2

1 R3391001/10W

2

1 R3381001/10W

2

1 R3371001/10W

2

1 R3361001/10W

2

1 R3351001/10W

IO_L8P_T1_16

IO_L7N_T1_16

IO_L7P_T1_16

IO_L6N_T0_VREF_16

IO_L6P_T0_16

IO_L5N_T0_16

IO_L5P_T0_16

IO_L4N_T0_16

IO_L4P_T0_16

IO_L3N_T0_DQS_16

IO_L3P_T0_DQS_16

IO_L2N_T0_16

IO_L2P_T0_16

IO_L1N_T0_16

IO_L1P_T0_16

GND

VTT_HP

GND

VTT_HP

GND

VTT_HP

GND

VTT_HP

2

1 R3941001/10W

2

1 R3931001/10W

2

1 R3731001/10W

2

1 R3721001/10W

2

1 R3551001/10W

2

1 R3541001/10W

2

1 R3341001/10W

2

1 R3331001/10W

IO_L10P_T1_16

IO_L9N_T1_DQS_16

IO_L9P_T1_DQS_16

IO_L8N_T1_16

GND

2

1 R4251001/10W

VTT_HP

2

1 R4171001/10W

IO_L10N_T1_16

GND

VTT_HP

GND

VTT_HP

GND

VTT_HP

2

1 R3711001/10W

2

1 R3701001/10W

2

1 R3531001/10W

2

1 R3511001/10W

2

1 R3321001/10W

2

1 R3311001/10W

IO_L12P_T1_MRCC_16

IO_L11N_T1_SRCC_16

IO_L11P_T1_SRCC_16

Page 68: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

SELECT I/O TERMINATION

ASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

RN

SELECT I/O TERMINATIONSCHEM, ROHS COMPLIANT

12-14-2012_16:02 C

01

VC7222 V7 HCG1155 MGT CHAR

68 73

IO_L18P_T2_16

IO_L17N_T2_16

IO_L17P_T2_16

IO_L16N_T2_16

IO_L16P_T2_16

IO_L15N_T2_DQS_16

IO_L15P_T2_DQS_16

IO_L14N_T2_SRCC_16

IO_L14P_T2_SRCC_16

IO_L13N_T2_MRCC_16

IO_L13P_T2_MRCC_16

IO_L12N_T1_MRCC_16

GND

VTT_HP

GND

VTT_HP

GND

VTT_HP

GND

VTT_HP

GND

VTT_HP

GND

VTT_HP

GND

VTT_HP

GND

VTT_HP

GND

VTT_HP

GND

VTT_HP

GND

VTT_HP

GND

VTT_HP

2

1 R4161001/10W

2

1 R4151001/10W

2

1 R4141001/10W

2

1 R4131001/10W

2

1 R4121001/10W

2

1 R4111001/10W

2

1 R3921001/10W

2

1 R3911001/10W

2

1 R3901001/10W

2

1 R3841001/10W

2

1 R3831001/10W

2

1 R3821001/10W

2

1 R3691001/10W

2

1 R3681001/10W

2

1 R3661001/10W

2

1 R3631001/10W

2

1 R3501001/10W

2

1 R3491001/10W

2

1 R3461001/10W

2

1 R3451001/10W

2

1 R3441001/10W

2

1 R3431001/10W

2

1 R3301001/10W

2

1 R3291001/10W

GND

VTT_HP

GND

VTT_HP

2

1 R4451001/10W

2

1 R4441001/10W

2

1 R4271001/10W

2

1 R4261001/10W

IO_L24N_T3_35

IO_L22P_T3_34

GND

VTT_HP

2

1 R4931001/10W

2

1 R4921001/10W

IO_L24P_T3_35

VTT_HP VTT_HP

GND GND

VTT_HP

GND

GND

VTT_HP

GND

VTT_HP

GND GND

VTT_HP VTT_HP

GND

VTT_HP

GND GND

VTT_HP VTT_HP

GND

VTT_HP

GND

VTT_HP

GND GND

VTT_HP VTT_HP

GND

VTT_HP

2

1 R5001001/10W2

1 R4991001/10W

2

1 R4981001/10W 2

1 R4971001/10W

2

1 R4961001/10W

2

1 R4951001/10W

2

1 R4851001/10W

2

1 R4841001/10W

2

1 R4831001/10W

2

1 R4821001/10W

2

1 R4811001/10W

2

1 R4801001/10W

2

1 R4691001/10W

2

1 R4681001/10W

2

1 R4671001/10W

2

1 R4661001/10W

2

1 R4651001/10W

2

1 R4641001/10W

2

1 R4531001/10W

2

1 R4521001/10W

2

1 R4511001/10W

2

1 R4501001/10W

2

1 R4431001/10W

2

1 R4421001/10W

2

1 R4371001/10W

2

1 R4361001/10W

2

1 R4351001/10W

2

1 R4341001/10W

2

1 R4331001/10W

2

1 R4321001/10W

IO_L24N_T3_34

IO_L24P_T3_34

IO_L23N_T3_34

IO_L23P_T3_34

IO_L22N_T3_34

IO_L24N_T3_16

IO_L24P_T3_16

IO_L23N_T3_16

IO_L23P_T3_16

IO_L22N_T3_16

IO_L22P_T3_16

IO_L21N_T3_DQS_16

IO_L21P_T3_DQS_16

IO_L20N_T3_16

IO_L20P_T3_16

Page 69: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

SELECT I/O TERMINATION

ASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

RN

SELECT I/O TERMINATIONSCHEM, ROHS COMPLIANT

7369

VC7222 V7 HCG1155 MGT CHAR

01

C12-14-2012_16:02

IO_L23P_T3_35

IO_L22N_T3_35

IO_L22P_T3_35

IO_L21N_T3_DQS_35

IO_L21P_T3_DQS_35

IO_L20N_T3_35

IO_L20P_T3_35

IO_25_VRP_34

GND

2

1 R5011001/10W

GND GND

VTT_HP VTT_HP

GND GND

VTT_HP VTT_HP

GND GND

VTT_HP VTT_HP

GND

VTT_HP

VTT_HP

2

1 R4941001/10W

2

1 R4791001/10W

2

1 R4781001/10W

2

1 R4631001/10W

2

1 R4621001/10W

2

1 R4611001/10W

2

1 R4601001/10W

2

1 R4491001/10W

2

1 R4481001/10W

2

1 R4471001/10W

2

1 R4461001/10W

2

1 R4311001/10W

2

1 R4301001/10W

2

1 R4291001/10W

2

1 R4281001/10W

Page 70: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn ByPLACE ONE 100UF CAP FOR EVERY 25 TERMINATED I/O SIGNAL.DISTRIBUTE THE CAPS EVENLY WITH RESPECT TO THE TERMINATIONRESISTORS. RN

ASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

SCHEM, ROHS COMPLIANTSELECT I/O TERMINATION

SELECT I/O TERMINATION - DECOUPLING CAPS

PLACE ONE 1UF CAP FOR EVERY 4 TERMINATED I/O SIGNAL.

12-14-2012_16:02 C

01

VC7222 V7 HCG1155 MGT CHAR

70 73

1

2

C969100UF6.3V

1

2

C968100UF6.3V

1

2

C11541UF16V

1

2

C11531UF16V

1

2

C11521UF16V

1

GND

VTT_HP

1

2

C11511UF16V

1

2

C11501UF16V

1

2

C11491UF16V

1

2

C11481UF16V

1

2

C11471UF16V

1

2

C11461UF16V

1

2

C11451UF16V

1

2

C11441UF16V

1

2

C11431UF16V

1

2

C11421UF16V

GND

VTT_HP

1

1

2

C2171UF16V

1

2

C2161UF16V

1

2

C2311UF16V

1

2

C2301UF16V

1

2

C2291UF16V

GND

VTT_HP

1

2

C2281UF16V

1

2

C2271UF16V

1

2

C2261UF16V

1

2

C2251UF16V

1

2

C2241UF16V

1

2

C2231UF16V

1

2

C2221UF16V

1

2

C2211UF16V

1

2

C2201UF16V

1

2

C2191UF16V

1

2

C2181UF16V

1

2

C213100UF6.3V

1

2

C214100UF6.3V

1

2

C215100UF6.3V

Page 71: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

VTT_HP SENSE

EXT VTT_HP JACK

VTT_HP SOURCE, PROBE POINTS

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

GROUND TURRETSFIDUCIAL HOLES

EXT VTT JACK, BOARD MECHANICALS

SUPERCLOCK-2

BOARD STANDOFFS

MOUNTING HOLES

EXT VTT JACKS / MOUNTING HOLES / FIDUCIALS / GND TURRETS

ENDS OF VTT PLANE.PLACE EXT VTT JACK AND VTT SENSE HEADER AT THE OPPOSITE

7371

VC7222 V7 HCG1155 MGT CHAR

01

C12-14-2012_16:02

1

1

MH261

MH251

MH27

1MH24MH_125_250

GND

1

M2

1

M1

1

E1

10-109-3-01

1MH21MH_125_250

1

E3

10-109-3-01

1MH18MH_125_250

1

E2

10-109-3-01

1MH22MH_125_250

1MH23MH_125_250

1MH20MH_125_250

1MH19MH_125_250

1MH17MH_125_250

1MH16MH_125_250

GNDGNDGND

GND

1

M3

1

M4

1

M5

1

M6

NC

NC

NC NC NC

NC

NC NC

NC

VTT_HP

1

1

GND

GND

GND

J197

1

2

J192

1

2

3

J195J198

VCCO_HP_EXT

VTT_HP

Page 72: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

GND

GND

GND

VCCINT

GND GND

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

JANUARY 30, 2012: RECOMMENDED FPGA DECOUPLING NETWORKFOR 7VH580T-HCG1155

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

VCCAUX

VCCBRAM

FPGA DECOUPLING

VCCINT

FPGA DECOUPLING

VCCAUX_IO (2 GROUPS)

12-14-2012_16:02 C

01

VC7222 V7 HCG1155 MGT CHAR

72 731

1

2

C11744.7UF10VX5R

1

2

C518680UF6.3VTANT

1

2

C51447UF6.3VTANT

VCCBRAM

1

2

C519680UF6.3VTANT

1

2

C517680UF6.3VTANT

1

2

C516100UF6.3VX5R

1

VCCAUX VCCAUX_IO

1

2 TANT10V330UFC814

1

2

C880100UF6.3VX5R

1

2

C520330UF10VTANT

1

2

C11664.7UF10VX5R

1

2

C11654.7UF10VX5R

1

2

C11644.7UF10VX5R

1

2

C11634.7UF10VX5R

1

2

C11624.7UF10VX5R

1

2

C11614.7UF10VX5R

1

2

C11604.7UF10VX5R

VCCBRAM

1

2

C11734.7UF10VX5R

2

1 C9314.7UF10VX5R

2

1 C9324.7UF10VX5R

Page 73: Xilinx XTP304 – VC7222 Schematics (Rev. C) · util_3v3 fmc2_hb05_p 2 1 4 3 6 5 8 7 10 9 12 11 14 13 j3 n3314-6603rb fmc1_la00_cc_p 2 1 r311 10.0k 1/10w mac_jtag_enable_b 2 1 r319

VCCO_HP

GND

GND

GND

VCCO_HP

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

VCCO_0 (BANK 0)

RN

SCHEM, ROHS COMPLIANTASSY P/N: 0431710PCB P/N: 1280636SCH P/N: 0381469TEST P/N: TSS0XXX

FPGA DECOUPLING

FPGA DECOUPLING

VCCO (8 BANKS)

JANUARY 30, 2012: RECOMMENDED FPGA DECOUPLING NETWORKFOR 7VH580T-HCG1155

12-14-2012_16:02 C

01

VC7222 V7 HCG1155 MGT CHAR

73 731

1

1

2

C581100UF6.3VX5R

1

2

C585100UF6.3VX5R

1

2

C584100UF6.3VX5R

1

2

C580100UF6.3VX5R

1

2

C579100UF6.3VX5R

1

2

C586100UF6.3VX5R

1

2

C583100UF6.3VX5R

1

2

C582100UF6.3VX5R

1

2

C57347UF6.3VTANT

VCCO_0