xilinx ise 9.1/9 - indian institute of technology...
TRANSCRIPT
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XILINX ISE 9.1/9.2By courtesy of Xilinx
EEP201: Digital ElectronicsIndian Institute of Technology, Delhi
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FPGA Environment
How to start an FPGA project? How to describe logic circuit using schematic? How to simulate and check for errors?
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simulation
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Source Pane
Editor Pane
Process Pane
Transcript Pane
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CONTINUE…….
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SELECT SCHEMATIC
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USEFUL SYMBOLS
ADD WIRE
I/O MARKER
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HALF ADDER SCHEMATIC
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HALF ADDER SCHEMATIC
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ATTRIBUTE THE IO MARKER
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HALF ADDER SCHEMATIC
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CHECK SCHEMATIC
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FIND TOOL OPTION FROM MAIN MENU
Tools > Symbol Wizard
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CREATING A MACRO
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PIN POSITION
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CONTINUE WITH MACRO
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MACRO LOOKS LIKE THIS
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HERE WE ARE CREATING A NEW SCHEMATIC
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4 BIT RIPPLE ADDER
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DEFINING THE SIGNALS: TB
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DEFINE INPUT TEST PATTERN
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SAVE TEST BENCH
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PRESS THE PROCESS TAB
DOUBLE CLICK SIMULATE BEHAVIOUR MODEL
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SIMULATION RESULTS
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References :
http://ecewww.colorado.edu/~ecen3100/lab/9.1_tutorial_3/xilinx_9.1_tutorial_3.htm http://ecewww.colorado.edu/~ecen3100/lab/9.1_tutorial_3/xilinx_9.1_tutorial_3.htm#demo