www.hypertransport.org 1 extreme interconnect performance extended applicability may 16, 2006...

www.hypertransport.org 1

Extreme Interconnect Performance

Extended Applicability May 16, 2006

Introducing HyperTransportTM 3.0

David RichPresident

HyperTransport Consortium

Brian HoldenVice President

Chair Technical Working Group HyperTransport Consortium

Mario CavalliGeneral Manager


www.hypertransport.org 2TechOnLine Webcast May 16, 2006

… … … … … …

HyperTransport ConsortiumOwns and Licenses HyperTransport Technology

Founding Members

Founded: 2001

Mission: The standardization of a low latency, high-bandwidth interconnect serving a broad range of next-generation high-performance electronic industry applications

Joined by Tens of World Technology Leaders

From …

… to


Dave Tanis

Delete Chip-to-Chip as we now have HTX in addition to c2c connectivity.


HyperTransportTM

Processor-to-Processor, Processor-to-I/O,Processor to High-Performance Peripherals Interconnect

Best End-User Performance• CPU Native• Lowest Latency• Highest Bandwidth

Broad System Scalability• 2-Bit to 32-Bit Links• Asymmetric Links Support• Easy Multiprocessor Scalability

Minimum Silicon Deployment• Less Control Logic• Less Power Consumption

Industry answer to:

HyperTransport Profile

HTX TM

HTXTM Connectivity

Lowest Latency Direct ConnectBetween CPU(s and Peripherals viaStandardized Direct HyperTransport Links• 16-Bit or 8-Bit Wide• 6.4GB/s Bandwidth

Eliminates Performance Bottlenecks of Compute-IntensivePeripherals and Co-Processing Subsystems


Core DifferentiatorsHyperTransportTM

(*)

(*)

HyperTransport Profile (cont.)


Adopted by Technology Leadersin Widest Range of Market Segments



Market Statistics


Summary Forecast of Worldwide HyperTransport Systems – 2003-2009(Units in Thousands)

Source: In-Stat 8/05


Interconnect Landscape

High Performance Interconnect Evolution

HyperTransport Delivers Widest Application Latitude


Server Clustering

Standard InterconnectsWeave Off-the-Shelf Servers into

Powerful Scalable Clusters

Server Clustering MakesHPC a Commodity!

Major Industry TrendsMajor Industry Trends Bank on HyperTransport

• Core Compute and Storage Functionality• No Legacy I/O Control Subsystem• Clustered via High-Bandwidth Low Latency Multi-Gb/s Interconnect• Cost Saving Times “n” Factor• Reduced Power Consumption• Increased Reliability

Localized Legacy I/O Processing

Performance/Cost-OptimizedData-Center Servers


High-Performance Co-Processing Functions

Compute-Intensive Applications Served byStandard CPU Platforms Tightly Coupled With

Application-Specific Co-Processing Subsystems

Commodity-Level SystemsMinimize TCO

Co-Processing ApproachTailors Performance to Application

at Optimized System Cost

Target Markets

Low Latency ClusteringSecurity Monitoring

Network Protocol AnalysisAlgorithm Acceleration Storage ManagementEncryption/Decryption

Others

Major Industry Trends Bank on HyperTransport

HTXConnector

DDR Memory

Others

DDR Memory

VacantOpteronSocket


200M HT PortsShipped

Technology Milestones

2001

HT 1.0

HT 2.0

2002

2004

2003

2005

HT 1.1

HTXConnectivity

30M HT PortsShipped

2006

HyperTransport Evolution

HT 3.0


Why HyperTransportTM 3.0?

• Need for Lowest Latency and Highest Bandwidth• Server Clusters• Parallel Processing• Co-Processing

• Design Flexibility• Direct Cross-System Processor-to-Processor Interconnects• Simplified Interconnect Protocol• Intelligent System Configuration

• Escalating Power Consumption Concerns

• Lower Total Cost of Ownership• Fewer Technologies Inside and Outside the Box• Higher Reliability

• Support for Next Generation Processors• Higher Throughput• More Interconnect Links

HyperTransport Evolution (cont.)


HyperTransport 3.0State-of-the-Art Specifications

• 1.8 GHz, 2.0 GHz, 2.4 GHz and 2.6 GHz Clock Support• 41.6 GB/s Aggregate Bandwidth• 20.8 GB/s (166.4 Gb/s) per Link

• DC Operating Mode Enhancements• AC Operating Mode (Optional)

• Supports Applications Requiring Greater Signal Interconnect Distance• Cables• Backplanes• Larger Physical Systems• Chassis-to-Chassis Interconnects

• DC/AC Auto-Configuration• Link-Splitting/Un-Ganging Mode (Optional)

• Auto-configuration of Bi-Mode 2x8 or 1x16 Links• Hot Plugging

• Backplanes Applications• Power Management Enhancements (Optional)

• Support Dynamic Link Frequency and Width• 100% Backward Compatibility

• Auto-Configuration at Boot-Up with Minimum Spec Common Denominator Selection

State-of-the-Art Specifications

Same Features as HT 2.0 Plus:


Doubling Performance - Again (*)

HT 3.020.8 GB/s(Aggregate)

HT 2.011.2 GB/s(Aggregate)

Twice HyperTransport 2.0’s 16-bit ThroughputWith No Increase in System Design Complexity

and Real Estate Penalty/Cost

State-of-the-Art Specifications (cont.)

1.4 GHz 1.8 GHz 2.0 GHz 2.2 GHz 2.4 GHz 2.6 GHz Clock

(*) HyperTransport 2.0 Doubled HyperTransport 1.x Performance in February 2004


DC Operational Mode Enhancements


• Transmitter• Enhanced Training Pattern Tolerates Multi-Bit Skew• Added Scrambling Enables Rx Phase Alignment• Retained Clock Forwarding Scheme on Dedicated Lane(s)

• Maximized System Performance Predictability – Scales with System Architecture

• Receiver• Enabled Use of Rx Equalization• Support for Multi-Bit Skew Through Clock-Based Rx Phase Alignment

• 100% Backwards Compatible• Runs in HyperTransport 1.x and 2.0 Mode when New Features Not Enabled


AC Operating Mode - Optional


Significantly Extends HyperTransport Usability Latitude

Inf

• Supports Backplane, Board-to-Board, Chassis-to-Chassis Implementations

• AC-Coupling Capacitors• 8B/10B for DC Balance• Tx Equalization• Lower Bandwidth, Higher Latency

than DC Mode• Enabled when Needed – Best of Both Worlds

Transmit with Pre- and Post-Cursor De-Emphasis


DC/AC Auto-Configuration


• Between Existing Low-Latency DC Mode and New Long-Reach AC Mode

• Circuitry Detects Presence of Coupling Capacitors

• Auto-Switches to AC Mode

• Allows System Vendors to Connect the Same HyperTransport Device in DC Mode for Short Runs and AC Mode for Long Runs

DC

Coupling

AC

Coupling


Link-Splitting Mode - Optional(Un-Ganging)


• Auto-Configuration of Bi-Mode 2x8 or 1x16 Link Width• More HyperTransport Ports Useful in Topologies Such As

Symmetric Multi-Processing (SMP)• Required by Vendors Interested in Dual-Mode Interfaces

2x 8-Bit Links1x 16-Bit Link


Link-Splitting + AC ModePowerful Multi-processor Expansion Capability


8-Bit DC HyperTransport Links16-Bit DC HyperTransport Links

HTX

ConnectorI/O

CPU CPU

CPU CPU

To otherCPU subsystems

To other CPUsubsystems

Chassis 1

HTX

ConnectorI/O

CPU CPU

CPU CPU

To otherCPU subsystems

To other CPUsubsystems

Chassis n

16-Bit AC HyperTransport Links

Max 3.0clock speedwith cables

up to 1m in length


Hot Plugging


• Ability to Add /Remove Devices from HyperTransport Fabric Without Disrupting Other Operations

• Defined Link Termination Methods• Transaction Termination Behaviors• Sync Flood Isolation• Link Training Times

• Parameter Configuration Mechanisms

Important in High-Availability Applications,Server and Storage Markets


Power Management Enhancements - Optional


• Dynamic Link Frequency and Width• Allows Implementation to Dynamically Change

Frequency and Width of a Link

• Rapid Pause-Change-Start Support• Implements in Hardware

Answer to Increasing Importance of Power Consumption


Meeting Present and FutureApplication Requirements

• Aggregate Bandwidth 8.0 GB/s 41.6 GB/s 520%

• Link Width 16-bit 32-bit 100%

• Clock Speed 1.0 GHz 2.6 GHz 162%

• Operational Mode DC DC or AC Distance

Max Use Max Capable At Present 3.0 Specs Headroom

HyperTransportTM



HyperTransport 3.0 Already In Demand

Where from Here

• HPC System Manufacturers Consider HT 3.0 Highly Strategic for Next-Generation Product Roadmap

• Vastly Improved Processor-to-Processor Interconnect Flexibility and Performance

• In-Chassis and Chassis-to-Chassis• Optimized Parallel Processing Operations• SMP Architectural and Cost Optimization

• Server and High-Performance Workstation Companies Regard HyperTransport 3.0 as Painless Path to Performance Doubling of 16-Bit Link Designs without Added System Design and PCB Real Estate Complexity


Questions and Answers

Introducing HyperTransport 3.0All product trademarks included in this presentation are the property of their respective owners

For more information about HyperTransport technologyplease visit the “Technology” page on our Consortium’s web portal at

www.hypertransport.org

or call us at 925-968-0220

www.hypertransport.org 1 extreme interconnect performance extended applicability may 16, 2006...

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