wu, jinyuan fermilab sept. 2012

A Digitization Scheme of Sub-uA Current Using a Commercial Comparator with Hysteresis and FPGA-based Wave Union TDC

Wu, JinyuanFermilabSept. 2012

Sept. 2012, Wu Jinyuan, Fermilab [email protected] A Sub-microampere Digitization Scheme 2

Introduction A current-to-frequency converting oscillator built

with an ADCMP605+2R+C. Small current input can be directly interfaced

without pre-amplifier. Variations of current are translated into output

frequency. FPGA Wave Union TDC with measurement

resolution 25-30 ps can be used to measure times of comparator output logic transitions.

The Current to Frequency Converting Oscillator



The Current to Frequency Converting Oscillator

The input to the hysteresis causes variation to the high and low thresholds of the comparator. The oscillation frequency changes accordingly. The input waveform can be reconstructed from the logic transition times.

-+HYS

-+HYS

InVout

Vo+

InVo-


The Comparator Devices

ADCMP601 and ADCMP605 are comparators with hysteresis input. Small variations of input current in HYS pin translated into hysteresis voltage changes. The fully differential topology with ADCMP605 was used in our test.


The Input Current and the Output Frequency

When input current changes, out oscillating frequency deviating from nominal oscillating frequency.

The input amplitude used here is significantly larger than normal operation for demo purpose.

The Wave Union TDC Implemented in FPGA



TDC Using FPGA Logic Chain Delay

This scheme uses current FPGA technology

Low cost chip family can be used. (e.g. EP2C8T144C6 $31.68)

Fine TDC precision can be implemented in slow devices (e.g., 60 ps in a 400 MHz chip).

IN

CLK


Two Major Issues In an FPGA TDC

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1. Widths of bins are different and varies with supply voltage and temperature.

2. Some bins are ultra-wide due to LAB boundary crossing


Wave Union Launcher A

In

CLK

1: Unleash0: HoldWave UnionLauncher A

Regular TDC records only one transition

Wave Union TDC records multiple transitions.


Wave Union Launcher A: 2 Measurements/hit

1: Unleash


Output Raw Data and Typical Delta T Histogram Between Two Channels

RMS of this histogram is 25 ps.

00003CC064A6F064B8C07CA4F07CB4C094A0F094B0C0AC9CF0ACACC0C497F0C4A8C0DC91F0DCA2

Bench-top Tests



Test Hardware

An ADCMP605 + 2R, 1C are used to build a current controlled oscillator. The output and oscillator network are fully differential. Nominal sampling rate: 50-60 M samples/s.


Waveform Digitization Result

Times of oscillating transition edges are measured.

Both periods between positive and negative edges are calculated and their deviations from the nominal period are converted to current.

The input pulse is a single cycle sine wave with peak current 200 nA and base width 2x200 ns.

Charge movement of the pulse: +-200 nA x 200 ns x 0.64 = +- 25 fC.


Measurement Resolution

For DC input current, the oscillator timing jitters for transition edges are measured. Pulse width RMS jitter: 280 ps. Period RMS jitter: 470 ps.

The FPGA TDC’s with measurement resolution better than 25 ps fulfill the requirements easily.


Trade-off Between Sampling Rate and Resolutions Consider time interval T(n) between edge 0

and edge n. Sensitivity: DT(n)/DI ~ n Timing jitter: s(T(n)) ~ sqrt(n)

Faster sampling rate: Coarser s(I) Finer s(Q)

Slower sampling rate: Finer s(I) Coarser s(Q)

The users can choose post process to suit their application.

DI=250nA

DI=30nADt=1000ns

Dt=16ns


Resolutions and Sensitivities of Different Transitions

Each band of the M1 plot represents the transition time. Vertical axis scale of M1: 2 us (the full scale of the left screen shot) Slower sampling rates make current measurements with better resolutions. FYI: M1 = CH1*AND(CH3>1.24,CH3<1.26) (Note: CH3 and CH4 50% level = 1.25V)

2us

2us


Performance of a Test

Sampling rate 53 M samples/s

Current-to-time conversion ratio 5.9 ns/uA

Timing jitter of the pulse width (RMS) 281 ps

Current measurement resolution at 53 M samples/s (RMS) 47 nA

Current measurement resolution at 1 M samples/s (RMS) 6.5 nA (Estimate)

Product of 3-sigma current * sampling period 2.7 fC

Power consumption (Oscillator) 37 mW/channel

Power consumption (TDC) 27 mW/channel

This is only a preliminary test. Not every drop of oil is squeezed out. Rooms for improvements and optimization are clearly available. Colleagues are encouraged to try different configurations.

Open-Loop Gain vs. Deep Negative Feedback



Deep Negative Feedback

Analog electronics has been based on deep negative feedback. We subconsciously apply deep negative feedback when we design analog circuits. Amplification ability is traded-off for better gain stability, linearity and flat bandwidth.

-+


ADC w/ Comparators: Taking Advantage of Open-Loop Gain

In digitization tasks, the primary requirement is to translate analog input into logic levels before it is contaminated by the noise.

All nonlinearity, gain variation etc. can be calibrated in digital domain. In this example, the input voltage is compared with a known ramping reference voltage. When reference voltage passes through the input level, the comparator amplifies the voltage

difference with its open-loop gain.

-+

InVout

A Collection of Examples



Ramp-Compare (Single Slope) ADC

The input voltage is compared with a known ramping reference voltage.

The input is sampled at fixed rate and the waveform can be reconstructed from the logic transition times of the comparator output.

Both single-ended and differential versions are available.

The FPGA LVDS input buffers can be used as the comparators and multi-channel ADC’s can be implemented with minimum external components. (4 resistors/CH for differential version.)

-+

-+

InVout

Vo+

In+

Vo-

In-

7-bit @ 62.5 MHz


The Duty Cycle Modulation Oscillator

The pulse widths depend on the input voltage level. The oscillator circuit is self-contained without external supports and is suitable for remote

operation.

-+HYS

InVout


Time Over Threshold (TOT)

The leading edge time of the input pulse is accurately captured. Pulse width is correlated with the pulse charge. The FPGA LVDS input buffers can be used as the comparators. Multi-channel T&Q measurements can be implemented in FPGA without external

components.

-+In Vout


Dynamic Time Over Threshold (DTOT, TODT)

The leading edge time of the input pulse is accurately captured. The pulse width is nearly linearly correlated with total charge. Better signal to noise ration (S/N) is anticipated.

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InVout

FF


Time Over Oscillating Threshold (TOOT)

The leading edge time of the input pulse is accurately captured. The circuit is simpler than TODT. Multiple points are sampled on the pulse waveform.

InVout

-+HYS


Summary Tests are performed with ADCMP605 oscillator. Current measurement resolution of 47 nA (RMS)

is achieved at 53 M sample/s, 6.5 nA (RMS) at 1 M samples/s is anticipated.

At 53 M samples/s, the product of 3-sigma current x sampling period is 2.7 fC.

Power consumptions for the oscillator and TDC are 37 mW and 27 mW/channel, respectively.

The End

Thanks


Wave Union Launcher B

Wave UnionLauncher B

In

CLK

1: Oscillate0: Hold


Cell Delay-Based TDC + Wave Union Launcher

Wave UnionLauncher

In

CLK

The wave union launcher creates multiple logic transitions after receiving a input logic step.

The wave union launchers can be classified into two types:

Finite Step Response (FSR) Infinite Step Response (ISR)

This is similar as filter or other linear system classifications:

Finite Impulse Response (FIR) Infinite Impulse Response (IIR)


Wave Union Launcher A

1: Unleash0: HoldIn

CLK

Wave Union?

Photograph: Qi Ji, 2010Sept. 2012, Wu Jinyuan, Fermilab [email protected] 34A Sub-microampere Digitization Scheme


A Current to Frequency Converter

The

-+HYS

-+HYS


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Auto Calibration Using Histogram Method It provides a bin-by-bin calibration at

certain temperature. It is a turn-key solution (bin in, ps out) It is semi-continuous (auto update

LUT every 16K events)

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DNLHistogram

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16KEvents


Good, However

Auto calibration solved some problems However, it won’t eliminate the ultra-wide bins

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Sub-dividing Ultra-wide Bins

1: Unleash

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Device: EP2C8T144C6 Plain TDC:

Max. bin width: 160 ps. Average bin width: 60 ps.

Wave Union TDC A: Max. bin width: 65 ps. Average bin width: 30 ps.

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Plain TDC

Wave Union TDC A

wu, jinyuan fermilab sept. 2012

Documents

wu jinyuan

fermilab jyw

small current input

variations of current

hysteresis input

fpga wave union tdc

introductiona current

input amplitude