work in progress --- not for publication erd wg 3/18/09 brussels, belgium fxf meeting1 2009 itrs...

Work in Progress --- Not for Publication ERD WG 3/18/09 Brussels, Belgium FxF Meeting 1

2009 ITRS Emerging Research Devices

Working Group

Face – to – Face Meeting

Jim Hutchby – FacilitatingDolce La Hulpe Brussels Hotel

135, Chaussée de Bruxelles, 1310 La Hulpe, BELRoom – Mahogany

(Near) Brussels, BelgiumWednesday, March 18, 2009

8:00 a.m. – 5:30 p.m.


Hiroyugi Akinaga AIST Tetsuya Asai Hokkaido U. Yuji Awano Fujitsu George Bourianoff Intel Michel Brillouet CEA/LETI Joe Brewer U. Florida John Carruthers PSU Ralph Cavin SRC An Chen AMD U-In Chung Samsung Byung Jin Cho KAIST Sung Woong Chung Hynix Luigi Colombo TI Shamik Das Mitre Erik DeBenedictis SNL Simon Deleonibus LETI Kristin De Meyer IMEC Michael Frank AMD Paul Franzon NCSU Akira Fujiwara NTT Christian Gamrat CEA Mike Garner Intel Dan Hammerstrom PSU Wilfried Haensch IBM Tsuyoshi Hasegawa NIMS Shigenori Hayashi Matsushita Dan Herr SRC Toshiro Hiramoto U. Tokyo Matsuo Hidaka ISTEK Jim Hutchby SRC Adrian Ionescu ETH Kohei Itoh Keio U. Kiyoshi Kawabata Renesas Tech Seiichiro Kawamura Selete

Rick Kiehl U. Minn Suhwan Kim Seoul Nation U. Hyoungjoon Kim Samsung Atsuhiro Kinoshita Toshiba Dae-Hong Ko Yonsei U. Hiroshi Kotaki Sharp Atsuhiro Kinoshita Toshiba Franz Kreupl Qimonda Nety Krishna AMAT Zoran Krivokapic AMD Phil Kuekes HP Jong-Ho Lee Kyungpook Nation U. Lou Lome IDA Hiroshi Mizuta U. Southampton Fumiyuki Nihei NEC Ferdinand Peper NICT Yaw Obeng NIST Dave Roberts Air Products Kaushal Singh AMAT Sadas Shankar Intel Atsushi Shiota JSR Micro Satoshi Sugahara Tokyo Tech Shin-ichi Takagi U. Tokyo Ken Uchida Toshiba Yasuo Wada Toyo U. Rainer Waser RWTH A Franz Widdershoven NXP Jeff Welser NRI/IBM Philip Wong Stanford U. Kojiro Yagami Sony David Yeh SRC/TI In-Seok Yeo Samsung In-K Yoo SAIT Peter Zeitzoff Freescale Yuegang Zhang LLLab Victor Zhirnov SRC

Emerging Research Devices Working Group


Review Administrative Aspects Deliverables, Timeline, and Next Steps Proposed Chapter Outline and Page Count/Allocation Technology Entry Inclusion Criteria

Broadly inclusive Maturity Metric (current publications)

Review Major Decisions Hiramoto-san, U-In Chung, and Adrian Ionescu agree to serve as

co-chairs of ERD with Jim Hutchby as chair. Guiding Principles – In the 3rd principle change “Novel Energy

Transfer …” to “Novel Information Transfer…” Begin to merge Memory technologies with Storage technologies

in 2010. Enter Carbon-based Nanoelectronics as a potential solution

2009 ITRS ERD Chapter Preparation Business Meeting Objectives (1/3)


Decide Structure & Major Technical Entries for Memory, Logic and Architecture Sections Factors considered

Structure Content (particularly proposed numerical content) considering 1)

Current experimental values, and 2) Long term potential values/goals for quantitative metrics

Decide Technology entries (drop/add/move to Transition Table) Sections

Logic Devices (including relevant materials issues w/ ref. to ERM) Memory Devices (including relevant materials issues w/ ref to ERM) Emerging Research Architectures (Decide approach for Architecture

Section and build a strong connection between Logic & Architecture Sections).



Review/critique each Technology Entry Major barrier and/or weaknesses Requirement(s) for new materials Most important research questions to be addressed (materials

and device structure) Level of risk and anticipated maturation time

Decide Critical Assessment & Guiding Principle Sections Critical Assessment

MemoryLogic

Guiding Principles – “Beyond CMOS” Discuss Proposal for Highlighting Promising Options for

Emerging Memory Technologies



7:30 Gathering time 8:00 Introductions 8:10 Review meeting objectives and agenda Hutchby 8:20 Review of Administrative Aspects Hutchby

Deliverables, Timeline, Events, & Next Steps Chapter Outline, Page Count & Allocation Cross TWG Linkages & Meetings

8:30 Review/Discuss Status of Major Tech Sections Section outline Table structure (Row headers, etc.) Table Content (Current & projected tables) Key materials issues

8:30 Memory Devices Zhirnov10:00 Break

ITRS ERD WG Meeting – March 18, 2009Agenda


10:15 Logic Devices Bourianoff11:45 MASTAR Readiness for III-V & Ge MOSFETs Ng12:00 Lunch12:30 Emerging Research Materials Garner 1:30 Architectures Cavin 2:30 Discuss/Decide Difficult Challenges Hutchby 3:15 Discuss Evaluation & Guidance Sections

3:15 Critical Assessment Hutchby 3:45 Guiding Principles Hutchby

4:00 Discuss Proposal for Highlighting Promising HutchbyOptions for Emerging Memory Technologies

4:45 Review ERD/ERM Beyond CMOS IRC Pres. All 5:25 Wrap up and Review Actions Required All 5:30 Adjourn

ITRS ERD WG Meeting – March 18, 2009Agenda


Draft ERD Chapter Outline Scope (1 page) Difficult Challenges (1) Taxonomy Chart (1) Devices

Memory Devices (13) Logic Devices (15)

Architectures (10) Critical Assessment (6) Fundamental Guiding Principles (3) Total Pages (50)

DRAFT


Proposed 2009 ERD Working Group OrganizationERD Function Leader

Chapter Chair – North America Hutchby Chapter Co-chair – Europe Ionescu Chapter Co-chair – Japan ERD Hiramoto Chapter Co-chair – Korea ERD Chung Memory Zhirnov Logic Bourianoff Architecture Cavin Editorial Team Hutchby, Bourianoff, Cavin,

Chung, Garner/Herr, Hiramoto, Ionescu, Zhirnov

ITRS Liaisons– PIDS Ng, Hutchby– FEP Colombo– Modeling & Simulation Shankar/Das– Materials Garner– Metrology Herr/Obeng– Design Yeh/Bourianoff– More than Moore Brillouet

New in 2009


2009 ITRS/ERD Major Deliverables and TimelineERD Chapter due August 21, 2009 Changed in San FranciscoMajor Tasks and Time Line Outlines for Memory, Logic, Architecture, Mat’l March 18 Technology Requirements Tables July 1 Guiding Principles Section March 18 Draft Text Completed

Memory, Logic, Architecture, Material June 6 Functional Organization & Critical Review July 20 Scope, Difficult Challenges, etc. July 27 Chapter Completed August 21 Chapter Frozen Sept. 15

Major Face-to-Face Meetings in 2009 ITRS/ERD Meeting near Brussels, Belgium March 18 ITRS/ERD Meeting at Semicon West (SF, CA) July 12 ERD/ERM Meeting at IEDM in WashingtonDec. 6 ITRS/ERD Meeting near Hsinchu, Taiwan Dec. 13


Decisions for 2009 Chapter

♦ Memory– Include device structural aspects of the new NW PCRAM in ERD with a summary

of the materials issues. Include more materials information in ERM on this topic.

– Include the Spin Torque Transfer MRAM in ERD/ERM.

– We will not include “Storage” technologies in 2009, but will begin to merge “Memory” and “Storage” technologies in 2010. At that time we will begin to include the “Magnetic Domain” or “Racetrack Memory” in ERD.

– We will keep nanomechanical memory in ERD Memory Table.

– Move the Ferroelectric Effects Tunneling Barrier Memory from the Electronic Effects Memory category to the Memory Transition Table

– Leave “Redox type” memories in the ERD. These are different than ionic cation migration effects memory.

– By categorizing using a physics-based system, a given material that exhibits 2 or more effects will be listed in each category.

– Drop the Charge Trapping Memory as a Technology Entry – move to Transition Table?

– Drop the Capacitive Memory Table


Decisions for 2009 Chapter♦ Logic

– We will have 3 Logic tables in 2009. They will be titled:

• Table 1: “MOSFET: Extending the Channel of MOSFETs to the End of the Roadmap”

• Table 2: “Non-Conventional FET, Charge-based Extended CMOS Devices”

• Table 3: “Non-FET, Non Charge-based ‘Beyond CMOS’ Devices”– ERD/ERM recommends carbon-based nanoelectronics to include CNT,

graphene for more resources and roadmapping for IRC as part of promising technologies for 5-10 years demonstration horizon

– Carbon-based nanoelectronics will be included in the 2009 ERD chapter via a two new Potential Solutions tables – for materials and for device issues.

– Seven potential technologies were considered:1. Carbon-based Nanoelectronics2. Collective spin3. Spin torque transfer4. Atomic and electrochemical metal5. CMOL/FPNI6. Single Electron Transistor7. NEMS


Action Items (1/3)1. Consider to include in the 2009 ERD Chapter the new chart entitled

“Evolution of Extended CMOS” contributed by ERD Japan.Bourianoff In Process

2. Strengthen ties between US-EU-Asia. Requires good balance of representing members from three regions

Hutchby In Process

3. The best demonstrated parameters are obtained from different devices. Is it possible to obtain them simultaneously on one device? We should include a note to this effect.

Bourianoff, Zhirnov Decided to not change; include note

4. Extend the Mission of ERD to include additional Research Vectors proposed by the Japan ERD WG. These are Numbers 1 – 4 listed in Item No. 1 above.

Bourianoff IPWGN Task

5. Consider moving to PIDS in 2009: 1) III-V Alternate Channel Materials, and 2) Low Dimensional Materials. Discuss this with PIDS. (This discussion has begun.)

Bourianoff In Process

6. Make the mission of ERD clear. Make it more Globally justified. Hutchby

7. Organize an ERD Working Group in Korea In U. Chung Completed


Action Items (2/3)8. Bob Doering argued that the Critical Evaluation Chart gives the

wrong message;a.We need to re-think this chartb.This chart assigns a different meaning to red than is used by all the other ITRS chapters. The other chapters use red to highlight a major research gap.c.We should point the directions into which “critical path” research should be directed.

We need a way to distinguish a Fundamental Limit versus the Maturity of the Technology Entry

Hutchby In Process

9. Need a dialog with the Design and Systems Drivers ITWG to address synergy between the two chapters.

Hutchby, Bourianoff, Yeh

In Process

10. Discuss/decide upon expanding scope to include Sensors, Actuators, and Power Sources to encompass More than Moore or Functional Diversification

Hutchby and Brillouet

Decided to not do this in 2009

11. Discuss other materials (in addition to NiO) for Fuse/Anti-fuse Memory Tech

Zhirnov & Garner In Process

12. Plan Memory FXF Meeting in Germany for April 2, 2008. Include Memory Expert Panel.

Zhirnov Done

13. Write paper/proposal for NSF Funding for workshops. Hutchby/Zhirnov Done

14. Include Akinaga-san in Memory Working Group Zhirnov Done


#

1. Set up biweekly ERM/ERD editorial/driver team meetings (See proposed times for these meetings below)

Hutchby

2. Discuss and create a draft of a STTRAM potential solution table Yeo and Yoda3. Develop a process for reviewing Memory Technology Entries to

present to the IRC for their direction regarding highlighting for more detailed roadmapping.

Hutchby and ERD/ERM

3. Discuss Storage or Mass Memory Technology at SF Meeting. Korean ERD would like us to reconsider including Mass Memory/Storage in the ERD Chapter

Hutchby

4. Continue discussions with PIDS regarding PIDS bringing STTMRAM into the PIDS chapter

Hutchby

5. Set up bi-weekly Telecoms Hutchby6. Create a Potential Solution Table for STTMRAM Bourianoff, Yeo,

Chung7. Dr. H. S. Hwang is a new Volunteer for the ERD Memory Team Chung8. Dr. Ko will contribute to CNTs, III-V, GNR9. Prepare recommendation regarding More than Moore Brillouet Nov. 3010, Discuss with Alan Allan the possibility of putting the Japanese ERD

chart in the Executive SummaryHutchby Mar. 18

11. Use colors in the ERD/ERM Critical Review that are consistent with the other chapters of the Roadmap

Hutchby

12. Send to Mike Garner a reference to an IBM/Zurich paper on conformational change in molecules to modify tunnel barrier

Waser

13. Update report on Molecular Devices – Discuss in Mar. 18 meeting Waser, Zhirnov Mar. 18

Action Items (3/3)


Backup Slides


2009 ITRSEmerging Research Devices

Editorial – Driver Team Meeting

Charter and Scope

George BourianoffMike GarnerJim Hutchby Victor Zhirnov

Santa Clara, CAOctober 13, 2004

Edited December 10, 2006


Charter of ERD ChapterOn behalf of the 2009 ITRS, develop an

Emerging Research Devices chapter to -- Critically assess new approaches to Information

Processing technology beyond ultimate CMOS Identify most promising approach(es) to Information

Processing technology to be implemented by 2024

To offer substantive guidance to – Global research community Relevant government agencies Technology managers Suppliers


Scope of ERD Chapter

Integrated emerging research memory, logic and new architecture technologies enabled by supporting -- Materials and process technologies Modeling and simulation Metrologies

Selection of specific technical approaches shall be Guided by fundamental requirements Bounded by ERD’s topic selection criteria


Scope of ERD Chapter Criteria for Including Technology Entries

Devices and Architectures – Published by 2 or more groups in archival literature and peer

reviewed conferences, or Published extensively by 1 group in archival literature and peer

reviewed conferences Technology Entry (by itself or integrated with CMOS) must

address a major electronics market. Materials and Fabrication Technologies – Materials and processes that address the specific material needs

defined by emerging research device technology entries Supporting disciplines – specify for crosscut TWGs

Metrologies Modeling & simulation


State Variable

Device

Data Representation

Architecture

Material

CNT FETs

Molecular

Spintronics Quantum

Scaled CMOS Ferromagnetic

Quantum

Analog

Digital

Reconfigurable

Cellular arrays

Boolean

Silicon

Carbon NTs

Macro molecules

Complex metal oxides

Quantum qubit

Spin orientationMolecular state

Electric charge Bio inspiredPhase state

Phase state

Linear

Nanowires

Con

vent

iona

l Sca

led

CM

OS

New

Info

rmat

ion

Proc

ess

Tech

nolo

gies

A Taxonomy for Nano Information Processing Technologies

Work in Progress --- Not for Publication22 ERD WG 3/20/09 Brussels IRC FxF Meeting

ERD ITWG Emerging Research Devices

Working Group

Proposal for Assessing Technology Options for Emerging

Research Memory Devices

Jim Hutchby & Mike Garner Friday March 20, 2009


Objective of IRC/ERD/ERM discussion of this request from Samsung, Hynix, and Micron

ERD/ERM is seeking IRC guidance on whether we should conduct a review and assessment of emerging research memory technologies with the goal of recommending those most promising for detailed roadmapping and accelerated research.♦ Assess technology capability of being scaled beyond the

15nm node.♦ Identify precompetitive research required for top

candidates to scale beyond the 15nm node♦ Process will be completed in April 2010 with an oral report

to the IRC in the Spring ITRS Meeting followed by a written report/recommendation to the IRC.


Assessment of Promising Emerging Memory Devices

• Samsung, Hynix , and Micron proposed that the ERD/ERM identify memory technologies needing more focused support

• Proposal: ERD & ERM hold a workshop in April 2010 to review and assess emerging research memory devices– Goal: Identify emerging research memory technologies that merit

more detailed roadmapping and more focused research.– Process: Same Process as the Logic Assessment in 2008

• Champions present Pros, Cons and research needed for technology• Friendly critic presents balanced assessment• White paper prepared on each memory and circulated prior to the

meeting• Face to Face Presentations & Discussion• Voting on Promising Technology• Identify Critical Research Needed

Work in Progress --- Not for Publication25 ERD WG 2/26/2009

Straw Candidate Emerging Research Memory Technologies

Capacitive Memory FeFET Memory

Resistive Memory Nanoelectromechanical STT MRAM Thermal PCM

FUSE/Anti-FUSE Nanowire PCM

Electrochemical Memory Cation migration Anion migration

Electronic Effects Memory Charge trapping Mott Transition FE barrier effects

Macromolecular Memory Molecular Memory


DRAFT GOALWith the goal of providing input to resource allocation decisions, ERD/ERM WGs will conduct an in-depth review and assessment of specific emerging research memory devices to highlight the most promising device technologies for detailed roadmapping and acceleration of pre-competitive*research and development.

(*Pre-competitive refers to those technologies capable of being scaled beyond the 15nm node.)


DRAFT SCOPE

The scope of the review of emerging research memory technologies will assess scalability beyond the 15nm node. – Identify precompetitive research needed to enable

scaling beyond the 15nm node.– Assessment will encompass both stand-alone and,

where different, embedded emerging research memory technologies.


Draft Timetable1. Develop/decide process, milestones, timeline July 12, 2009

2. Develop invitation to advocates/proponents & friendly critics Introduction Potential of technology – fundamental limits Barriers – Fundamental vs. technological/engineering Evaluation Criteria Definition of specific emerging research memory devices for roadmapping Readiness in 10 - 15 years

July 31

3. Identify Major emerging research memory device candidates Strong technical proponent and friendly critic teams and their leaders Knowledgeable ERD/ERM mentor for each proponent team Key questions to be addressed by the teams Background materials for each technical candidate

July 31

4. Issue invitations to team leaders, friendly critics, and ERD/ERM mentors and obtain their commitments

Sept. 15

5. Obtain a white per & background materials from each candidate technology proponent team for ERD/ERM WG review

Jan. 15, 2010

6. ERD/ERM WG review candidate emerging research memory devices candidates based on white papers & identify key questions using a formal process prior to Spring Europe FxF meeting.

Mar. 15, 2010

7. Conduct a FxF review of categories with each proponent & friendly critic making a presentation

April yy, 2010Spring FXF Mtg.

8. On second day of ERD FxF meeting, discuss/decide ERD/ERM WG’s prioritized recommendation of narrowed emerging research memory devices options. This will include selection of specific devices for roadmapping within the recommended option

April yy+1,2010Spring FXF Mtg.

9. Write & submit report on ERD/ERM WG’s recommendations May 31, 2010


Proposed ERD/ERM WG Process for Assessing Candidate Emerging Research Memory Device Technology Options

Develop/decide process, milestones, timeline Develop invitation to advocates & opponents

Introduction Potential of technology – fundamental limits Barriers – Fundamental vs. technological/engineering Evaluation Criteria / Benchmark memory technology Definition of maturing, high potential specific devices

for roadmapping Readiness in ~ 5 - 10 years



Identify Major emerging research memory technology candidates Strong technical proponent and opponent teams and their

leaders Knowledgeable ERD/ERM mentor for each proponent

team Key questions to be addressed by the teams Background materials for each technical candidate

Issue invitations to team leaders and obtain their commitments

Obtain a white paper & background materials from each candidate technology proponent team for ERD/ERM review


Appendix 4a: Comparison of a NEM Relay with an ultimately scaled Si MOSFET Major Categories MOSFET NEM Relay

Basic description

Device Proposed Field Effect Transistor NEM RelayState variables and control Charge or Voltage Charge or Voltage

Number of logic states 2 (high and low) 2 (on or off)Principle of Operation Thermal injection over gate barrier Mechanical switching of currentMaterials Si Si, SiC, TiN, metals used in CMOS (top

down); CNT or NW (bottom up)Geometry Transistor, 3 or 4 terminal Mechanical relay: 3 or 4 terminal

Device density as a function of feature size F

~ 1/F^2 ~1/(F^2 x R) where F=gap=beam thickness. Lateral tech is assumed. R is aspect ratio.

Size in units of feature size F of a gate equivalent to a 2-input NAND gate, including contacts and isolation and necessary peripheral circuitry

>~65 F^2 >~10F^2xR (same assumptions as above , NAND =2x inverter area.)

Functonal Density in terms of "gate

equivalents" per cm2 using the primitive cell size defined above and an appropriate value of F.

Operating Parameters - Temp Usually 25C - 125C compatible with high-T electronicsOutput sensing device MOSFET RelaySelf gain gm/gd ~ Vdd/DIBL N/ASwitching Energy per gate or gate equivalent @ proposed clock rate

0.5*Cload*Vdd^2 0.5*(Cgap + Cload)*Vdd^2

Static Power Dissipation per gate or gate equivalent

Vdd*Ioff*(2/5) Essentially zero

Binary throughput (Gbits/nsec-cm2-joule)

Logic Family - Information processing basis

Universal set comprising NAND, NOR, NOT logic gates, also pass gates

Universal set comprising NAND, NOR, NOT logic gates, also pass gates

Interconnects Wire WireCompatible memory SRAM (fast) , DRAM (dense) SRAM (Fast) , DRAM (Dense), & NV M.

Clock or its equivalent CMOS based clock circuits Relay based clock circuitsCMOS compatible N/A Yes

Performance Potential

Switching speed & energy

Interconnect delay per micron

Limitations

External parasiticsNoise margin

This section comprises a description of the proposed device family. The section may include textual and graphical descriptions but should be independent of (or

parameterized by) feature size F

This section comprises an extrapolation of the technology to about the year 2020, stipulating F=14 nm. Provide best estimate numerical values.

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Appendix 4a: Comparison of a NEM Relay with an ultimately scaled Si MOSFET Major Categories

Basic description

Device ProposedState variables and control

Principle of OperationMaterials

Geometry

Operating Parameters - TempOutput sensing deviceSelf gain

InterconnectsCompatible memory

Clock or its equivalent CMOS compatible N/A Yes

Performance Potential

Switching speed & energy Lchan/v ~ 0.1ps Delay ~ ns range; Vdd ~ few 100mV, energy ~ aJ range

Interconnect delay per micron RC RCInterconnect energy as a function of distance at proposed clock rate

CV^2 CV^2

Limitations

Materials & Geometry - Sources of variability

LER, Doping fluctuations ~ 1/SQRT (LW) Gap, thickness, material properties, vdW forces

External parasitics Access resistance, fringe capacitance Fringe capacitanceNoise margin (Vdd-Vth)/ KT/q > 5 Better or comparable with CMOS

This section comprises a list of known limiting factors for performance and manufacturing

This section comprises an extrapolation of the technology to about the year 2020, stipulating F=14 nm. Provide best estimate numerical values.



Conduct a FxF review of categories with each proponent & friendly critic team making a presentation

On second day of ERD/ERM FxF meeting, discuss/decide ERD/ERM’s recommendation of most promising emerging research memory technology options. Mentors will lead the discussion of their candidate technology

Write & submit report to the IRC on ERD/ERM WG’s recommendations


Decision Making & Majority Voting Scheme Each member of ERD WG will be given a maximum of X votes to use

in voting for their top X choices among the candidate technologies (Majority Voting scheme) ERD/ERM WG members present in the FIRST DAY Workshop &

the SECOND DAY meeting will be eligible to vote at SECOND DAY meeting, based on their personal technical judgment, independent of their corporate affiliation or regional representation,

Only 0 or 1 vote can be cast for any candidate technology Member does not have to use all X votes, but cannot use more

than X votes. All members can participate in the straw vote.

The Candidate Technologies will be ordered according to which received the largest number of votes.

Consensus approval will be our goal, but a 75% affirmative vote will be required as a minimum. This is what is meant by the term approximate consensus.

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ERD “Beyond CMOS” Technology Selection MtgAgenda – SECOND DAY

9:20 Review Process for selecting beyond CMOS emerging technologies

9:45 Discuss Technologies 9:45 NEMS Switch Technology

10:05 Spin Torque Transfer Technology 10:25 Carbon-based Nanoelectronics

10:45 Break11:00 Atomic Switch / Electrochemical Metal Switch

11:20 Collective Spin Devices (including M-QCA) 11:40 Single Electron Transistors 12:00 CMOL and FPNI

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ERD “Beyond CMOS” Technology Selection Mtg Agenda – SECOND DAY (Cont’d)

12:50 Preliminary vote on technologies – Majority voting process

1:00 Discuss preliminary results

1:45 Second vote on technologies

2:00 Discuss the leading technologies resulting from vote

2:30 Final vote on the leading technology(ies) to determine if we have approximate consensus (75% of those voting) to recommend one or more for roadmapping and enhanced engineering development

2:45 Decide next steps in roadmapping the chosen technologies REDO T

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Work in Progress --- Not for Publication37 ERD WG 7/12-13/08 San Francisco Workshop & FxF Meeting

Decision Making & Majority Voting Scheme Each member of ERD WG will be given a maximum of 3 votes to use

in voting for their top 3 choices among the candidate technologies (Majority Voting scheme) ERD/ERM WG members present in the July 11 Workshop & the

July 12 FxF meeting will be eligible to vote at July 12 meeting, based on their personal technical judgment, independent of their corporate affiliation or regional representation,

Only 0 or 1 vote can be cast for any candidate technology Member does not have to use all 3 votes, but cannot use more

than 3 votes. All members can participate in the straw vote.

The Candidate Technologies will be ordered according to which received the largest number of votes.

Consensus approval will be our goal, but a 75% affirmative vote will be required as a minimum. This is what is meant by the term approximate consensus.

work in progress --- not for publication erd wg 3/18/09 brussels, belgium fxf meeting1 2009 itrs...

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